Abstract: Methods and apparatus for a novel memory array are disclosed. In an embodiment, a method is provided for reading a dynamic random-access memory (DRAM) array. The method includes activating the bit line select gates to equalize voltage levels on a plurality of bit lines, deactivating the bit line select gates to maintain the equalized voltage levels on the plurality of bit lines using a bit line capacitance associated with each bit line, and activating a selected word line to access selected memory cells connected to the selected word line. The method also includes activating bit line select gates to pass first data from a first bit line and second data from a second bit line to the sense amplifier. The first data is from a selected memory cell and the second data is reference data. The method also includes determining sensed data from the first and second data.

Abstract: A semiconductor memory includes, in part, M×N select transistors disposed along M rows and N columns, where M and N are integers greater than or equal to 2. The memory further includes, in part, a first set of M wells each configured to be biased independently of the remaining M?1 wells. Each well has formed therein N of the select transistors each having a source/drain terminal coupled to the same bitline corresponding to a different one of M bitlines of the memory. The memory further includes, in part, M×N anti-fuses. Each anti-fuse is associated and forms a bitcell with a corresponding one of the M×N select transistors.

Abstract: Since power source voltages are different depending on circuits used for devices, a circuit for outputting at least two or more power sources is additionally prepared. An object is to unify outputs of the power source voltages. A transistor using an oxide semiconductor is provided in such a manner that electrical charge is retained in a node where the transistor and a capacitor are electrically connected to each other, a reset signal is applied to a gate of the transistor to switch the states of the transistor from off to on, and the node is reset when the transistor is on. A circuit configuration that generates and utilizes a potential higher than or equal to a potential of a single power source can be achieved.

Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.

Abstract: Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.

Abstract: A memory device includes a memory array having a first memory cell in a first column of the memory array, a second memory cell in the first column of the memory array, a first read bit line extending in a column direction and connected to the first memory cell to read data from the first memory cell, and a second read bit line extending in the column direction and connected to the second memory cell to read data from the second memory cell.

Abstract: A physically unclonable function (PUF) circuit includes a program control transistor, a program select transistor, a read select transistor, and a PUF bit storage transistor. The PUF bit storage transistor has a drain region coupled to the read select transistor, a source region coupled to a source line and the program select transistor, a channel region, a gate dielectric layer, and a gate electrode coupled to the program select transistor. The gate dielectric layer has a first portion formed on the drain region, a second portion formed on the source region, and a main portion formed on the channel region and between the first portion and the second portion, thicknesses of the first portion of the gate dielectric layer and the second portion of the gate dielectric layer being smaller than a thickness of the main portion of the gate dielectric layer.

Abstract: A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.

Abstract: A method for the patterning and control of single electrons on a surface is provided that includes implementing scanning tunneling microscopy hydrogen lithography with a scanning probe microscope to form charge structures with one or more confined charges; performing a series of field-free atomic force microscopy measurements on the charge structures with different tip heights, where interaction between the tip and the confined charge are elucidated; and adjusting tip heights to controllably position charges within the structures to write a given charge state. The present disclose also provides a Gibb's distribution machine formed with the method for the patterning and control of single electrons on a surface. A multi bit true random number generator and neural network learning hardware formed with the above described method are also provided.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory blocks. The peripheral circuit performs a read operation on a selected memory block among the plurality of memory blocks. The control logic controls the read operation of the peripheral circuit. The selected memory block is coupled to a plurality of bit lines, and the plurality of bit lines are grouped into a plurality of bit line groups. The peripheral circuit performs data sensing by applying different reference currents to the plurality of bit line groups, respectively.

Abstract: A method of obtaining, in an electronic circuit, at least one first key intended to be used in a cryptographic mechanism, on the basis of at least one second key contained in the same circuit, the first key being stored in at least one first storage element of the circuit, the first storage element being reinitialized automatically after a duration independent of the fact that the circuit is or is not powered. Also described are applications of this method to encrypted transmissions, usage controls, as well as an electronic circuit implementing these methods.

Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

Abstract: A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed in a plurality of resistive states according to an electrical signal received. The upper electrode of the capacitive device is coupled to the second electrode of the resistive memory cell. The resistive memory cell is a two-terminal device.

Abstract: Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells.

Abstract: A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).

Abstract: A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays.

Abstract: An object is to increase the retention characteristics of a memory device formed using a semiconductor with a wide bandgap, such as an oxide semiconductor. A transistor including a back gate (a back gate transistor) is inserted in series at one end of a bit line so that the back gate is constantly at a sufficiently negative potential. The minimum potential of the bit line is set higher than that of a word line. When power is turned off, the bit line is cut off by the back gate transistor, ensuring prevention of outflow of charge accumulated in the bit line. At this time, the potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor (0 V), so that the cell transistor is put in a sufficiently off state; thus, data can be retained.

Abstract: Power management of an embedded dynamic random access memory (eDRAM) by receiving an eDRAM power state transition event and determining both the current power state of the eDRAM and the next power state of the eDRAM from the power states of: a power-on state, a power-off state, and a self-refresh state. Using the current power state and the next power state to determine whether a power state transition is required, and, in the case that a power state transition is required, transition the eDRAM to the next power state. Power management is achieved because transitioning to a power-off state or self-refresh state reduces the amount of power consumed by the eDRAM as compared to the power-on state.

Abstract: A 2.5D or 3D repair architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic has a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The control logic further comprises a wide input/output controller, a built-in-repair analyzer (BIRA), and a repair controller. A method utilizing the repair architecture provides for repairing failed columns and rows of a memory device.

Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.

Abstract: Large capacity memory systems are constructed using multiple groups of memory integrated circuits or chips. The memory system includes one or more interface circuits for interfacing between the multiple groups of memory integrated circuits and a memory controller. The interface circuit may detect and/or recover failed data using error-checking information stored in a memory integrated circuit.

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Abstract: A system for charging a low voltage power domain in a low power DRAM includes: a first capacitor, for providing a local domain power voltage supply; a first transistor, coupled to the first capacitor and a voltage supply and turned on by a powerdown signal, the first transistor for decoupling the first capacitor during powerdown mode, and charging the capacitor to provide the local domain power voltage supply when exiting powerdown mode; a second capacitor selectively coupled to the voltage supply or the local domain voltage power supply; and a second transistor, coupled to the second capacitor, the powerdown signal, and the local domain power voltage supply, for decoupling the second capacitor from the local domain power voltage supply during powerdown mode and coupling the second capacitor to the local domain power voltage supply when exiting powerdown mode.

Abstract: A memory device is provided. The memory device includes a plurality of memory cells and a controller to write data to and read data from the memory cells. Each memory cell includes a first semiconductor material having a spontaneous polarization, a resistive ferroelectric material having a switchable spontaneous polarization, and a second semiconductor material having a spontaneous polarization, the resistive ferroelectric material being positioned between and in contact with the first and second semiconductor materials. The memory device can be configured to store energy that can be released by applying a voltage pulse to the memory device.

Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

Abstract: A memory cell is provided with a transistor which includes source and drain electrodes formed in a semiconductor film by respectively N-doped and P-doped areas. The transistor includes first and second devices for generating a potential barrier in the semiconductor film. The two potential barriers are shifted laterally and are opposed to the passage of the charge carriers emitted by the nearest source/drain electrode. One of the devices for generating the potential barrier is electrically connected to the gate. The other of the devices for generating the potential barrier is electrically connected to the counter-electrode. The writing of a high state is carried out by imposing on the P-doped electrode a potential higher than that of the N-doped electrode and charging the capacitor formed between the gate and the semiconductor film. The resetting of the memory cell is obtained by discharging the capacitor.

Abstract: Data is written in the following manner: potentials of first and second control gates of a transistor are set at a potential for making a storage gate of the transistor a conductor, a potential of data to be stored is supplied to the storage gate, and at least one of the potentials of the first and second control gates is set at a potential for making the storage gate an insulator. Data is read in the following manner: the potential of the second control gate is set at a potential for making the storage gate an insulator; a potential is supplied to a wiring connected to one of a source and a drain of the transistor; then, a potential for reading is supplied to the first control gate to detect a change in the potential of a bit line connected to the other of the source and the drain.

Abstract: Power management of an embedded dynamic random access memory (eDRAM) using collected performance counter statistics to generating a set of one or more eDRAM effectiveness predictions. Using a set of one or more eDRAM effectiveness thresholds, each corresponding to one of the set of eDRAM effectiveness predictions, to determine whether at least one eDRAM effectiveness prediction has crossed over threshold. In the case that at least one eDRAM effectiveness prediction has crossed over its threshold, transitioning the eDRAM to a new power state. Power management is achieved by transitioning to a power-off state or self-refresh state and reducing the amount of power consumed by the eDRAM as compared to a power-on state.

Abstract: A DRAM controller component generates a timing signal and transmits, to a DRAM, write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sampled by the DRAM on one or more edges of the timing signal, a clock signal that requires a second time interval to propagate from the DRAM controller component to the DRAM, and a write command, associated with the write data, to be sampled by the DRAM on one or more edges of the clock signal. The DRAM controller component includes series-coupled delay elements to generate respective incrementally delayed signals, and a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval.

Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.

Abstract: A memory cell includes a capacitor, a first transistor, and a second transistor whose off-state current is smaller than that of the first transistor. The first transistor has higher switching speed than the second transistor. The first transistor, the second transistor, and the capacitor are electrically connected in series. Accumulation of charge in the capacitor and release of charge from the capacitor are performed through the first transistor and the second transistor. In this manner, the power consumption of the semiconductor device can be reduced and data can be written and read at higher speed.

Abstract: Provided is a current steering element that can prevent write didturb even when an electrical pulse with different polarities is applied and that can cause a large current to flow through a variable resistance element. The current steering element includes a first electrode (32), a second electrode (31), and a current steering layer (33). The current steering layer (33) comprises SiNx (where 0<x?0.85) added with hydrogen or fluorine. When D (D=D0×1022 atoms/cm3) represents a density of hydrogen or fluorine, d (nm) represents a thickness of the current steering layer (33), and V0 (V) represents a maximum value applicable to between the first electrode (32) and the second electrode (31), D, x, d, and V0 satisfy the following Formulae. (ln(10000(C·exp(?·d)exp(?·x))?1)?)2?V0 (ln(1000(C·exp(?·d)exp(?·x))?1)?)2?(ln(10000(C·exp(?·d)exp(?·x))?1)?)2/2?0 wherein C=k1×D0k2, and ?, ?, ?, k1, and k2 are constants.

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Abstract: A dynamic random-access memory (DRAM) and a method for testing the DRAM are provided. The DRAM includes a memory cell, a bit line associated with the memory cell, a local buffer, and a bit line sense amplifier (BLSA). The local buffer receives a first power voltage as power supply. The local buffer provides a ground voltage to the bit line when a data signal is de-asserted and provides the first power voltage to the bit line when the data signal is asserted. The BLSA receives a second power voltage as power supply. The BLSA provides the second power voltage to the bit line when the data signal and a wafer level burn-in test signal are both asserted. The second power voltage may be higher than the first power voltage. The wafer level burn-in test signal is asserted when the DRAM is in a wafer level burn-in test mode.

Abstract: A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed in a plurality of resistive states according to an electrical signal received. The upper electrode of the capacitive device is coupled to the second electrode of the resistive memory cell. The resistive memory cell is a two-terminal device.

Abstract: Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells.

Abstract: A nonvolatile storage device adapted for use with computers, workstations and other processing apparatuses. The storage device includes a printed circuit board, a nonvolatile memory array comprising at least two sub-arrays that contain nonvolatile solid-state memory devices, and control circuitry for interfacing with the processing apparatus. The control circuitry includes an abstraction layer and at least two memory control units configured to communicate data, address and control signals with the sub-arrays of the memory devices. A bus connects each memory control unit to a corresponding one of the sub-arrays. The control circuitry further includes a crossbar switch that functionally connects each memory control unit to the abstraction layer. The storage device is capable of overcoming limitations of current SSD designs by enabling independent read and write transfers (accesses) to the memory devices of the storage device, including concurrent read and write accesses.

Abstract: An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell.

Abstract: A semiconductor storage device includes a memory cell array in which a memory cell including an MOS capacitor is arranged; a power supply unit that supplies a plate voltage to a plate line that is coupled to a gate electrode of the MOS capacitor; and a switch that couples the plate line to a first power supply line when an access to the memory cell array is caused.

Abstract: Circuits for generating refresh period signals and semiconductor integrated circuits using the same are presented. The refresh period signal generation circuit can include an oscillator, a pulse generation unit, and a signal controller. The oscillator is configured to generate an oscillation signal in response to a refresh duration correction signal. The pulse generation unit is configured to generate a refresh period signal in response to the oscillation signal. The signal controller configured to generate the refresh duration correction signal, which corrects an active time of a refresh duration signal, in response to the oscillation signal.

Abstract: Semiconductor memory devices with a memory cell array including a first word line and a second word line arranged in a first direction, a source line arranged in the first direction between the first word line and the second word line, a bit line pair including a first bit line and a second bit line arranged in a second direction perpendicular to the first direction, a first memory cell including a gate connected to the first word line and first and second regions respectively connected to the second bit line and the source line, and arranged in a third direction between the first direction and the second direction, and a second memory cell including a gate connected to the second word line, a third region and the second region respectively connected to the first bit line and the source line, and arranged in the third direction.

Abstract: A semiconductor memory device is provided between a refresh request circuit and a command decoder, and includes a refresh synchronous circuit for deactivating a refresh request if an external access request is output from the command decoder. The semiconductor memory device further includes a clock phase adjusting unit that generates a delay to a clock, where the delay is same or longer than the time taken from when the external access request is issued until when a critical path is passed, and the delay is also shorter than one cycle. Then a flip-flop retrieves the request from the command decoder at the clock timing from the clock phase adjusting unit to supply it to the memory cell array.

Abstract: A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory circuits. In response to the receipt of a refresh control signal, a first refresh control signal is sent to a first subset of the plurality of other DRAM memory circuits and a second refresh control signal is sent to a second subset of the plurality of other DRAM memory circuits.

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping latter for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory, as non-volatile memory when power to the device is interrupted.

Abstract: Provided herein is an MV DRAM device for storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, where the gate of the transistor is connected to the ground voltage.

Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels Vss and Vdd, and for providing a select signal at levels Vss and Vdd, a high voltage supply source Vpp which is higher in voltage than Vdd, a circuit for translating the select signals at levels Vss and Vdd to levels Vss and Vpp and for applying it directly to the word lines whereby an above Vdd voltage level word line is achieved without the use of double boot-strap circuits.

Abstract: A capacitorless DRAM and methods of manufacturing and operating the same are provided. The capacitorless DRAM includes a source, a drain and a channel layer, formed on a substrate. A charge reserving layer is formed on the channel layer. The capacitorless DRAM includes a gate that contacts the channel layer and the charge reserving layer.

Abstract: An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell.

Abstract: A semiconductor storage device precharging a bit line pair to a ground potential includes a sense amplifier connected between the bit line pair, a storage cell connected to one of the bit line pair and storing data, a first transistor controlling a conduction state between the other of the bit line pair and a reference cell node, a second transistor connected between a reference voltage source generating a reference voltage and the reference cell node, the second transistor exclusively controlled from the first transistor, and a capacitor setting a potential of the reference cell node.

Abstract: An integrated circuit includes a memory cell array including a plurality of memory cells. A first plurality of bit lines is positioned in a first plane. The first plurality of bit lines is electrically coupled to a first set of the memory cells. A second plurality of bit lines is positioned in a second plane that is different than the first plane. The second plurality of bit lines is electrically coupled to a second set of the memory cells.