Capacitors Patents (Class 365/149)
  • Patent number: 10388360
    Abstract: An example apparatus includes a memory device having first sensing circuitry positioned adjacent an edge of an edge array section and selectably coupled to a row memory cells, the first sensing circuitry including a first sense amplifier selectably coupled via a first sense line to a first memory cell in the row and via a second sense line to the first memory cell. The example apparatus includes second sensing circuitry positioned at an opposite edge of the edge array section and selectably coupled to the row via a third sense line, the second sensing circuitry including a second sense amplifier selectably coupled via the third sense line to a second memory cell in the row. The example apparatus further includes a component positioned outside the edge array section and proximate the first sensing circuitry, the component configured to perform an operation based on data sensed by the first sensing circuitry.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 10373682
    Abstract: Apparatuses and techniques are described for programming phase change memory cells while avoiding a clamp condition in transistors which are used for biasing a word line and bit line when the word line and bit line are unselected for a write operation. The transistors may be connected in parallel with the word line and bit line. During a write operation, a current source is connected to a selected word line and a voltage control circuit is connected to the selected bit line. The voltage control circuit can include a capacitor or a voltage driver, for example. The capacitor accumulates charge, or the voltage driver applies an increasing ramp voltage to the bit line, to increase the voltage of the bit line and word line during the write operation and to avoid the clamp condition.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 6, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Ward Parkinson, James O'Toole, Thomas Trent
  • Patent number: 10361204
    Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Slmsek-Ege, Diem Thy N. Tran
  • Patent number: 10354714
    Abstract: Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Donald M. Morgan
  • Patent number: 10346227
    Abstract: Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected number of spare memory cells for replacing the “leaky” memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: July 9, 2019
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 10341571
    Abstract: In various embodiments, an image sensor and related methods of operation of the image sensor are disclosed. In an embodiment, an image sensor includes at least one pixel. The at least one pixel including a transistor to couple an overflow capacitor to a floating diffusion node. Under a low light condition, photocharge is to be collected in a floating diffusion, but substantially not into an overflow node. Under a high light condition, photocharge is to overflow into the overflow node. Other sensors and related operations are disclosed.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: July 2, 2019
    Assignee: INVISAGE TECHNOLOGIES, INC.
    Inventors: Emanuele Mandelli, David Michael Boisvert, Nikolai Bock
  • Patent number: 10332580
    Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 25, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10332581
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: June 25, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Keiji Ikeda, Chika Tanaka, Toshinori Numata, Tsutomu Tezuka
  • Patent number: 10324645
    Abstract: A data storage method for a data storage device is provided. The data storage method includes steps of: determining whether a power drop/loss event occurs; when the power drop/loss event is determined to have occurred, recording a voltage level of a charge storage device, wherein the charge storage device provides power to the data storage device during the power drop/loss event; determining whether the charge storage device is operating normally according to the recorded voltage level of the charge storage device; and when the charge storage device is determined to be not operating normally, configuring the data storage device to enter a safe operation mode. A data storage device is also provided.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 18, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Tsai-Fa Liu, Hung-Lian Lien
  • Patent number: 10319431
    Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
  • Patent number: 10304516
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) and a method of operating the same. The DRAM includes a storage area and a control device. The storage area includes a memory row. The control device is configured to selectively allow the memory row to be eligible for a row-hammer refresh according to temperature of the DRAM.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: May 28, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-jen Chen
  • Patent number: 10305457
    Abstract: A voltage trimming circuit includes a comparator, a code generator, nonvolatile storage device, a switch circuit, and a voltage generator. The comparator compares a reference voltage with a feedback voltage. The code generator generates a plurality of trimming codes for trimming the feedback voltage based on the comparison result of the comparator. If the feedback voltage is less than the reference voltage, the code generator adjusts up codes to increase the feedback voltage, from among the plurality of trimming codes and maintains down codes to decrease the feedback voltage, from among the plurality of trimming codes at an initial value. If the feedback voltage is greater than the reference voltage, the code generator adjusts the down codes and maintains the up codes at an initial value.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye Jung Kwon, Younghun Seo
  • Patent number: 10290747
    Abstract: MIS capacitors are formed using a finned semiconductor structure. A highly doped region including the fins is formed within the structure and forms one plate of a MIS capacitor. A metal layer forms a second capacitor plate that is separated from the first plate by a high-k capacitor dielectric layer formed directly on the highly doped fins. Contacts are electrically connected to the capacitor plates. A highly doped implantation layer having a conductivity type opposite to that of the highly doped region provides electrical isolation within the structure.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10276230
    Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Patent number: 10276792
    Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: April 30, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Ming-Che Wu, Tanmay Kumar
  • Patent number: 10269416
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: April 23, 2019
    Assignee: ARM Limited
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Fakhruddin Ali Bohra
  • Patent number: 10269441
    Abstract: A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one capacitor. The memory array includes at least one programmed memory cell. The programmed memory cell is selectively programmed by applying hot-carrier injection (HCI) to a transistor of the programmed memory cell. The programmed memory cell may provide an indication of pattern data that may be used to facilitate functionality such as data encryption, data decryption, implementation of a particular memory device operation mode, and/or machine-implemented instructions.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, William C. Waldrop
  • Patent number: 10262739
    Abstract: Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: April 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 10255965
    Abstract: A memory circuit capable of being quickly written in data includes a plurality of banks, and each bank of the plurality of banks includes a plurality of segments. Each segment of the plurality of segments includes a plurality of bit line groups, and each bit line group of the plurality of bit line groups corresponds to a pre-charge line. When a predetermined signal is enabled, a potential is written into memory cells of the each segment corresponding to the each bit line group through the pre-charge line and the each bit line group.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 9, 2019
    Assignee: Etron Technology, Inc.
    Inventors: Chun Shiah, Yu-Hui Sung
  • Patent number: 10256241
    Abstract: Apparatus and methods for reducing minority carriers in a memory array are described herein. Minority carriers diffuse between ON cells and OFF cells, causing disturbances during write operation as well as reducing the retention lifetime of the cells. Minority Carrier Lifetime Killer (MCLK) region architectures are described for vertical thyristor memory arrays with insulation trenches. These MCLK regions encourage recombination of minority carriers. In particular, MCLK regions formed by conductors embedded along the cathode line of a thyristor array, as well as dopant MCLK regions are described, as well as methods for manufacturing thyristor memory cells with MCLK regions.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: April 9, 2019
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Valery Axelrad, Charlie Cheng
  • Patent number: 10249347
    Abstract: A normally-off state of an OS transistor is maintained or an on-state current thereof is increased without additionally generating a positive potential or a negative potential. When data is written to a node connecting an OS transistor and a capacitor, a potential supplied to the other side of the capacitor is set to an L level, and when the data is retained, the potential is switched from the L level to an H level. In addition, a power switch for a volatile memory circuit is provided on a low power supply potential side so that the supply of a power supply voltage can be stopped. Accordingly, at the time of data retention, a source and a drain of the OS transistor can be set at a high potential, whereby the normally-off state can be maintained and the on-state current can be increased.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 10249626
    Abstract: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 10236068
    Abstract: The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 19, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu
  • Patent number: 10204674
    Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
  • Patent number: 10199090
    Abstract: Techniques for implementing a storage array write driver with a reduced-power boost circuit. An apparatus may include a bit cell configured to store data, a bit line circuit coupled to convey data to the bit cell, a write driver circuit configured to transmit write data to the bit cell via the bit line circuit, and a boost circuit that is distinct from the write driver circuit. The boost circuit may be selectively coupled to drive the bit line circuit below a ground voltage dependent on activation of a boost signal and the write data being in a logic low state. The boost circuit may also be coupled to the bit line circuit at a location that is closer to the bit cell than to the write driver circuit, and may be sized to discharge the bit line circuit without being sized to discharge internal capacitance of the write driver.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: February 5, 2019
    Assignee: Apple Inc.
    Inventor: Edward M. McCombs
  • Patent number: 10199095
    Abstract: A structure includes a write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line using a strapped bit line on a selected column of the memory cell array.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dhani Reddy Sreenivasula Reddy, Venkatraghavan Bringivijayaraghavan, Vinay Bhat Soori
  • Patent number: 10170178
    Abstract: Techniques for improving the security of nonvolatile memory such as magnetic random access memory (MRAM) are provided. In one aspect, a method of operating a nonvolatile memory chip is provided. The method includes: overwriting data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on. For example, all bits in the nonvolatile memory chip can be written to either i) a predetermined data state (e.g., a logic 1 or a logic 0) or ii) a random data state. A system is also provided that includes: a nonvolatile memory chip; and a writing circuit configured to overwrite data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: John K. DeBrosse, William E. Hall, Hillery C. Hunter, Jeffrey A. Stuecheli, Daniel C. Worledge
  • Patent number: 10170200
    Abstract: According to one embodiment, a memory device is provided including a plurality of data word memories, a test controller configured to, for each data word memory, read a data word stored in the data word memory, check the read data word to detect an error of the memory device, determine a complementary data word of the data word, store the complementary data word in the data word memory, read the complementary data word from the data word memory and check the read complementary data word to detect an error of the memory device.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 1, 2019
    Assignee: Infineon Technologies AG
    Inventor: Martin Huch
  • Patent number: 10170185
    Abstract: Described is an apparatus for a hybrid eDRAM and MRAM memory cell comprising: a capacitor having a first terminal and a second terminal; a first transistor having a gate terminal coupled to a first word line (WL), a source/drain terminal coupled to bit line (BL), and drain/source terminal coupled to the first terminal of the capacitor; a resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor; and a second transistor having a gate terminal coupled to a second WL, a source/drain terminal coupled to source line (SL), and drain/source terminal coupled to the second terminal of the resistive memory element device.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Ian A. Young
  • Patent number: 10164640
    Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Cheng-En Lee, Jui-Che Tsai
  • Patent number: 10157655
    Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: December 18, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yorinobu Fujino, Kosuke Hatsuda, Yoshiaki Osada
  • Patent number: 10157657
    Abstract: A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: December 18, 2018
    Assignee: Rambus Inc.
    Inventors: Hongzhong Zheng, James Tringali, Frederick A. Ware
  • Patent number: 10157685
    Abstract: A memory device may include a plurality of memory cells; one or more backup memory cells; a test circuit suitable for performing a backup operation and a test operation to a test target cell selected among the plurality of memory cells; and a control circuit suitable for accessing the backup memory cells instead of the test target cell during the performance of the test operation after completion of the backup operation for the selected test target cell, wherein, during the backup operation, the test circuit controls the control circuit to copy an original data of the test target cell to a corresponding backup memory cell selected among the backup memory cells, and wherein, during the test operation, the test circuit determines whether the test target cell is a pass or a fail.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 18, 2018
    Assignee: SK Hynix Inc.
    Inventors: Tae-Kyun Kim, Jin-Hee Cho, Jun-Gi Choi
  • Patent number: 10153301
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: December 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
  • Patent number: 10153019
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of the memory cell may be initialized to a value associated with the threshold voltage of a switching component in electronic communication with the memory cell. The voltage may be initialized by reducing the existing voltage on the access line to the value. The switching component or an additional pull down device, or both, may be used to reduce the voltage of the access line. After the access line has been initialized to the value, the read operation may be triggered.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 11, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Aswin Thiruvengadam, Hernan A. Castro
  • Patent number: 10147496
    Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: December 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Akhilesh Gautam, Suresh Uppal, Min-hwa Chi
  • Patent number: 10147465
    Abstract: Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an external power supply and to provide an internal power supply to the memory device upon receipt of a command. The power up circuitry may be configured to provide the internal power supply limited to a peak current, or may be configured to provide the internal power supply not limited to a peak current. The memory device may be, for example, a synchronous dynamic random access memory (SDRAM) device or Flash memory.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Ted Pekny, Jeff Yu
  • Patent number: 10147470
    Abstract: A semiconductor memory device includes a charge storage element, a read transistor, and a write transistor. The charge storage element is for preserving a first data voltage. The read transistor has a first terminal coupled to the charge storage element, a second terminal coupled to a read bit line, and a control terminal coupled to a read word line. The write transistor has a first terminal coupled to the first terminal of the read transistor, a second terminal coupled to a write bit line, and a control terminal coupled to a write word line. The semiconductor memory device is able to perform a read operation and a write operation to the charge storage element simultaneously through the read transistor and the write transistor.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: December 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chung-Hao Cheng
  • Patent number: 10141044
    Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: November 27, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shang-Pin Chen, Chia-Yu Chan, Bo-Wei Hsieh
  • Patent number: 10141035
    Abstract: The memory cell includes a read selection transistor, a program selection transistor, and an anti-fuse capacitor. The read selection transistor has a first terminal coupled to a bit line, a second terminal, and a control terminal coupled to a read word line. The program selection transistor has a first terminal coupled to the second terminal of the read selection transistor, a second terminal coupled to a high voltage control line, and a control terminal coupled to a program word line. The anti-fuse capacitor has a first terminal coupled to the second terminal of the read selection transistor, and a second terminal coupled to a low voltage control line.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: November 27, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tsai-Yu Huang, Pin-Yao Wang
  • Patent number: 10134737
    Abstract: An interconnect structure includes a lower interconnect layer, an intermediate interconnect layer, and an upper interconnect layer. First and second conductive lines in the lower interconnect layer extend generally in a first direction over a memory array region, and additional lower conductive lines in the lower interconnect layer extend generally in the first direction over a peripheral region. A first plurality of conductive line segments in the intermediate interconnect layer extend generally in the first direction over the memory array region, and additional intermediate conductive line segments in the intermediate interconnect layer extend generally in a second, perpendicular direction over the peripheral region. A second plurality of conductive line segments in the upper interconnect layer extend generally in the first direction over the memory array region, and additional upper conductive line segments in the upper interconnect layer extend generally in the first direction over the peripheral region.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sahil Preet Singh, Yen-Huei Chen
  • Patent number: 10127994
    Abstract: A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one capacitor. The memory array includes at least one programmed memory cell. The programmed memory cell is selectively programmed by applying hot-carrier injection (HCI) to a transistor of the programmed memory cell. The programmed memory cell may provide an indication of pattern data that may be used to facilitate functionality such as data encryption, data decryption, implementation of a particular memory device operation mode, and/or machine-implemented instructions.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: November 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, William C. Waldrop
  • Patent number: 10115474
    Abstract: A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information; connecting the fuse cell to the fuse read node for reading the information; and determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: October 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Raghukiran Sreeramaneni, William J. Wilcox, Girish N. Cherussery
  • Patent number: 10115465
    Abstract: Methods of operating a memory include receiving a plurality of digits of data, determining a value of the plurality of digits of data, and selecting a function to represent the value of the plurality of digits of data. The selected function is a function of a cell number of each memory cell within a grouping of memory cells. The methods further include determining a desired threshold voltage of a particular memory cell of the grouping of memory cells corresponding to the value of the selected function for the cell number of the particular memory cell, and programming the particular memory cell to its desired threshold voltage.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: October 30, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Ramin Ghodsi
  • Patent number: 10108357
    Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: October 23, 2018
    Assignee: Oracle International Corporation
    Inventors: David Jeffrey, Clement Fang, Neil Duncan, Heechoul Park, Lik Cheng, Gregory F. Grohoski
  • Patent number: 10108245
    Abstract: Interaction based charging control is described. In an embodiment, a device is described, comprising: an interface configured to receive a charging power from another device; a sensor configured to detect interaction of the device; a charging controller configured to reduce the charging power in response to the detected interaction; in response to the reduced charging power, a processor configured to allow more processing power for the device. In other embodiments, a device comprising a sensor configured to detect a temperature of the device, and a method are discussed.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: October 23, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mikael Troberg, Jani Mäki
  • Patent number: 10101763
    Abstract: A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: October 16, 2018
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventor: Yonatan Tzafrir
  • Patent number: 10090025
    Abstract: In one embodiment, an integrated circuit comprises a volatile memory including a plurality of memory cells, a detector to detect one or more in-specification conditions, and a discharger, external to the volatile memory, to discharge electric charge stored in the integrated circuit, including electric charge stored in the volatile memory, unless the detector detects the one or more conditions.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: October 2, 2018
    Assignee: Cisco Technology, Inc.
    Inventor: Reuven Elbaum
  • Patent number: 10074414
    Abstract: Apparatuses and methods are disclosed that in ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Patent number: 10062435
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: August 28, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Piyush Agarwal, Akshay Kumar