Capacitors Patents (Class 365/149)
  • Patent number: 11152056
    Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. A true digit-line has a short first region along the first deck and a long second region along the second deck. A complementary digit-line has a long first region along the first deck and a short second region along the second deck. A first set of first memory cells is associated with the true digit-line. The first set includes a first subset along the short first region, a second subset along a portion of the long second region, and a third subset along another portion of the long second region. A routing region of the true digit-line extends between the second and third subsets of the first memory cells. A connection extends from the short first region to the routing region of the true digit-line.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Seung Yeong Seo, Myung Ho Bae
  • Patent number: 11126548
    Abstract: An apparatus having a memory array. The memory array having a first section and a second section. The first section of the memory array including a first sub-array of memory cells made up of a first type of memory. The second section of the memory array including a second sub-array of memory cells made up of the first type of memory with a configuration to each memory cell of the second sub-array that is different from the configuration to each cell of the first sub-array. Alternatively, the section can include memory cells made up of a second type of memory that is different from the first type of memory. Either way, the second type of memory or the differently configured first type of memory has memory cells in the second sub-array having less memory latency than each memory cell of the first type of memory in the first sub-array.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Dmitri Yudanov
  • Patent number: 11100978
    Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 24, 2021
    Assignee: Surecore Limited
    Inventors: Stefan Cosemans, Bram Rooseleer
  • Patent number: 11099922
    Abstract: An information handling system includes a device and a baseboard management controller. The device is configured to communicate with a processor of the information handling system. The baseboard management controller is configured to communicate with the device via an in-band communication channel. The baseboard management controller determines whether data is received from the device via an in-band communication channel, and determines whether the baseboard management controller may communicate with the device via an out-of-band communication channel. In response to the data not being received and the baseboard management controller not able to communicate with the device, the baseboard management controller detects a failure of the device. In response to the detection of the failure of the device, the baseboard management controller isolates the device.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: August 24, 2021
    Assignee: Dell Products L.P.
    Inventors: Rama Rao Bisa, Johan Rahardjo, Pavan Kumar Gavvala, Elie Antoun Jreij, Akkiah Choudary Maddukuri, Isaac Qin Wang
  • Patent number: 11094698
    Abstract: A semiconductor storage device according to the present embodiment includes a plurality of first wires provided above a surface of a semiconductor substrate to extend in a first direction, and a plurality of second wires provided above the first wires to extend in a second direction crossing the first direction. A plurality of capacitor elements are arranged every other intersection region among intersection regions between the first wires and the second wires as viewed from above the surface of the semiconductor substrate. A plurality of transistors are provided above the capacitor elements to correspond thereto, respectively. A first distance between two of the capacitor elements, which are adjacent to each other in the first direction, is narrower than a second distance between two of the capacitor elements, which are adjacent to each other in the second direction.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: August 17, 2021
    Assignee: Kioxia Corporation
    Inventor: Tsuneo Inaba
  • Patent number: 11087839
    Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 10, 2021
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Jungho Yoon, Cheol Seong Hwang, Soichiro Mizusaki, Youngjin Cho
  • Patent number: 11087791
    Abstract: A data storage drive includes a magnetic recording media comprising a ferroelectric layer between a bottom electrode layer and a top electrode layer. An applied voltage to the ferroelectric layer generates a strain that is transferred to a ferromagnetic recording layer formed proximate to the ferroelectric layer. The change in strain transferred to the recording layer changes the magnetic properties of the recording layer. A voltage can be selectively applied to all or part of the ferroelectric layer to place the ferromagnetic recording layer in a low coercivity state to assist in writing data. Voltage-assisted magnetic recording (VAMR) is provided based upon control of a magnetic recording media comprising a ferroelectric layer between a bottom electrode layer and a top electrode layer.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: August 10, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Alan Kalitsov, Kumar Srinivasan, Bhagwati Prasad
  • Patent number: 11088289
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: August 10, 2021
    Assignee: Mosaid Technologies Incorporated
    Inventor: Hyoung Seub Rhie
  • Patent number: 11081594
    Abstract: In a display panel according to the disclosure, the display panel includes a substrate, an active layer having a source region, a drain region and a channel region on the substrate, a source electrode contacted with the source region, a drain electrode contacted with the drain region, an upper gate electrode above the active layer, and a lower gate electrode below the active layer. An edge of the lower gate electrode closest to the drain region overlaps with the channel region, and the source region and the drain region do not overlap with the upper gate electrode. The driving element constituting the display panel can generate a high driving current without deteriorating the characteristics thereof, thereby stably maintaining the luminance of the display panel.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 3, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sunyoung Choi, Kummi Oh
  • Patent number: 11074953
    Abstract: The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Shunpei Yamazaki
  • Patent number: 11062753
    Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Charles L. Ingalls, Scott J. Derner
  • Patent number: 11048476
    Abstract: Provided are a method and system for using a non-linear feedback shift register (NLFSR) for generating a pseudo-random sequence with at least near-maximal length for n number of stages, where a maximal length is 2n?1. The method may include selecting n, where n requires more than two taps in maximal length linear feedback shift registers; and generating, for the selected n-stage register, a pseudo-random sequence using a feedback logical operation of only a first logic gate and a second logic gate. Two suitable non-end taps are inputs for the first logic gate, an output of the first logic gate and an end tap are inputs for the second logic gate, and an output of the second logic gate is used as feedback to a first stage of the n-stage register.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventor: Andrew Johnson
  • Patent number: 11037622
    Abstract: A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: June 15, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Kiyoshi Kato, Shuhei Maeda
  • Patent number: 11024358
    Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a positive capacitor. A first plate of the positive capacitor connects to a positive read bit line. An inverter inverts a voltage of the second plate of the positive capacitor to drive a first plate of a negative capacitor having a second plate connected to a negative read bit line.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 1, 2021
    Assignee: Qualcomm Incorporated
    Inventor: Ankit Srivastava
  • Patent number: 11017834
    Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Nathaniel J. Meier, James S. Rehmeyer, Sang-Kyun Park, Makoto Kitayama
  • Patent number: 11011216
    Abstract: A compute-in-memory dynamic random access memory bitcell is provided that includes a first transistor having an on/off state controlled by a weight bit stored across a capacitor. The first transistor is in series with a current-source transistor connected between the first transistor and a read bit line. An activation voltage controls whether the current-source transistor conducts a current when the first transistor is in the on state.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: May 18, 2021
    Assignee: Qualcomm Incorporated
    Inventor: Ankit Srivastava
  • Patent number: 11005038
    Abstract: A semiconductor structure includes stack structures. Each of the stack structures comprises a first conductive material, a chalcogenide material over the first conductive material, a second conductive material over the chalcogenide material, and a first dielectric material between the chalcogenide material and the first conductive material and between the chalcogenide material and the second conductive material. The semiconductor structure further comprises a second dielectric material on at least sidewalls of the chalcogenide material. The chalcogenide material may be substantially encapsulated by one or more dielectric materials. Related semiconductor structures and related methods are disclosed.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Agostino Pirovano
  • Patent number: 11004983
    Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: May 11, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kosei Noda, Kouhei Toyotaka, Kazunori Watanabe, Hikaru Harada
  • Patent number: 10998043
    Abstract: A nonvolatile memory apparatus includes a plurality of cell arrays, each including a near area and a far area. A plurality of memory cells are included in the near area, and a plurality of memory cells are included in the far area. When a memory cell of the plurality of memory cells, included in a near area of at least one cell array, among the plurality of cell arrays, is selected, based on an address signal, the nonvolatile memory apparatus selects memory cells included in far areas of the remaining cell arrays based on the address signal. The nonvolatile memory apparatus performs a first read operation on the selected memory cell of the at least one cell array, and performs a second read operation on the selected memory cells of the remaining cell arrays.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Jung Hyuk Yoon, In Soo Lee
  • Patent number: 10991400
    Abstract: An integrated circuit includes: one or more first sections in which first to Nth data (where N is an integer equal to or greater than 2) corresponding to one command are transferred through one line; and two or more second sections in which the first to Nth data are serial-to-parallel converted in 1:N and transferred through N lines, wherein whenever the command is applied, the first to Nth data are transferred without being inverted or transferred after being inverted repeatedly in at least one second section among the two or more second sections.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventors: Heat-Bit Park, Ji-Hwan Kim, Dong-Uk Lee
  • Patent number: 10984840
    Abstract: To provide a novel semiconductor device.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: April 20, 2021
    Inventors: Tatsuya Onuki, Takanori Matsuzaki, Kiyoshi Kato, Shunpei Yamazaki
  • Patent number: 10984958
    Abstract: Capacitive energy storage devices (CESDs) are disclosed, along with methods of making and using the CESDs. A CESD includes an array of electrodes with spaces between the electrodes. A dielectric material occupies spaces between the electrodes; regions of the dielectric material located between adjacent electrodes define capacitive elements. The disclosed CESDs are useful as energy storage devices and/or memory storage devices.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: April 20, 2021
    Assignee: Carver Scientific, Inc.
    Inventors: David Reginald Carver, Bradford Wesley Fulfer, Chase Andrepont, Sean Claudius Hall, Sean William Reynolds
  • Patent number: 10978297
    Abstract: A method of making stacked lateral semiconductor devices is disclosed. The method includes depositing a stack of alternating layers of different materials. Slots or holes are cut through the layers for subsequent formation of single crystal semiconductor fences or pillars. When each of the alternating layers of one material are removed space is provided for formation of single crystal semiconductor devices between the remaining layers. The devices are doped as the single crystal silicon is formed.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: April 13, 2021
    Assignee: TC Lab, Inc.
    Inventor: Harry Luan
  • Patent number: 10977003
    Abstract: A method and system for using a linear feedback shift register (LFSR) with near-maximal length sequences for generating a pseudo-random sequence for n number of stages, where a maximal length is 2n-1. The method includes selecting n, where n requires more than two taps in maximal length linear feedback shift registers; and for the selected n-stage register, using a feedback logical operation of only two XOR gates. The logical operation includes a first logical XOR performed on outputs of two taps, a second logical XOR performed on the output of the first logical XOR and an output of a third tap. The output of the second logical XOR is used as feedback to a first stage of the n-stage register, where one of the taps is an end tap, the other two taps are suitable non-end taps, and the feedback logical operation includes an odd number of gate inversions.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventor: Andrew Johnson
  • Patent number: 10978136
    Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: April 13, 2021
    Assignee: Apple Inc.
    Inventors: Liang Deng, Norman J. Rohrer, Yizhang Yang, Arpit Mittal
  • Patent number: 10964374
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Matthew D. Jenkinson, Nathaniel J. Meier, Dennis G. Montierth
  • Patent number: 10950279
    Abstract: A BLSA circuit includes a first inverter disposed between a first sensing node and a second inner bit line, a second inverter disposed between a second sensing node and a first inner bit line, a first capacitor disposed between a first bit line and the first sensing node, a second capacitor disposed between a second bit line and the second sensing node, a first offset canceling switch for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation, a second offset canceling switch for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation, a first isolation switch for electrically coupling the first bit line with the first inner bit line, and a second isolation switch for electrically coupling the second bit line with the second inner bit line.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 16, 2021
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Deog-Kyoon Jeong, Jung Min Yoon, Hyungrok Do, Dae-Hyun Koh
  • Patent number: 10950284
    Abstract: Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may be configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder may include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells. In some cases, the decoder may include a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Fabio Pellizzer
  • Patent number: 10943670
    Abstract: Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 9, 2021
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Gaurav Rattan Singla
  • Patent number: 10943170
    Abstract: A neural network circuit includes: a storage part that includes memristors in a lattice shape; a voltage application circuit that applies a bias voltage to the storage part; a controller that controls the voltage application circuit to perform to a selection element, writing, erasing, or reading; and multiple conversion amplification circuits that convert a current flowing into a voltage, and output the voltage.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: March 9, 2021
    Assignee: DENSO CORPORATION
    Inventors: Shigeki Otsuka, Hironobu Akita, Irina Kataeva
  • Patent number: 10932582
    Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Huy T. Vo, Adam S. El-Mansouri
  • Patent number: 10937487
    Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Vimercati, Stefan Frederik Schippers, Xinwei Guo
  • Patent number: 10930359
    Abstract: A programmable memory device. The device comprises at least four memory cells, each cell comprising a data storage element connected to a switching element. The device is arranged such that each switching element is connected to at least two selection lines for selecting of at least one of the at least four memory cells. At least one of the four memory cells is selectable by applying a voltage to at least one of the at least two selection lines, such that at least two switching elements share one of the at least two selection lines and one of the at least two switching elements shares another one of the at least two selection lines with another switching element and such that each data storage element is connected to a shared data line for applying a programming or reading voltage to each storage element of the at least four memory cells to allow for programming or reading of the selected memory cell.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: February 23, 2021
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
    Inventors: Rumen Rachinsky, Aleksandar Radev, Valeri Ivanov
  • Patent number: 10930337
    Abstract: Techniques are provided for writing a high-level state to a memory cell capable of storing three or more logic states. After a sense operation performed by a first sense component and a second sense component, a digit line may be isolated from the first sense component and the second sense component. The high-level state may be stored in the memory cell, then a second state may be stored in the memory cell, in which the second state may be a mid-level state or a low-level state. The second state may be stored based on a write-back component identifying that the second state was stored in the memory cell before the write back procedure.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John F. Schreck, George B. Raad
  • Patent number: 10923173
    Abstract: A voltage generating circuit, a semiconductor memory device, and a voltage generating method are provided. The voltage generating circuit includes: an oscillation signal generating part generating an oscillation signal that alternately repeats a state of a first voltage and a state of a second voltage; a capacitor having one end receiving the oscillation signal and an other end connected to an output node; a switch element receiving a control voltage and set to an on state or an off state according to the control voltage, and applying the first voltage to the output node when set to the on state; and a switch control part supplying, as the control voltage to the switch element, the second voltage when the oscillation signal is in the state of the first voltage, and a voltage of the output node when the oscillation signal is in the state of the second voltage.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: February 16, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Akira Akahori
  • Patent number: 10901622
    Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Cariello, Mauro Luigi Sali, Stefano Falduti, Ugo Russo
  • Patent number: 10902893
    Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Pramod Kolar, John Riley, Gunjan Pandya
  • Patent number: 10902235
    Abstract: According to a first aspect of the present disclosure, a fingerprint sensor module is provided, comprising: an assembly comprising a substrate and a fingerprint sensor mounted on one side of the substrate; wherein the fingerprint sensor comprises a set of sensor elements and a measurement unit; and wherein the measurement unit is configured to concurrently measure capacitances on subsets of the set of sensor elements. According to a second aspect of the present disclosure, a corresponding method of producing a fingerprint sensor module is conceived.
    Type: Grant
    Filed: May 12, 2018
    Date of Patent: January 26, 2021
    Assignee: NXP B.V.
    Inventor: Thomas Suwald
  • Patent number: 10896730
    Abstract: In a particular implementation, a method of storing dynamic random-access memory (DRAM) data in respective magneto-electric magnetic tunnel junctions (ME-MTJ) of D-MRAM bit-cells of a D-MRAM bit-cell memory array, the method comprising: for each of the D-MRAM bit-cells: writing a first data value in a storage capacitor; and in a first cycle, providing a first voltage to a source line coupled to an ME-MTJ, wherein in response to the storage capacitor storing the first data value, the ME-MTJ is configured to store the first data value if the first voltage generates a voltage difference between first and second terminals of the ME-MTJ.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 19, 2021
    Assignee: Arm Limited
    Inventors: Akhilesh Ramlaut Jaiswal, Mudit Bhargava
  • Patent number: 10896715
    Abstract: A dynamic memory system having multiple memory regions respectively storing multiple types of data. A controller coupled to the dynamic memory system via a communication channel and operatively to: monitor usage of a communication bandwidth of the communication channel; determine to reduce memory bandwidth penalty caused by refreshing the dynamic memory system; and in response, reduce a refresh rate of at least one of the memory regions based on a type of data stored in the respective memory region.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Gil Golov
  • Patent number: 10896717
    Abstract: An example apparatus includes an array of memory cells coupled to an array power supply and a controller. The controller may be configured to cause a data value to be stored in at least one memory cell of the array of memory cells while the array of memory cells is operating in a first power state and a determination to be made that a change in a power status to a computing system coupled to the array of memory cells has occurred, wherein the change in the power status of the computing system is characterized by the computing device operating in a reduced power state. Responsive to the determination, the controller may be configured to cause the array power supply to be disabled to operate the array of memory cells in a second power state.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Patent number: 10891239
    Abstract: One embodiment facilitates operation of non-volatile memory. During operation, the system determines, by a flash translation layer module, a physical block address associated with a first request which indicates data to be read, wherein the non-volatile memory is divided into separate physical zones, wherein the physical block address is associated with a first physical zone, and each separate physical zone has a dedicated application to read or write data thereto. The system obtains a free page frame in a volatile memory by writing data from a cold page in the volatile memory to a second physical zone, wherein a cold page is a page with a history of access which is less than a predetermined threshold. The system loads, based on the physical block address, data from the non-volatile memory to the free page frame. The system executes the request based on the data loaded into the free page frame.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: January 12, 2021
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 10878889
    Abstract: A high retention time memory element is described that has dual gate devices. A memory element has a write transistor with a gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Rafael Rios, Gilbert Dewey, Van H. Le, Jack Kavalieros, Mesut Meterelliyoz
  • Patent number: 10879381
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: December 29, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoru Okamoto, Shinya Sasagawa
  • Patent number: 10878132
    Abstract: A device can be used for detecting faults. A shift register is suitable for shifting, in tempo with a clock, a binary signal alternating between two logic levels, in successive cells of the shift register. A first logic circuit is suitable for comparing values contained in at least one pair of cells of the register.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 29, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas
  • Patent number: 10867640
    Abstract: There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Jin Ha Hwang
  • Patent number: 10860913
    Abstract: An RFID tag manufacturing apparatus that includes an antenna base material conveying part that conveys an antenna base material with antenna patterns in a first direction. Moreover, the apparatus includes a conveying part for an RFIC element that supplies an RFIC element having terminal electrodes for connection with the antenna patterns on one principal surface. A plotter is further provided that conveys the supplied RFIC element to a predetermined position of the antenna patterns and temporarily bonds the RFIC element to the antenna patterns. Finally, the apparatus includes a pressurizing part that applies a pressure to the temporarily bonded RFIC element to permanently bond the RFIC element to the antenna patterns. In an aspect, the plotter includes a fixed arm portion and a movable suction head.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 8, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Noboru Kato
  • Patent number: 10861579
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Patent number: 10854276
    Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Patent number: 10854270
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Smith, Michael A. Shore