Capacitors Patents (Class 365/149)
  • Patent number: 11510002
    Abstract: A semiconductor device with a novel structure which can identify the sound source is provided. The semiconductor device includes a microphone array, delay circuits, and a signal processing circuit. The delay circuit includes a first selection circuit, which selects a microphone, signal retention circuits, which retain voltages depending on the sound signal, and a second selection circuit, which selects a signal retention circuit. Each signal retention circuit includes a transistor which includes a semiconductor layer including an oxide semiconductor in its channel formation region. The first selection circuit writes the voltage of discreet sound signals to the signal retention circuit. The second selection circuit selects at different timings the voltages which are retained in the signal retention circuit and generates the output signal corresponding to the delayed sound signal.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 22, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Kiyotaka Kimura, Takeya Hirose
  • Patent number: 11495284
    Abstract: Disclosed are a memory device and an operating method thereof. The memory device includes a bitline sense amplifier connected to a bitline and a complementary bitline connected to a memory cell, and a sense amplifier driver circuit. The bitline sense amplifier senses and amplifies a voltage difference by developing a voltage of the bitline and a voltage of the complementary bitline. The sense amplifier driver circuit includes a pull-up circuit adjusting a level of a bitline low-level voltage developed by the bitline sense amplifier to be higher than a ground voltage in response to a first pull-up pulse, and a pull-down circuit adjusting the level of the bitline low level adjusted by the pull-up circuit to be equal to the ground voltage in response to a pull-down pulse. A pulse generator generates the first pull-up pulse and the pull-down pulse based on a command received from a host.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Ho Moon, Sung-Hwan Jang
  • Patent number: 11495280
    Abstract: A semiconductor memory device includes an external resistor provided on a board and a plurality of memory dies mounted on the board, designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation during an initialization sequence of the semiconductor memory device and stores, in a first register set therein, first calibration data, a first voltage and a first temperature. Each of the slave dies, after the first impedance calibration operation is completed, performs a second impedance calibration operation during the initialization sequence and stores, in a second register set therein, second calibration data associated with the second impedance calibration operation and offset data corresponding to a difference between the first calibration data and the second calibration data.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: November 8, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeongseok Seo, Kwanghyun Kim, Chikook Kim, Seungwoo Ryu, Doohee Hwang
  • Patent number: 11475939
    Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Akira Yamashita, Kenji Asaki
  • Patent number: 11476258
    Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a gate electrode formed on the main surface of the semiconductor substrate, a side-wall oxide film formed on a side wall of the gate electrode, a first insulating layer formed on the gate electrode and containing silicon nitride, and a second insulating layer formed between the gate electrode and the first insulating layer and containing silicon oxide.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 18, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yukio Maki
  • Patent number: 11462258
    Abstract: A memory device and an operating method thereof are provided. The memory device includes a latch configured to sense a voltage or a current of a bit line coupled to a memory cell and store read data, a transmission circuit configured to output the read data stored in the latch through a page bus line in response to a transmission signal, a cache latch configured to receive the read data through the page bus line and temporarily store the read data, and a pump voltage output circuit coupled to the transmission circuit through a transmission line and configured to apply a second voltage greater than a first voltage after applying the first voltage to the transmission line for a set time.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11417385
    Abstract: A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes a temperature sensor, a plurality of memory blocks and a refresh controller. The temperature sensor detects a device temperature inside the semiconductor memory apparatus to generate a corresponding temperature signal. Each of the memory blocks includes a memory cell array having a plurality of volatile memory cells, and a plurality of word lines. The refresh controller monitors accesses to the word lines, detects accesses that occur a predetermined number of times within a predetermined period, and assigns a refresh operation corresponding to the refresh operation command to a first refresh operation or a second refresh operation.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: August 16, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Yutaka Ito
  • Patent number: 11386945
    Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: July 12, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Ward Parkinson, James O'Toole, Nathan Franklin, Thomas Trent
  • Patent number: 11380396
    Abstract: The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 5, 2022
    Assignee: Hefei Reliance Memory Limited
    Inventor: Brent Steven Haukness
  • Patent number: 11381231
    Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwan Yeob Chae, Jong-Ryun Choi
  • Patent number: 11356625
    Abstract: An image sensor semiconductor device includes a first photodiode disposed in a semiconductor substrate and configured to generate charges in response to radiation, a first transistor disposed adjacent to the first photodiode, a floating diffusion region configured to store the generated charges, a reset transistor configured to reset the floating diffusion region, and a second transistor disposed over the substrate between the first photodiode and the reset transistor. The first transistor and the second transistor are configured to generate a first electric field and a second electric field, respectively, to move the charges generated by the first photodiode to the floating diffusion region.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Seiji Takahashi, Jhy-Jyi Sze
  • Patent number: 11355504
    Abstract: Described herein are anti-ferroelectric (AFE) memory cells and corresponding methods and devices. For example, in some embodiments, an AFE memory cell disclosed herein includes a capacitor employing an AFE material between two capacitor electrodes. Applying a voltage to one electrode of such capacitor allows boosting the charge at the other electrode, where nonlinear behavior of the AFE material between the two electrodes may advantageously manifest itself in that, for a given voltage applied to the first electrode, a factor by which the charge is boosted at the second electrode of the capacitor may be substantially different for different values of charge at that electrode before the boost. Connecting the second capacitor electrode to a storage node of the memory cell may then allow boosting the charge on the storage node so that different logic states of the memory cell become more clearly resolvable, enabling increased retention times.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
  • Patent number: 11335396
    Abstract: Methods, systems, and devices for timing signal delay for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. A memory device may include delay components having a configurable impedance based at least in part on one or more fabrication characteristics of the memory device, one or more operating conditions of the memory device, one or more bias voltages, or a combination thereof.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Zhi Qi Huang, Wei Lu Chu, Dong Pan
  • Patent number: 11329640
    Abstract: An analog delay line includes a clock generator, an analog sampling circuit, a bank of analog memory cells, a memory controller, an analog readout circuit, and an analog multiplexer. The clock generator is configured to output plural reception clock signals of different frequencies and plural transmission clock signals of different frequencies, the transmission clock signals offset in accumulated phase relative to the reception clock signals. The analog sampling circuit is controlled by at least one of the reception clock signals, and is configured to output a sequence of sampled voltages of an analog input signal. The memory controller is configured to control a write operation at a write frequency of at least one of the reception clock signals and a read operation at a read frequency of at least one of the transmission clock signals.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: May 10, 2022
    Assignee: Keysight Technologies, Inc.
    Inventors: Charles Wu, Ken A. Nishimura, Kenneth D. Poulton
  • Patent number: 11309320
    Abstract: A nonvolatile memory cell using vertical nanowire (VNW) FETs includes a program element of which a gate is connected to a word line, and a switch element that is provided between the program element and a bit line and of which a gate is connected to the word line. The program element and the switch element are each constituted by one or a plurality of VNW FETs, and these VNW FETs are arranged in a line in a first direction.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 19, 2022
    Assignee: SOCIONEXT INC.
    Inventor: Tomoyuki Yamada
  • Patent number: 11309306
    Abstract: An integrated circuit includes an active zone having a center portion adjoining a first side portion and a second side portion. A first transistor having a gate formed over one of the first channel regions in the center portion has a first threshold-voltage. A second transistor having a gate formed over one of the second channel regions in the center portion has a second threshold-voltage. A third transistor having a gate formed over one of the third channel regions in the first side portion has a third threshold-voltage. A fourth transistor having a gate formed over one of the fourth channel regions in the second side portion has a fourth threshold-voltage. A first average of the first threshold-voltage and the second threshold-voltage is larger than a second average of the third threshold-voltage and the fourth threshold-voltage by a predetermined threshold-voltage offset.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Tao Yang, Wen-Shen Chou, Yung-Chow Peng
  • Patent number: 11309011
    Abstract: A memory system is disclosed. The memory system includes a memory array and a controller. The controller is configured to perform a refresh operation to the memory array with a first refresh cycle rate. The first refresh cycle rate is derived from a first refresh time in a lookup table. The lookup table is configured to store refresh times and refresh temperatures corresponding to the refresh times separately.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hiroki Noguchi, Yih Wang
  • Patent number: 11302374
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Matthew D. Jenkinson, Nathaniel J. Meier, Dennis G. Montierth
  • Patent number: 11282561
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Bill Nale, Christopher E. Cox
  • Patent number: 11270997
    Abstract: A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are stacked. One of two bit lines of a first bit line pair is electrically connected to A memory cells of the first cell array, and the other of the two bit lines of the first bit line pair is electrically connected to D memory cells of the second cell array. One of two bit lines of a second bit line pair is electrically connected to B memory cells of the first cell array and F memory cells of the second cell array, and the other of the two bit lines of the second bit line pair is electrically connected to C memory cells of the first cell array and E memory cells of the second cell array. The first bit line pairs and the second bit line pairs are alternately provided.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: March 8, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Yuki Okamoto, Hisao Ikeda, Shuhei Nagatsuka
  • Patent number: 11264079
    Abstract: Apparatuses, systems, and methods for row hammer based cache lockdown. A controller of a memory may include an aggressor detector circuit which determines if addresses are aggressor addresses or not. The controller may include a tracker circuit which may count a number of times an address is identified as an aggressor, and may determine if the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, a cache entry associated with the frequent aggressor address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker which may determine if the frequent aggressor address is a highly attacked address. An address mapping associated with the highly attacked address may be changed.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: David A. Roberts
  • Patent number: 11264115
    Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 1, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Russell Schreiber, Keith A. Kasprak, Vance Threatt, James A. Wingfield, William A. Halliday, Srinivas R. Sathu, Arijit Banerjee
  • Patent number: 11237828
    Abstract: This application discloses a mechanism to securely store and compute with a matrix of numbers or any two-dimensional array of binary values in a storage entity called a matrix space. A matrix space is designed to store matrices or arrays of values into arrays of volatile or non-volatile memory cells with accessibility in two or three dimensions. Any row or column or line of storage elements in the storage entity is directly accessible for writing, reading, or clearing via row bit lines and column bit lines, respectively. The elements in rows of the arrays are selected or controlled for access using row address lines and the elements in columns of the arrays are selected or controlled for access using column address lines. Access control methods and mechanisms with keys to secure, share, lock, and unlock regions in the matrix space for matrices and arrays under the control of an operating system or a virtual-machine hypervisor by permitted threads and processes are also disclosed.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: February 1, 2022
    Inventor: Sitaram Yadavalli
  • Patent number: 11238928
    Abstract: A read-write circuit mainly includes a read circuit and a write circuit. The write circuit comprises: a first voltage selector and a first voltage follower circuit that is electrically connected to the memristor storage array. The read-write circuit further includes a second voltage selector and a second voltage follower circuit that is electrically connected to the memristor storage array. Voltage stable following during bipolar writing is selected through the foregoing selector. Meanwhile, the reading circuit is provided with a variable resistor to select an access mode. The actual read-out voltage and the output voltage passing through the reference resistor under the same read voltage are input into a differential amplifier to obtain read-out data.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: February 1, 2022
    Assignee: Huazhong University of Science and Technology
    Inventors: Xingsheng Wang, Enming Huang, Xiangshui Miao
  • Patent number: 11222682
    Abstract: Apparatuses and methods for generating refresh addresses for row hammer refresh operations are disclosed. In some examples, determination of a row address associated with a highest count value may be initiated at a precharge command preceding a row hammer refresh operation. The row address determined to be associated with the highest count value may be provided for generating the refresh addresses.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Honoka Enomoto, Masaru Morohashi
  • Patent number: 11217292
    Abstract: Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Umberto Di Vincenzo
  • Patent number: 11218019
    Abstract: Various embodiments described herein use a set of capacitor sets (e.g., capacitor banks) in a power backup architecture for a memory sub-system, where each capacitor set can be individually checked for a health condition (e.g., in parallel) to determine their respective health after the memory sub-system has completed a boot process. In response to determining that at least one capacitor set has failed the health condition (or a certain number of capacitor sets have failed the health condition), the memory sub-system can perform certain operations prior to primary power loss to the memory sub-system (e.g., preemptively performs a data backup process to ensure data integrity) and can adjust the operational mode of the memory sub-system (e.g., switch it from read-write mode to read-only mode).
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vehid Suljic, Matthew D. Rowley
  • Patent number: 11217668
    Abstract: A miniaturized transistor with reduced parasitic capacitance and highly stable electrical characteristics is provided. High performance and high reliability of a semiconductor device including the transistor is achieved. A first conductor is formed over a substrate, a first insulator is formed over the first conductor, a layer that retains fixed charges is formed over the first insulator, a second insulator is formed over the layer that retains fixed charges, and a transistor is formed over the second insulator. Threshold voltage Vth is controlled by appropriate adjustment of the thicknesses of the first insulator, the second insulator, and the layer that retains fixed charges.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 4, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Kazuki Tanemura, Daisuke Matsubayashi
  • Patent number: 11211447
    Abstract: A semiconductor device includes a substrate, a bottom electrode on the substrate, a first support layer on the substrate next to a sidewall of the bottom electrode, a dielectric layer covering the sidewall and a top surface of the bottom electrode, and a top electrode on the dielectric layer. The bottom electrode includes a first part having a plurality of protrusions that protrude from a sidewall of the first part. The first part of the bottom electrode may be on the first support layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: December 28, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyukwoo Kwon, Ha-Young Yi, Byoungdeog Choi, Seongmin Choo
  • Patent number: 11204799
    Abstract: A semiconductor device capable of suppressing performance degradation and systems using the same are provided. The semiconductor device includes a plurality of processors CPU1 and CPU2, a scheduling device 10 (ID1) connected to the processors CPU1 and CPU2 for controlling the processors CPU1 and CPU2 to execute a plurality of tasks in real time, memories 17 and 18 accessed by the processors CPU1 and CPU2 to store data by executing the tasks, and access monitor circuits 15 for monitoring accesses to the memories by the processors CPU1 and CPU2. When an access to the memory is detected by the access monitor circuit 15, the data stored in the memory 18 is transferred based on the destination information of the data stored in the memory 18.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: December 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuo Sasaki
  • Patent number: 11200940
    Abstract: According to one implementation of the present disclosure, a memory array to block read-access of uninitialized memory locations is disclosed. The memory array includes: a plurality of memory cells apportioned into a plurality of memory columns and a plurality of memory rows, where each of the memory cells is configured to store a single bit of memory data; and one or more initialization columns corresponding to at least one of the plurality of memory columns. The initialization state of a memory row of the memory cells may be configured to be stored in: the memory row; a latch of word-line driver circuitry coupled to the memory array; or a memory cell of the one or more initialization columns of a corresponding row of the plurality of memory rows of the memory array.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 14, 2021
    Assignee: Arm Limited
    Inventors: Pranay Prabhat, James Edward Myers, Graham Peter Knight
  • Patent number: 11201154
    Abstract: A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Song Guo, Sanh D. Tang, Shen Hu, Yan Li, Nicholas R. Tapias
  • Patent number: 11200927
    Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zhi Qi Huang, Wei Lu Chu, Dong Pan
  • Patent number: 11189529
    Abstract: Methods of producing a self-aligned structure comprising a metal chalcogenide are described. Some methods comprise forming a metal-containing film in a substrate feature and exposing the metal-containing film to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise forming a metal-containing film in a substrate feature, expanding the metal-containing film to form a pillar and exposing the pillar to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise directly forming a metal chalcogenide pillar in a substrate feature to form a self-aligned structure comprising a metal chalcogenide. Methods of forming self-aligned vias are also described.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: November 30, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Amrita B. Mullick, Srinivas Gandikota
  • Patent number: 11176992
    Abstract: The present disclosure discloses a memory write operation apparatus to perform write operation on a selected memory unit coupled to two bit lines that includes a coupling capacitor, a charge sharing circuit, a write operation driving circuit, a charging circuit and a negative voltage coupling circuit. The charge sharing circuit electrically couples a first terminal of the coupling capacitor and a first bit line to receive charges therefrom to perform charging. The negative voltage coupling circuit electrically couples the first terminal of the coupling capacitor to a ground terminal during a negative voltage generation time period such that a second terminal of the coupling capacitor couples a negative voltage to the first bit line to perform write operation.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: November 16, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Hung-Yu Lee
  • Patent number: 11177145
    Abstract: A method of manufacturing a plurality of electronic circuits is disclosed. Each electronic circuit comprises a respective first portion, comprising a respective group of contact pads, and a respective integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad. The method comprises: providing a first structure comprising the plurality of first portions; providing a second structure comprising the plurality of ICs and a common support arranged to support the plurality of ICs; transferring said ICs from the common support onto a first roller having a removable surface portion; and transferring said ICs from the first roller onto the first structure such that each group of terminals is mounted on a respective group of contact pads.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: November 16, 2021
    Assignee: PRAGMATIC PRINTING LTD.
    Inventors: Neil Davies, Richard Price, Stephen Devenport, Stuart Speakman
  • Patent number: 11164625
    Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Vijay S. Ramesh, Allan Porterfield
  • Patent number: 11158645
    Abstract: According to one embodiment, a semiconductor memory device including a first memory cell; a word line; a bit line; a row decoder; a sense amplifier including a latch circuit; a data register; and a control circuit capable of suspending a write operation during the write operation of the first memory cell to perform a read operation of the first memory cell. In a read operation of the first memory cell performed while suspending the write operation, the row decoder applies a read voltage to the word line, and the sense amplifier transmits data read from the first memory cell to the data register as read data when writing to the first memory cell is completed, and transfers write data held by the latch circuit to the data register as the read data when the writing is not completed.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: October 26, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Koichiro Yamaguchi
  • Patent number: 11158262
    Abstract: A display device includes a display panel including pixels; a panel driver to supply a scan signal and a data signal to the pixels; and a power supply to generate a first supply voltage and a second supply voltage, and to change the first supply voltage and/or the second supply voltage to provide it to the pixels. The pixels emit light in response to the scan signal based on the data signal during an emission period where a voltage difference between the first supply voltage and the second supply voltage is larger than a first reference voltage. A first voltage difference between the first supply voltage and the second supply voltage at a start of the emission period is larger than an average voltage difference between the first supply voltage and the second supply voltage throughout the emission period.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: October 26, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Bon Seog Gu, Hong Soo Kim, Woo Mi Bae, Ki Wan Ahn, Joo Sun Yoon, Chong Chul Chai
  • Patent number: 11152056
    Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. A true digit-line has a short first region along the first deck and a long second region along the second deck. A complementary digit-line has a long first region along the first deck and a short second region along the second deck. A first set of first memory cells is associated with the true digit-line. The first set includes a first subset along the short first region, a second subset along a portion of the long second region, and a third subset along another portion of the long second region. A routing region of the true digit-line extends between the second and third subsets of the first memory cells. A connection extends from the short first region to the routing region of the true digit-line.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Seung Yeong Seo, Myung Ho Bae
  • Patent number: 11126548
    Abstract: An apparatus having a memory array. The memory array having a first section and a second section. The first section of the memory array including a first sub-array of memory cells made up of a first type of memory. The second section of the memory array including a second sub-array of memory cells made up of the first type of memory with a configuration to each memory cell of the second sub-array that is different from the configuration to each cell of the first sub-array. Alternatively, the section can include memory cells made up of a second type of memory that is different from the first type of memory. Either way, the second type of memory or the differently configured first type of memory has memory cells in the second sub-array having less memory latency than each memory cell of the first type of memory in the first sub-array.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Dmitri Yudanov
  • Patent number: 11099922
    Abstract: An information handling system includes a device and a baseboard management controller. The device is configured to communicate with a processor of the information handling system. The baseboard management controller is configured to communicate with the device via an in-band communication channel. The baseboard management controller determines whether data is received from the device via an in-band communication channel, and determines whether the baseboard management controller may communicate with the device via an out-of-band communication channel. In response to the data not being received and the baseboard management controller not able to communicate with the device, the baseboard management controller detects a failure of the device. In response to the detection of the failure of the device, the baseboard management controller isolates the device.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: August 24, 2021
    Assignee: Dell Products L.P.
    Inventors: Rama Rao Bisa, Johan Rahardjo, Pavan Kumar Gavvala, Elie Antoun Jreij, Akkiah Choudary Maddukuri, Isaac Qin Wang
  • Patent number: 11100978
    Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 24, 2021
    Assignee: Surecore Limited
    Inventors: Stefan Cosemans, Bram Rooseleer
  • Patent number: 11094698
    Abstract: A semiconductor storage device according to the present embodiment includes a plurality of first wires provided above a surface of a semiconductor substrate to extend in a first direction, and a plurality of second wires provided above the first wires to extend in a second direction crossing the first direction. A plurality of capacitor elements are arranged every other intersection region among intersection regions between the first wires and the second wires as viewed from above the surface of the semiconductor substrate. A plurality of transistors are provided above the capacitor elements to correspond thereto, respectively. A first distance between two of the capacitor elements, which are adjacent to each other in the first direction, is narrower than a second distance between two of the capacitor elements, which are adjacent to each other in the second direction.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: August 17, 2021
    Assignee: Kioxia Corporation
    Inventor: Tsuneo Inaba
  • Patent number: 11088289
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: August 10, 2021
    Assignee: Mosaid Technologies Incorporated
    Inventor: Hyoung Seub Rhie
  • Patent number: 11087839
    Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 10, 2021
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Jungho Yoon, Cheol Seong Hwang, Soichiro Mizusaki, Youngjin Cho
  • Patent number: 11087791
    Abstract: A data storage drive includes a magnetic recording media comprising a ferroelectric layer between a bottom electrode layer and a top electrode layer. An applied voltage to the ferroelectric layer generates a strain that is transferred to a ferromagnetic recording layer formed proximate to the ferroelectric layer. The change in strain transferred to the recording layer changes the magnetic properties of the recording layer. A voltage can be selectively applied to all or part of the ferroelectric layer to place the ferromagnetic recording layer in a low coercivity state to assist in writing data. Voltage-assisted magnetic recording (VAMR) is provided based upon control of a magnetic recording media comprising a ferroelectric layer between a bottom electrode layer and a top electrode layer.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: August 10, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Alan Kalitsov, Kumar Srinivasan, Bhagwati Prasad
  • Patent number: 11081594
    Abstract: In a display panel according to the disclosure, the display panel includes a substrate, an active layer having a source region, a drain region and a channel region on the substrate, a source electrode contacted with the source region, a drain electrode contacted with the drain region, an upper gate electrode above the active layer, and a lower gate electrode below the active layer. An edge of the lower gate electrode closest to the drain region overlaps with the channel region, and the source region and the drain region do not overlap with the upper gate electrode. The driving element constituting the display panel can generate a high driving current without deteriorating the characteristics thereof, thereby stably maintaining the luminance of the display panel.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 3, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sunyoung Choi, Kummi Oh
  • Patent number: 11074953
    Abstract: The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Shunpei Yamazaki
  • Patent number: 11062753
    Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Charles L. Ingalls, Scott J. Derner