Capacitors Patents (Class 365/149)
  • Patent number: 10734066
    Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 10733059
    Abstract: An image formation apparatus includes a first non-volatile memory, a second non-volatile memory smaller in allowable number of times of rewriting of data than the first non-volatile memory and higher in rate of reading of data than the first non-volatile memory, and a processor. The processor backs up control data for the image formation apparatus to the first non-volatile memory, backs up the control data to the second non-volatile memory less frequently than to the first non-volatile memory, and reads the control data from the second non-volatile memory when the control data stored in the first non-volatile memory matches with the control data stored in the second non-volatile memory at the time of start-up of the image formation apparatus and otherwise reads the control data from the first non-volatile memory.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: August 4, 2020
    Assignee: KONICA MINOLTA, INC.
    Inventor: Masatoshi Hitaka
  • Patent number: 10727222
    Abstract: A memory system is provided. The memory system includes a number of memory cells and a number of bit lines. The memory cells are interlocked with each other in rows and columns. The memory cells include respective capacitors, respective first transistors and respective second transistors. Respective upper plates of the respective capacitors are electrically connected to respective gates of the respective first transistors, and respective drains of the respective second transistors are connected to respective sources of the respective first transistors. The bit lines are arranged along an extending direction of the rows. Respective bit lines are connected to the respective first transistors through respective bit-line contacts, and each of the respective bit-line contacts is shared by two adjacent memory cells of the extending direction of the rows.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Patent number: 10726887
    Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory blocks. The peripheral circuit performs a dummy operation on a dummy area among the plurality of memory blocks of the memory cell array.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Jong Wook Kim, Tae Un Youn
  • Patent number: 10726919
    Abstract: Apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. The method can include determining whether a data pattern of the number of data patterns matches the target data pattern.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 10720193
    Abstract: A system and method for efficiently managing switching power of bit lines. In various embodiments, a first bit line in a memory array is pre-charged in multiple discrete steps, rather than in one continuous step. For a read operation that completed and read a logic low level from a first storage node, the first bit line is pre-charged from a ground reference level to a first power supply voltage. Similarly, a second bit line corresponding to a second storage node storing an inverse voltage level of the first storage node is pre-charged from a larger second power supply voltage to the smaller first power supply voltage. When the first time interval has elapsed, the first and second bit lines are pre-charged from the first power supply voltage to the second power supply voltage during a second time interval. Discrete steps are also used for pre-charging after write operations.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 21, 2020
    Assignee: Apple Inc.
    Inventors: Yildiz Sinangil, Mohamed H. Abu-Rahma
  • Patent number: 10712624
    Abstract: A method for producing an active matrix substrate includes the steps of: (A) forming in individual pixels a thin-film transistor element, a first insulating film, a pixel electrode to be connected to a drain electrode of the thin-film transistor element through a contact hole formed at least in the first insulating film, a second insulating film, and a common electrode to be superposed on the pixel electrode outside the contact hole, with the second insulating film in between; (B) detecting a short-circuited pixel among the pixels; (C) removing the pixel electrode inside the contact hole in the short-circuited pixel and thereby isolating the pixel electrode from the drain electrode; and (D) forming a through hole that penetrates the second insulating film outside the contact hole in the short-circuited pixel, and connecting the pixel electrode and the common electrode to each other through the through hole.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: July 14, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Akifumi Morishima
  • Patent number: 10714175
    Abstract: Disclosed are methods, systems and devices for operation of correlated electron switch (CES) devices. In one aspect, a CES device may be placed in any one of multiple impedance states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. In one implementation, a CES device may be placed in a high impedance or insulative state, or two more distinguishable low impedance or conductive states.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: July 14, 2020
    Assignee: ARM, Ltd.
    Inventors: Bal S. Sandhu, Glen Arnold Rosendale
  • Patent number: 10707200
    Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: July 7, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Takayuki Tsutsui, Isao Obu, Yasuhisa Yamamoto
  • Patent number: 10706911
    Abstract: A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: July 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hun Seo, Kyung-Ryun Kim
  • Patent number: 10699777
    Abstract: The beginning of using Complementary Metal-Oxide-Semiconductor (CMOS) process technology to implement Static Random-Access Memory (SRAM) which transistor number is six. And then reducing transistor number for increasing integration density, but it will diminish the stability of memory, and also may enhance the complexity of access circuit, thus increasing the power consumption. For increasing the integration density of SRAM, and according to the electrical characteristics of reduced transistor number therefore designing the memory possess low power consumption and its corresponding circuits, and then implementing an access system. If electrical characteristic of the other various memories are similar to SRAM, such as Dynamic Random-Access Memory (DRAM), so they can also use the corresponding access circuit of SRAM.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: June 30, 2020
    Inventor: Chao-Jing Tang
  • Patent number: 10685952
    Abstract: A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10680001
    Abstract: In the non-volatile semiconductor memory device, a mobile charge collector layer, a mobile charge collecting contact, a mobile charge collecting first wiring layer, an in-between contact between the mobile charge collector layers, and a mobile charge collecting second wiring layer are disposed adjacent to a floating gate. Thereby, without increasing areas of active regions in the non-volatile semiconductor memory device, the number of mobile charges collected near the floating gate is reduced. The non-volatile semiconductor memory device allows high-speed operation of a memory cell while reducing fluctuations in a threshold voltage of the memory cell caused by collection of the mobile charges, which are attracted from an insulation layer, near the floating gate.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: June 9, 2020
    Assignee: FLOADIA CORPORATION
    Inventors: Yasuhiro Taniguchi, Yasuhiko Kawashima, Hideo Kasai, Yutaka Shinagawa, Ryotaro Sakurai, Kosuke Okuyama
  • Patent number: 10635131
    Abstract: A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: April 28, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Yonatan Tzafrir
  • Patent number: 10636494
    Abstract: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. When the sense circuit is connected to the unselected bit line during the sense operation, the sense circuit is locked out in order to reduce current consumption. However, noise from the locked out sense circuit may be transmitted to the sense circuits connected to the selected bit lines through adjacent bit line coupling. In order to reduce the effect of the noise, charge transfer from the sense node may be blocked from passing to the unselected bit lines. Or, charge may be drained from the sense node, thereby preventing the charge from passing to the unselected bit lines.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: April 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Stanley Jeong, Wei Zhao, Huai-yuan Tseng, Deepanshu Dutta
  • Patent number: 10636479
    Abstract: A semiconductor memory device includes a first memory cell that includes a first transistor and a first capacitor, a second transistor having a first terminal that is connected to a first terminal of the first memory cell, a first bit line that is connected to a second terminal of the first memory cell, a second bit line that is connected to a second terminal of the second transistor, and a controller that turns on the first transistor and turns off the second transistor during a write operation on the first memory cell and turns on the first transistor and the second transistor during a read operation on the first memory cell.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji Ikeda, Chika Tanaka
  • Patent number: 10629443
    Abstract: A method for manufacturing a semiconductor device includes forming a first active region on a semiconductor substrate, forming a semiconductor layer on the first active region, patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located at bottom ends of the plurality of fins, forming a silicide layer on exposed portions of the first active region, forming an electrically conductive contact on the silicide region, forming a second active region on top ends of each of the plurality of fins, and forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie, Junli Wang
  • Patent number: 10622070
    Abstract: In one embodiment, a device is described for using ferroelectric material in a memory cell without a selector device. In another embodiment, a method of operating a ferroelectric memory cell without a selector device is described. Other embodiments are likewise described.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: April 14, 2020
    Assignee: AP Memory Corp, USA
    Inventor: Wenliang Chen
  • Patent number: 10622057
    Abstract: A sensing system can read from a memory cell configured to store a data bit and to produce a differential signal indicating a data state of the memory cell. The data state can be selected from three data states. An example of the system can include a pair of bit lines, a pair of sense amplifiers (SAs), and a data output circuit. The bit lines are coupled to the memory cell to receive the differential signal. The SAs are each independently coupled to the bit lines through an isolation circuit. The data output circuit can receive outputs from the SAs and indicate the data state of the memory cell based on the outputs.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Charles L. Ingalls, Scott J. Derner
  • Patent number: 10600475
    Abstract: This invention uses a novel mechanism to store a matrix of numbers or any two dimensional array of binary values in a novel storage entity called a Matrix Space. A matrix space which may reside in a processing unit, is designed to store a plurality of matrices or arrays of values into arrays of volatile or non-volatile memory cells or latch or flip-flop elements much like in a memory, but with accessibility in two or three dimensions. In this invention any row and/or any column of storage elements in a storage array is directly accessible for writing, reading or clearing via row bit lines and column bit lines, respectively. The elements in rows of arrays are selected or controlled for access using row address lines and the elements in columns of arrays are selected or controlled for access using column address lines. This allows access to data stored in matrix space arrays for use in matrix and array computations, by both rows and columns of the arrays.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: March 24, 2020
    Inventor: Sitaram Yadavalli
  • Patent number: 10558613
    Abstract: A storage system in one embodiment comprises a plurality of storage devices storing data pages. Each data page has a content-based signature derived from that data page. The content-based signatures are associated with physical locations storing the data pages. In response to receipt of a write input/output (IO) request that includes a data segment that is smaller than a page granularity of the storage devices, a content-based signature associated with the data segment is determined which also corresponds to a target data page stored at one of the physical locations. In response to determining the content-based signature, an inflight write count corresponding to the content-based signature is incremented. In response to a decrement request to decrement a reference count of the physical location corresponding to the content-based signature, a decrement flag corresponding to the content-based signature is set in the data structure and the decrement request is postponed.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: February 11, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Shveidel, Lior Kamran, Oran Baruch
  • Patent number: 10553726
    Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: February 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kosei Noda, Kouhei Toyotaka, Kazunori Watanabe, Hikaru Harada
  • Patent number: 10553594
    Abstract: Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line coupled to a first capacitor plate of a ferroelectric capacitor of a memory cell, sharing a second voltage to decrease a voltage of a second sense line coupled to a second capacitor plate of the ferroelectric capacitor of the memory cell, sharing a third voltage to increase the voltage of the second sense line, and sharing a fourth voltage to decrease the voltage of the first sense line. A voltage difference between the first sense line and the second sense line that results from the voltage sharing is amplified, wherein the voltage difference is based at least in part on a polarity of the ferroelectric capacitor.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Yasushi Matsubara
  • Patent number: 10539997
    Abstract: The disclosure generally relates to a memory power reduction scheme that can flexibly transition memory blocks among different power states to reduce power consumption (especially with respect to leakage power) in a manner that balances tradeoffs between reduced power consumption and performance impacts. For example, according to various aspects, individual memory blocks may be associated with an access-dependent age, whereby memory blocks that are not accessed may be periodically aged. As such, in response to the age associated with a memory block crossing an appropriate threshold, the memory block may be transitioned to a power state that generally consumes less leakage power and has a larger performance penalty. Furthermore, one or more performance-related criteria may be defined with certain memory blocks to prevent and/or automatically trigger a transition to another power state.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: January 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Giby Samson, Parixit Laljibhai Aghera, Adam Edward Newham
  • Patent number: 10535399
    Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Patent number: 10529401
    Abstract: Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10529425
    Abstract: A semiconductor apparatus may include a unit memory region, a first column main decoder, a second column main decoder, and a control circuit. The unit memory region may include a plurality of sub-memory regions. The first and second column main decoders may be configured to receive and decode a column pre-decoding signal and configured to generate a respective column select signal for controlling a column access of a respective first and second half of the plurality of sub-memory regions. The control circuit may be configured to provide the column pre-decoding signal to the first or second column main decoders based on their proximities to a sub-memory region to be enabled among the plurality of sub-memory regions.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: January 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Jung Hwan Ji, Sang Ho Lee, Ho Don Jung, Jun Hyun Chun
  • Patent number: 10529413
    Abstract: The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: January 7, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Junpei Sugao
  • Patent number: 10529410
    Abstract: Techniques are described herein for mitigating parasitic signals induced by state transitions during an access operation of a selected memory cell in a memory device. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended coupling between various components of the memory device may occur during an access operation. To mitigate parasitic signals induced by the unintended coupling, the memory device may isolate the selected memory cell from a selected digit line during certain portions of the access operation. The memory device may isolate the selected memory cell when the plate transitions from a first voltage to a second, when the selected digit line transitions from a third voltage to a fourth voltage, or a combination thereof.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Di Vincenzo, Lucia Di Martino
  • Patent number: 10529720
    Abstract: A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. The trench openings have walls therein extending longitudinally in and along the individual trench openings against laterally-opposing sides of the trenches. At least some of the insulative material that is under the trench openings is removed through bases of the trench openings between the walls and the masked portions to form individual capacitor openings in the insulative material that is lower than the walls. Individual capacitors are formed in the individual capacitor openings. A line of access transistors is formed in the individual trenches. The line of access transistors electrically couples to the individual capacitors that are along that line.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Patent number: 10522214
    Abstract: A reliability aware negative bit-line write assist (RA-NBL) circuit comprises a coupling capacitor to provide a negative bump for write assist, and a control input generator control charging of the coupling capacitor, such that the negative bump is high at a low voltage, and the negative bump is low at a high voltage.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: December 31, 2019
    Assignee: Synopsys, Inc.
    Inventors: Sudhir Kumar, Vinay Kumar, Sumit Srivastava, Nikhil Puri
  • Patent number: 10505108
    Abstract: A memcapacitor according to an embodiment includes a first electrode, a first dielectric layer provided on the first electrode, a plurality of variable resistance portions provided separately from each other on the first dielectric layer, a second dielectric layer provided on the first dielectric layer and between the variable resistance portions, and a second electrode provided on the variable resistance portions and the second dielectric layer. Each of the variable resistance portions is formed of a material that allows diffusion of metal atoms constituting the second electrode to inside of the variable resistance portion, and the second dielectric layer is formed of a material that prevents diffusion of the metal atoms constituting the second electrode to inside of the second dielectric layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 10, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Jun Deguchi, Yoshifumi Nishi, Masamichi Suzuki, Fumihiko Tachibana, Makoto Morimoto, Yuichiro Mitani
  • Patent number: 10497428
    Abstract: A semiconductor memory device includes a memory cell that stores multi-bit data, and a bit line sense amplifier that is connected to a bit line of the memory cell and a complementary bit line corresponding to the memory cell in an open bit line structure. The bit line sense amplifier includes a first latch that sequentially senses a first bit and a second bit of the stored multi-bit data and transmits the sensed first bit to a second latch, and a second latch that senses the transmitted bit from the first latch.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungryun Kim, Younghun Seo, Soobong Chang
  • Patent number: 10497420
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Smith, Michael A. Shore
  • Patent number: 10489309
    Abstract: A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a storage unit to store a page table entry including one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode, a first permission register including a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode, and a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: David A. Koufaty, Gilbert Neiger, Rajesh M. Sankaran, Andrew V. Anderson, Subramanya R. Dulloor, Werner Haas, Joseph Nuzman
  • Patent number: 10482981
    Abstract: Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a refresh operation is performed repeatedly to couple up data word line voltages but not dummy word line voltages. The refresh operation can involve applying a voltage pulse to the data word lines of a block when the block is not being used for a storage operation such as a program, read or erase operation. When the voltage pulse is applied to the data word lines, the dummy word lines can be set to a low level such as 0 V. This low level prevents or limits coupling up of the dummy memory cells to avoid creating an electric field which can cause holes to move from the dummy memory cells to adjacent select gate transistors.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 19, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Vinh Diep
  • Patent number: 10482951
    Abstract: The beginning of using Complementary Metal-Oxide-Semiconductor (CMOS) process technology to implement Static Random-Access Memory (SRAM) which transistor number is six. And then reducing transistor number for increasing integration density, but it will diminish the stability of memory, and also may enhance the complexity of access circuit, thus increasing the power consumption. For increasing the integration density of SRAM, and according to the electrical characteristics of reduced transistor number therefore designing the memory possess low power consumption and its corresponding circuits, and then implementing an access system. If electrical characteristic of the other various memories are similar to SRAM, such as Dynamic Random-Access Memory (DRAM), so they can also use the corresponding access circuit of SRAM.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: November 19, 2019
    Inventor: Chao-Jing Tang
  • Patent number: 10461211
    Abstract: The invention pertains to a process for producing an array (1) of mesa-structured photodiodes (2), including at least the following steps: a) producing a useful layer (3); b) producing an etch mask formed of a plurality of etch pads (20); c) wet-etching part of the useful layer (3) located between the etch pads (20), forming a plurality of mesa-structured photodiodes (2), producing a recess (21); d) conformally depositing a passivation layer (14); e) removing the etch pads (20) by chemical dissolution; f) producing conductive pads (11).
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: October 29, 2019
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Giacomo Badano, Clement Lobre, Roch Espiau de Lamaestre, Jean-Paul Chamonal
  • Patent number: 10453863
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: October 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
  • Patent number: 10447345
    Abstract: An embodiment near-field communication (NFC) router, includes a first switch coupled between a first terminal of the NFC router and a second terminal of the NFC router; and a rectifier bridge having an output terminal coupled to a control terminal of the first switch, the rectifier bridge being configured to rectify a signal detected by an antenna external to the NFC router.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 15, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Nathalie Vallespin
  • Patent number: 10446199
    Abstract: A semiconductor device may include a latch circuit configured for storing a row address including information on a position where a smart refresh operation has been performed, as a storage address. The semiconductor device may include a refresh control circuit configured for controlling, depending on a result of comparing a row address inputted from an exterior and the storage address, a smart refresh operation to be performed for the row address, and omitting the smart refresh operation based on the row address and the storage address being the same combination.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang Ah Hyun, Yunyoung Lee
  • Patent number: 10424350
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array of memory cells. The sensing circuitry includes a primary latch and a secondary latch. The primary latch is coupled to a pair of complementary sense lines and selectively coupled to a pair of adjacent complementary sense lines. The secondary latch is selectively coupled to the primary latch. The primary latch and secondary latch are configured to shift a data value between the pair of adjacent complementary sense lines and the primary latch. The primary latch and secondary latch are configured to shift the data value from the pair of adjacent complementary sense lines without activating a row line.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 10423203
    Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Rafael Rios, Somnath Paul, Muhammad M. Khellah
  • Patent number: 10410964
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kanta Saino
  • Patent number: 10403388
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells. Cells may be selected in pairs in order to accommodate an electric current relationship, such as a short, between cells that make up the pair. Cells may be arranged in cell plate groups, and a pair of cells may include a first cell plate from one cell plate group and a second cell plate from the same cell plate group or from another, adjacent cell plate group. So a pair of cell plates may include cell plates from different cell plate groups. The first and second cell plates may be selected as a pair or a group based at least in part on the electric current relationship between the cell plates.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Richard E. Fackenthal, Charles L. Ingalls
  • Patent number: 10403627
    Abstract: The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: September 3, 2019
    Assignee: IMEC vzw
    Inventors: Jan Van Houdt, Julien Ryckaert, Hyungrock Oh
  • Patent number: 10403389
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Patent number: 10395992
    Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10394618
    Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Briana E. Foxworth, Saravanan Sethuraman, Kevin M. Mcilvain, Lucas W. Mulkey, Adam J. McPadden
  • Patent number: 10388360
    Abstract: An example apparatus includes a memory device having first sensing circuitry positioned adjacent an edge of an edge array section and selectably coupled to a row memory cells, the first sensing circuitry including a first sense amplifier selectably coupled via a first sense line to a first memory cell in the row and via a second sense line to the first memory cell. The example apparatus includes second sensing circuitry positioned at an opposite edge of the edge array section and selectably coupled to the row via a third sense line, the second sensing circuitry including a second sense amplifier selectably coupled via the third sense line to a second memory cell in the row. The example apparatus further includes a component positioned outside the edge array section and proximate the first sensing circuitry, the component configured to perform an operation based on data sensed by the first sensing circuitry.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush