Abstract: Memory systems and memory programming methods are described.

Abstract: A liquid electrochemical memory device is provided. In one aspect, the device includes a memory region for storing at least two bits, the memory region having a first volume; and a liquid electrolyte region fluidically connected to the memory region, the liquid electrolyte region having a second volume larger than the first volume. The device further includes a working electrode exposed to the memory region, and a counter electrode exposed to the liquid electrolyte region. The device also includes an electrolyte filling the memory region and the liquid electrolyte region, in physical contact with the working electrode and the counter electrode, the electrolyte including at least two conductive species. The device further includes a control unit for biasing the working electrode and the counter electrode.

Abstract: A variable resistance element according to the present invention comprises a configuration in which an ion conduction layer is arranged between an upper electrode and a lower electrode, wherein a recess part is formed on a surface of the lower electrode of the variable resistance element, and the ion conduction layer is formed in contact with at least the recess part on a surface of the lower electrode.

Abstract: A device including an array of aligned conductive channels. The conductive channels are operable for directional transport of species selected from the group consisting of electrons, ions, phonons, and combinations thereof. The conductive channels are provided for by nanofibers in a form selected from the group consisting of ribbons, sheets, yarns, and combinations thereof.

Abstract: The present disclosure relates to a Turing machine having a reactor comprising a reactant solution comprising a reactant; a first chemical species source to provide a selected amount of a first chemical species; a second chemical species source to provide a selected amount of a second chemical species; one or more controllers coupled to control the addition of the first and second chemical species from the first and second chemical species sources responsive to an input; and a sensor positioned to sense changes in the reactant as the controller controls the first and second chemical species sources to add selected amounts of the respective first and second chemical species to the reactor. The controller receives signals corresponding to the state of the reactant and correlates the states of the reactant to a result that is computed as a function of the input.

Abstract: A high voltage generating circuit for a resistive memory apparatus is provided. The high voltage generating circuit includes a capacitor spaced from a semiconductor substrate and electrically insulated from the semiconductor substrate. A switching device, which is electrically connected to the capacitor, is electrically insulated from the semiconductor substrate.

Abstract: Providing for rectified-switching of a two-terminal solid state memory cell is described herein. By way of example, the subject disclosure provides a solid state device exhibiting rectified resistive switching characteristics that can be fabricated with semiconductor fabrication techniques. The solid state device can comprise a metal ion layer adjacent to an electrically resistive diffusion layer, which is at least in part permeable to conductive ions of the metal ion layer. A pair of electrodes can be placed, respectively, on opposite sides of the adjacent ion layer and electrically resistive diffusion layer to facilitate operating on the two-terminal solid state memory cell. In operation, a program voltage induces conductive ions to form a semi-stable conductive filament within the diffusion layer, which partially deforms in response to reduction in the program voltage.

Abstract: An integrated circuit (IC) device can include a plurality of memory cells with programmable impedance elements. A circuit can be configured to read a data value stored by an element of a memory cell by application of at least one read voltage pulse and at least one relaxation voltage pulse across the terminals of the element; wherein the read voltage pulse has a same polarity as a voltage used to program the element, the relaxation voltage pulse has a different polarity than the read voltage pulse, and neither the read or relaxation voltage pulses program the element to a particular impedance state.

Abstract: A memory device can include a plurality of memory cells each comprising at least one programmable impedance memory element; a programming circuit coupled to the memory elements and configured to apply at least one time varying pulse to memory elements to place them into one of at least two different impedance states; and a programming voltage source coupled to the programming circuit configured to generate the at least one time varying pulse; wherein the time varying pulse decreases and increases in potential while having an overall increase in one voltage polarity.

Abstract: A solid-state, multi-valued, molecular random access memory (RAM) device, comprising an electrically, optically and/or magnetically addressable unit, a memory reader, and a memory writer. The addressable unit comprises a conductive substrate; one or more layers of electrochromic, magnetic, redox-active, and/or photochromic materials deposited on the conductive substrate; and a conductive top layer deposited on top the one or more layers. The memory writer applies a plurality of predetermined values of potential biases or optical signals or magnetic fields to the unit, wherein each predetermined value applied results in a uniquely distinguishable optical, magnetic and/or electrical state of the unit, thus corresponding to a unique logical value. The memory reader reads the optical, magnetic and/or electrical state of the unit.

Abstract: An RC-based sensing scheme to effectively sense the cell resistance of a programmed Phase Change Material (PCM) memory cell. The sensing scheme ensures the same physical configuration of each cell (after programming): same amorphous volume, same trap density/distribution, etc. The sensing scheme is based on a metric: the RC based sense amplifier implements two trigger points. The measured time interval between these two points is used as the metric to determine whether the programmed cell state, e.g., resistance, is programmed into desired value. The RC-based sensing scheme is embedded into an iterative PCM cell programming technique to ensure a tight distribution of resistance at each level after programming; and ensure the probability of level aliasing is very small, leading to less problematic drift.

Abstract: Phase-change memory devices are provided. A phase-change memory device may include a substrate and a conductive region on the substrate. Moreover, the phase-change memory device may include a lower electrode on the conductive region. The lower electrode may include a metal silicide layer on the conductive region, and a metal silicon nitride layer including a resistivity of about 10 to about 100 times that of the metal silicide layer. Moreover, the lower electrode may include a metal oxide layer between the metal silicon nitride layer and the metal silicide layer. The metal oxide layer may include a resistivity that is greater than that of the metal silicide layer and less than the resistivity of the metal silicon nitride layer. The phase-change memory device may also include a phase-change layer and an upper electrode on the lower electrode.

Abstract: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Abstract: Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer.

Abstract: Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed.

Abstract: An integrated circuit (IC) device can include a memory array having memory elements formed with a solid ion conductor, the memory array programmable to provide portions with different response types; and a logic section comprising logic circuits configured to perform logic functions, the logic section being coupled to the memory array to store and read data values therefrom. A memory device can also have a plurality of access ports, each configurable to access any of the different portions of the memory array. A memory device can further include a read circuit configured to read data values from the different portions according to the response type of each portion.

Abstract: A stateful negative differential resistance device includes a first conductive electrode and a second conductive electrode. The device also includes a first material with a reversible, nonvolatile resistance that changes based on applied electrical energy and a second material comprising a differential resistance that is negative in a locally active region. The first material and second material are sandwiched between the first conductive electrode and second conductive electrode. A method for using a stateful NDR device includes applying programming energy to the stateful NDR device to set a state of the stateful NDR device to a predetermined state and removing electrical power from the stateful NDR device. Power-up energy is applied to the stateful NDR device such that the stateful NDR device returns to the predetermined state.

Abstract: A memory element can include a memory layer formed between two electrodes; at least one element within the memory layer that is oxidizable in the presence of an electric field applied across the electrodes; and an inhibitor material incorporated into at least a portion of the memory layer that decreases an oxidation rate of the at least one element within the memory layer with respect to the memory layer alone. Methods of forming such a memory element are also disclosed.

Abstract: Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer.

Abstract: An integrated circuit memory device includes a memory cell array comprising memory cells having respective data storage regions therein, a plurality of pass transistors having different channel widths and/or channel lengths, and a plurality of conductive lines. Each of the conductive lines electrically couple a respective one of the pass transistors to ones of the memory cells. Each of the memory cells has a line resistance defined by a portion of the corresponding one of the conductive lines extending between the memory cell and the pass transistor coupled thereto. Ones of the memory cells having greater line resistances are coupled to ones of the pass transistors having greater channel widths and/or shorter channel lengths than ones of the memory cells having smaller line resistances. Each of the memory cells may also include a diode therein, and ones of the memory cells having greater line resistances may include diodes having lower resistances. Related devices are also discussed.

Abstract: Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed.

Abstract: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Abstract: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Abstract: One embodiment of the present invention includes a three dimensional memory array having a plurality of memory elements coupled to form the array through a single top lead and a single bottom lead, each memory element including a magnetic free layer in which non-volatile data can be stored, wherein each memory element possesses unique resonant frequencies associated with each digital memory state, thereby enabling frequency addressing during parallel write and read operations, each memory element further including a fixed layer and a spacer formed between the free layer and the fixed layer.

Abstract: A phase-change material for use in a phase-change memory device is provided. The phase-change material includes at least one metal and is reversibly phase-changeable, switchable, to a detectable metallic glass state or to a detectable crystalline state thereof. There is also provided a phase-change memory, that includes at least one phase change memory cell comprising the phase change material whereby the phase-change material and thereby the phase-change memory cell is reversibly programmable to one of these states. A method of fabricating the phase-change memory is also provided.

Abstract: A switching element according to the present invention includes an ion-conducting layer, first electrode 11 and second electrode 12 placed in contact with the ion-conducting layer, and third electrode 15 placed in contact with the ion-conducting layer and to control electrical conductivity between the first electrode and the second electrode, wherein the shortest distance between any two of first, second, and third electrodes 11, 12, and 13 is defined by the film thickness of the ion-conducting layer.

Abstract: A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier. The unit cell receives a plurality of voltage ranges to perform a plurality of operations. A read operation is performed when an input voltage is in a first voltage range. A first write operation is performed when the input voltage is in a second voltage range higher than the first voltage range. A second write operation is performed when the input voltage is in a third voltage range higher than the second voltage range. An erase operation is performed when the input voltage is higher than the third voltage range.

Abstract: A non-volatile electrochemical memory cell formed of a stack of thin films comprising at least one first active layer, suited to releasing and accepting, in a reversible manner, at least one ion species, at least one second active layer, suited to releasing and accepting said ion species, in a reversible manner, the active layers being based on materials having different compositions and electrochemical potential profiles.

Abstract: Metal-oxide based memory devices and methods for operating and manufacturing such devices are described herein. A method for manufacturing a memory device as described herein comprises forming a metal-oxide memory element, and applying an activating energy to the metal-oxide memory element. In embodiments the activating energy can be applied by applying electrical and/or thermal energy to the metal-oxide material.

Abstract: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Abstract: Non-volatile resistance change memories, systems, arrangements and associated methods are implemented in a variety of embodiments. According to one embodiment, a memory cell having two sections with outwardly-facing portions, the outwardly-facing portions electrically coupled to electrodes is implemented. The memory cell has an ionic barrier between the two sections. The two sections and the ionic barrier facilitate movement of ions from one of the two sections to the other of the two sections in response to a first voltage differential across the outwardly-facing portions. The two sections and the ionic barrier diminish movement of ions from the one of the two sections to the other of the two sections in response to another voltage differential across the outwardly-facing portions.

Abstract: Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed.

Abstract: A non-volatile memory device includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation.

Abstract: Using a synthetic molecular spring device in a system for dynamically controlling a system property, such as momentum, topography, and electronic behavior. System features (a) the synthetic molecular spring device having (i) at least one synthetic molecular assembly each featuring at least one chemical unit including at least one: (1) atom; (2) complexing group complexed to at least one atom; (3) axial ligand reversibly physicochemically paired with at least one complexed atom; and (4) substantially elastic molecular linker; and, (ii) an activating mechanism directed to at least one atom-axial ligand pair; and, (b) a selected unit operatively coupled to synthetic molecular assembly, and exhibiting the system property.

Abstract: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Abstract: An objective of the present invention is to provide a switching device that shows two markedly different stable resistance characteristics reversibly and repetitively, and which is applicable to highly integrated nonvolatile memories.

Abstract: A sequence or array of electrochemical cells storing both digital and analog data. Both binary code and codes having a higher base may be stored in the memory device to increase information density. Such battery arrays could also provide power for the micro or nanodevice. Devices are microscale and nanoscale in size and utilize electrically conductive atomic force microscopy tips to record and read data stored in the device.

Abstract: A non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.

Abstract: A memory cell is described, the memory cell comprising a dielectric rupture antifuse and a layer of a resistivity-switching material arranged electrically in series, wherein the resistivity-switching material is a metal oxide or nitride compound, the compound including exactly one metal. The dielectric rupture antifuse is ruptured in a preconditioning step, forming a rupture region through the antifuse. The rupture region provides a narrow conductive path, serving to limit current to the resistivity-switching material, and improving control when the resistivity-switching layer is switched between higher- and lower-resistivity states.

Abstract: Synthetic molecular spring device featuring: (a) a synthetic molecular assembly, SMA, each scalable chemical module including: (i) at least one atom, M, (ii) at least one complexing group, CG, complexed to an atom, M, (iii) at least one axial ligand, AL, reversibly physicochemically paired with at least one atom, M, complexed to a complexing group, CG, (iv) at least one substantially elastic molecular linker, ML, having body and two ends with at least one chemically bonded to another component of SMA; (b) activating mechanism, AM, operatively directed to an atom-axial ligand pair, whereby following activating mechanism, AM, sending activating signal, AS/AS?, to an atom-axial ligand pair for physicochemically modifying the atom-axial ligand pair, there is activating at least one cycle of spring-type elastic reversible transitions between contracted and expanded linear conformational states of molecular linker, ML. Optionally includes (v) chemical connectors, CC, and/or, (vi) binding sites, BS.

Abstract: A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

Abstract: A PMC memory including: a memory cell, the memory cell including, an active zone, a heating element disposed outside of the active zone, and at least two contacts that apply a writing voltage to the memory cell, wherein the heating element transitionally heats the memory cell-during a writing process in the memory cell to a writing temperature higher than an operating temperature of the memory cell outside the writing process.

Abstract: A method and apparatus for providing electric microcontact printing is provided. A stamp is brought into contact with the surface of a substrate to provide high resolution features. Aspects of the invention may be used for data storage, microcontact printing, and for other applications requiring high resolution pattern transfer.

Abstract: In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and spaced apart from the first word line by a first gap, the bit line extending in a second direction transverse to the first direction. A second word line structure is provided over the bit line and spaced apart from the bit line by a second gap, the second word line structure extending in the first direction.

Abstract: A nonvolatile memory, such as a write-once memory, includes a memory cell array that has first memory cells and at least one second memory cell. The memory also includes a first writing circuit that is capable of writing data to the first memory cells and the second memory cell, a second writing circuit, and a verify circuit which is capable of confirming whether the data is normally stored in the first memory cells. When the writing of data to one of the first memory cells fails, the second writing circuit is arranged to assign an address of the one of the first memory cells to the second memory cell. The first memory cells and the second memory cell are arranged to irreversibly change their electrical resistance when the data is stored in them. The first memory cells and the second memory cell include an organic compound layer interposed between a pair of electrodes.

Abstract: A non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.

Abstract: A non-volatile electrochemical memory cell formed of a stack of thin films comprising at least one first active layer, suited to releasing and accepting, in a reversible manner, at least one ion species, at least one second active layer, suited to releasing and accepting said ion species, in a reversible manner, the active layers being based on materials having different compositions and electrochemical potential profiles.

Abstract: There is provided a resistive memory device, the device including: a plurality of word lines and a plurality of bit lines arranged such that the word lines intersect the bit lines; a plurality of resistive memory cells each having a variable resistive material coupled between the corresponding word line and the corresponding bit line and an access element; selecting circuits selecting one of the plurality of resistive memory cells; and a filament-forming circuit supplying a filament-forming voltage to the selected resistive memory cell through the bit line coupled to the selected resistive memory cell while increasing the filament-forming voltage from a predetermined voltage level until filaments having a predetermined thickness are formed in the variable resistive material of the selected resistive memory cell.

Abstract: A bistable electrical device employing a bistable polymer body made from an electrically insulating polymer material in which doped nanofibers are dispersed. The doped nanofibers are composed of an electrically conductive nanofiber material and electrically conductive nanoparticles. The doped nanofibers impart bistable electrical characteristics to the polymer body, such that the polymer body is reversibly convertible between a low resistance state and a high resistance state by application of an electrical voltage.

Abstract: A switching element has an ion conductor capable of conducting metal ions for use in an electrochemical reaction therein, a first electrode and a second electrode which are disposed in contact with said ion conductor and spaced a predetermined distance from each other, and a third electrode disposed in contact with the ion conductor. When a voltage for causing the switching element to transit to an on state is applied to the third electrode, metal is precipitated between the first electrode and the second electrode by metal ions, electrically interconnecting the first electrode and the second electrode. When a voltage for causing the switching element to transit to an off state is applied to the third electrode, the precipitated metal is dissolved to electrically disconnect the first electrode and the second electrode from each other.