Abstract: A transistorless memory cell for storing information as one of two possible bistable current states comprises (i) at least one first transistorless device exhibiting N-type negative differential resistance, including a high-impedance region, a low-impedance region and a negative-resistance region and having a polarity and (ii) at least one second transistorless device exhibiting an exponential or linear current-voltage characteristic and coupled to the first transistorless device. The second transistorless device may be a diode or a resistor. The read/write operation of the transistorless memory cell is performed in a current mode.

Abstract: A new static memory cell based on the bistable operation of a three-terminal four layer semiconductor device working in the forward blocking state is disclosed. The power consumption of the memory cell is low. The switching speed of the memory cell is in the nanosecond range. The memory cell may be integrated into VLSI processes and is of a size suitable for VLSI applications. The memory cell comprises a semiconductor device which comprises: an n-type semiconductor cathode region; a p-type semiconductor gate region; a third semiconductor region adjacent the gate region; a fourth region adjacent the third semiconductor region; and a hole-injecting boundary between the third semiconductor region and the fourth region. The semiconductor device is preferably a p-n-p-n device. The gate current-voltage characteristics of the device comprise a negative resistance region. The device is designed to operate in a forward blocking low current state.

Abstract: A memory device includes a first address signal line, a pair of second address signal lines, a standby signal line, and a memory cell provided at a cross point at which the first address signal line crosses the pair of second address signal lines. The memory cell includes first and second elements connected, via a connection node, in series between the pair of second address signal lines in a forward direction, each of the first and second elements having a negative-differential conductance characteristic. A threshold diode is connected between the first address signal line and the connection node, and has a characteristic in which a current flows in the threshold diode when a voltage applied across the threshold diode exceeds threshold voltages. A gate is connected to the standby signal line and controls currents flowing in the first and second elements.

Abstract: A semiconductor memory device including a plurality of bit lines and a plurality of word lines which intersect to form a matrix of cross points. A respective memory cell is disposed at each cross point and corresponds to the respective word line and respective bit line intersecting at the respective cross point. Each memory cell includes a transfer gate having a first current terminal connected to the corresponding bit line and a control terminal connected to the corresponding word line. Each memory cell also includes a pair of serially connected negative differential resistance memory elements having an interconnection node therebetween. The interconnection node is connected to the second current terminal of the transfer gate.

Abstract: A back-bias level sensor used for a semiconductor device wherein a sensing current for sensing a back-bias voltage is prevented from directly flowing into the substrate (or the back-bias voltage terminal). The gate of a PMOS transistor is provided with the back-bias voltage while the source is provided with a ground voltage, so that a pump circuit performs the pumping operation to increase the back-bias voltage when the back-bias voltage is lower than a predetermined voltage level; otherwise, the pump circuit is de-energized, thereby reducing the back-bias voltage.

Abstract: A semiconductor memory device comprises a memory array including a plurality of memory cells arranged in a matrix form, a plurality of word lines arranged in column and a plurality of bit lines arranged in row. Each memory cell includes a bipolar transistor in which a collector-emitter voltage is controlled so that the polarity of a base current changes is changed in accordance with an increase in a base-emitter voltage, and a switching element, provided between the base of the bipolar transistor and an associated bit line and controllable by an associated word line. A switch circuit is provided for applying a collector voltage to the collector of the bipolar transistor smaller in a second state where an associated one of the memory cells is holding data than in a second state where the associated memory cell is accessible for data reading and data writing.

Abstract: A semiconductor memory device comprises a transistor and a resistor. The transistor has negative differential resistance characteristics in an emitter current or a source current thereof. Therefore the semiconductor memory device has few elements and a simplified configuration, and thus high speed operation and large scale integration can be realized. Further, in the semiconductor memory device of the present invention, several variations in design are possible.

Abstract: A semiconductor memory device comprises a transistor having such a current characteristic that a base current has a differential negative resistance characteristic and a collector current greatly flows after the differential negative resistance characteristic occurs in the base current when a base-emitter voltage is increased, a load coupled in series between a collector and a base of the transistor, first and second input terminals coupled to the base of the transistor through a base resistance of the transistor, and an ouptut terminal coupled to the collector of the transistor.

Abstract: A logic circuit including a resonant-tunneling transistor having a superlattice containing at least one quantum well layer, and a constant current source operatively connected between a base and an emitter of the transistor and supplying a constant current to said base. The transistor has a differential negative-resistance characteristic with at least one resonant point in a relationship between a current flowing in the base and a voltage between the base and emitter, and having at least two stable base current values at both sides of the resonant point on the characteristic, defined by the changeable base.multidot.emitter voltage. By supplying the base.multidot.emitter voltage having an amplitude of at least two amplitudes corresponding to the stable base current values, the transistor holds data corresponding to the base.multidot.emitter voltage.

Abstract: A semiconductor memory device comprises an address line, a write line, a read line, and a memory cell connected to the address, write and read lines, where the memory cell comprises a power source, an RHET, a switching element and a data transfer element. The power source is coupled to a base of the RHET through a first resistor so that the RHET has a plurality of stable states. The switching element is coupled between the write line and the base of the RHET, and is controlled by a signal from the address line. The data transfer element is coupled between a collector of the RHET and the read line, and the collector is coupled to the power source through a second resistor. When reading an information from the memory cell, a signal corresponding to one of the plurality of stable states of the RHET is transmitted to the read line via the data transfer element.

Abstract: Disclosed is a memory or display device which includes a shift register having a bubble generator, a bubble propagator, and a bubble annihilator. Front and back glass plates are provided with dielectric-covered, transparent electrodes with the plates being positioned in spaced, parallel alignment. A suitable medium having a bilaterally symmetric V-J characteristic with a current controlled negative resistance region is provided between the plates and in contact with the dielectric covering the transparent electrodes. Bubbles are moved along an asymmetric track in the propagator by modulating voltage on two electrodes on opposing sides of the asymmetric track.

Abstract: A two state memory cell includes a bipolar transistor and a tunnel diode shunted across the base-collector junction thereof. A constant operating current is established through the transistor and the tunnel diode. The voltage across the tunnel diode may thus be maintained at one of two stable levels, while the bipolar transistor is kept on regardless of the tunnel diode voltage, which determines the ZERO or ONE state of the cell. Since the transistor is not switched on and off when the memory state (corresponding to the two tunnel diode voltage levels) changes, memory cell switching speed is not degraded by transistor switching delay. Moreover, since the current in the tunnel diode is maintained constant, preferably at a value midway between the tunnel diode peak and valley currents, the noise margin of the memory cell is enhanced and the possibility of false switching reduced.

Abstract: Disclosed is an improved static memory cell comprised of first and second conductive means for carrying respective bias voltages in the cell, a third conductive means for carrying an input/output voltage signal in the cell, and a Lambda diode coupled between the first and third conductive means for there providing a negative dynamic resistance whenever the input/output voltage signal is within a predetermined range between the bias voltages on the first and second conductive means, with the improvement being a voltage dependent resistance means coupled between the second and third conductive means for there providing a negative dynamic resistance in response to at least some of the input/output voltages within said range.

Abstract: A static memory cell uses a micro-tunnel diode as load to a switching circuit involving field effect transistors. Another field effect transistor circuit is used as gate for read-address and read-out. The stationary current through the tunnel diode at logic zero is kept barely above the valley current to prevent aging. Close control of two threshold levels for the transistors in the memory cell is achieved by using the same dopant distribution in their channels in conjunction with a Schottky gate and a p-n junction gate.

Abstract: A new type of nonvolatile static read/write memory cell constructed with one MOS transistor and one MNOS transistor (4) is disclosed. The MNOS transistor (4) and the MOS transistor (3) together with a load resistor are complementary combined to offer binary states in the .LAMBDA.-shaped I-V curve for memory operation under normal power supply. Upon power failure, the MNOS transistor (4) acts as a backing-up element for nonvolatility. By impressing a control pulse on the drain of the MNOS transistor (4) the MNOS transistor changes from the depletion mode to the enhancement mode, thereby storing the last memory contents before the power failure. The stored nonvolatile memory contents can be easily retrieved. Thus a small size static random access memory is provided. The new cell is characterized by advantageous features such as small cell size, simple peripheral circuit, operation with a unipolar power supply and low standby power consumption.