Abstract: A reset device detects a rise of a supply voltage to start outputting a reset signal. The reset device includes a voltage detection circuit for detecting the supply voltage. The voltage detection circuit includes a ferroelectric capacitance element for detecting the supply voltage.

Abstract: A magneto-resistive memory that has a shared word line and sense line is disclosed. By providing the shared word line and sense line, the number of relatively large drivers required to drive the word line and sense line currents can be reduced. This reduces the peripheral overhead of the memory, and may increase the overall density and reduce the overall power of the memory.

Abstract: A memory device in which each cell includes two portions of isolated-granular material: one portion forms the channel of a single-electron transistor, and the other provides a hysteretic I-V relationship in the gate circuit of the transistor.

Abstract: In nonvolatile memory capable of erasing, writing and reading data, simplified in structure of memory cells, and enabling high-density information recording, each memory cell is composed of a thin film phase change material having two stable phases, “high-temperature phase” and “low-temperature phase” under the room temperature, and an np junction made by a p+-type region and an n+-type region, serially connected to the thin film phase change material. By applying a predetermined voltage to the upper electrode and the lower electrode to have a current flow in a memory cell (MC1l) and change the phase of the thin film phase change material, data is written. By flowing a current in the memory cell (M1l) and thereby reading the current phase of the thin film phase change material, data is read out.

Abstract: An integrated circuit includes a substrate having a surface. A first conductive path is disposed on the substrate at a first level and has a first height. A second conductive path is also disposed on the substrate at the first level and has a second height that is significantly different than the first height. Where the integrated circuit is a memory circuit, the digit lines formed from a layer can have a smaller height than other signal lines that are formed from the same layer. Thus, the capacitive coupling between the digit lines can be reduced without degrading the current carrying capability of the other signal lines.

Abstract: A superconducting cell (10) is provided which has a storage loop (12), a read-out loop (14), and a direct coupling element between the storage loop (12) and read-out loop (14). The direct coupling element is preferably an inductor (30) common to the storage loop (12) and read-out loop (14). The superconducting cell (10) is preferably a vortex-transitional superconducting memory cell. In the superconducting cell (10) a first address line (18) is directly connected to the storage loop (12) and a second address line (16) is electromagnetically coupled to the storage loop (12). The storage loop (12) has a first switchable storage element (20) to switch the superconducting cell (10) into the storing state, when currents on the first and second address lines (18), (16) have the same polarity, and into the reading state, when currents on the first and second address lines (18), (16) have different polarity.

Abstract: The instant invention is a switch, comprising: (1) a pathway of a superconductive material; and (2) a ferromagnet, where the ferromagnet is adapted for having at least a first magnetization state and a second magnetization state, where fringe fields from the ferromagnet in the first magnetization state do not exceed a predetermined magnetic field in the superconductive pathway to convert at least a portion of the superconductive pathway to the normal state; where fringe fields from the ferromagnet in the second magnetization state exceed the predetermined magnetic field in the superconductive pathway to convert at least a portion of the superconductive pathway to the normal state.

Abstract: A memory cell architecture utilizing a dual access gate and dual wordlines is disclosed. The cell is comprised of a first transistor connected between a digitline and a cellplate. The transistor is responsive to a read wordline to enable the cell to be read. An active device, such as a second transistor, is provided for modifying at least one conductive characteristic of the first transistor according to the state of a signal on the digitline. The conductive characteristic that is modified may be, for example, the threshold voltage or the transistor's channel resistance. Modification of the first transistor's characteristics is representative of writing information to the memory cell. A circuit structure for implementing the circuit architecture is also disclosed together with a method of operating a memory cell.

Abstract: An SRAM cell formed on a semiconductor substrate with low standby current is disclosed. The memory cell includes a first inverter, a second inverter cross-coupled to the first inverter to form a storage element, a first load device coupled to the first inverter, a second load device coupled to the second inverter, a first access transistor coupled to an output port of the first inverter, and a second access transistor coupled to an output port of the second inverter. In this memory cell, the first load device is placed over the second inverter with substantial overlapping therebetween, so that resistance of the first load device increases when an input of the second inverter is at a low potential, thereby decreasing a standby current of the first load device. Similarly, the resistance of the second load device increases when an input of the first inverter is at a low potential.

Abstract: A memory cell in which data is written and read from a pass gate. The memory cell has a connection to a first pass gate, connecting the memory cell to a bit line. Additionally, the memory cell has a second pass gate connecting the memory cell to a complementary bit line. The pass gates are controlled by a word line and a complementary word line.

Abstract: A memory cell comprises at least three conducting layers (20) spaced apart by insulating layers (10), a first voltage application means (24) for applying a predetermined voltage between first and third conducting layers (20a, 20c) of the at least three conducting layers, no tunneling current flowing directly between the first and third conducting layers, and a second voltage application means (5) connected to a second conducting layer (20b) of at least three conducting layers, a tunneling current being able to flow between the first and second conducting layers and between the second and third conducting layers. Within these conducting layers (20), quantum-mechanical confinement of free electrons has been made.

Abstract: In the static random access memory, load on a transistor having a gate and drain cross-connected, for example resistance or in general a pull-up element of TFT is reduced, thereby the manufacturing process is significantly simplified.A memory with a control circuit for stabilizing the operation of the memory cell during stand-by and for reading data is disclosed.

Abstract: A magnetic memory cell 10 is provided, which includes a layer 12 of superconducting material. A current path 22 is formed insulatively adjacent layer 12 of superconducting material, such that a current passed through current path 22 induces a magnetic field of a selected magnitude and selected orientation in layer 12 of superconducting material.

Abstract: In a static random access memory device where thin film transistors are used memory cell loads, first and second semiconductor layers having source regions, channel regions and drain regions of the thin film transistors partly oppose first and second conductive layers serving as gate electrodes thereof. A third conductive layer for receiving a definite potential opposes at least the channel regions of the first and second semiconductor layers.

Abstract: A static random access memory of the thin film transistor load type which is enhanced in soft error resistance without involving an increase of the area of a cell is disclosed. A conductor layer is connected to the gate electrode of a first one of a pair of thin film transistors which serve as load means of each cell and is formed as a different layer from the first thin film transistor. The conductor layer is layered on a conductor layer of the other second thin film transistor with an insulating layer interposed therebetween to form a coupling capacity between the conductor layer connected to the gate electrode of the first thin film transistor and the conductor layer of the second thin film transistor. Resistors are interposed between the gates and active layers of the first and second thin film transistors and storage nodes connected to the first and second thin film transistors.

Abstract: A superconducting magnet module comprises an alternate series of abutting and coaxially aligned first and second superconductive magnet modules. The first magnet module includes a first substrate having opposed first and second faces and a bore filled with a superconductive material extending between the first and second faces. The first face is formed of an electrically conductive material and the second face is formed of an electrically insulating material. A first spiral track of the superconductive material is formed on the first face in electrical and thermal contact with the electrically conductive material. The first spiral track is melt fused to the superconductive material in the bore. The second magnet module includes a second substrate having opposed third and fourth faces. The third face is formed of an electrically conductive material and the fourth face is formed of the electrically insulating material.

Abstract: Superconducting-semiconducting hybrid memories are disclosed. These superconducting-semiconducting hybrid memories utilize semiconductor circuits to store information, and either superconducting or semiconducting or combinations of superconducting and semiconducting circuits, with at least some superconducting circuitry used, to write and read information. The state of memory cells in the hybrid memories is determined by utilizing superconductor current sensing schemes to detect currents in the bit-line, thereby avoiding any bit-line charging delays and other problems associated with purely semiconductor memories. Additional features of the superconducting-semiconducting hybrid memories include wide margins, dense packing of memory cells, low power dissipation and fast access times. Interface curcuitry for converting superconducting signals to signals compatible with semiconductor circuits and for converting semiconductor signals to signals compatible with superconducting circuits is also disclosed.

Abstract: A novel nonvolatile memory element or cell comprising a memory means consisting of at least one superconducting ring (21, 22) and a detector means consisting of a MOSFET. The superconducting ring and the MOSFET are arranged in such a manner that a magnetic flux created by the superconducting ring (21, 22) passes through a channel zone of the MOSFET. Information is held in the superconducting ring in a form of permanent current and is detected electrically as variation in the conductivity of the channel zone of the MOSFET.

Abstract: A superconducting optically reconfigurable device (SORD) wherein predetermined and optically achieved patterns of superconducting material generate Meissner effect magnetic flux to achieve control of physical characteristics in local areas of an adjacent film of electromagnetic energy controlling material. The superconducting material magnetic flux is remembered by way of a cycle wherein selected portions of the material are elevated from the superconducting temperature range through the critical temperature T.sub.c into the non-superconducting state while in the presence of a writing magnetic field and then cooled through the critical temperature T.sub.c to permanently retain the writing magnetic flux in the area of temporary optical warming. The pattern of magnetic flux thusly achieved is coupled to one of several possible electromagnetic energy influencing or controlling materials which also have magnetic flux susceptibility.

Abstract: A magnetic memory cell including an information storage unit of a three-layer structure having two magnetic thin films and a non-magnetic thin film interposed between the two thin films, an X-direction conductor and a Y-direction conductor intersecting each other at a position of the information storage unit, and a sense conductor located at a side of the X-direction conductor opposite to the Y-direction conductor. The sense conductor is separated from the X-direction conductor and extending to overlap the X-direction conductor. The two magnetic thin films have an equal saturation magnetic flux amount and an uniaxial magnetic anisotropy in the film plane, but are different from each other in either one of a magnetic anisotropy and a coercive force. The X-direction conductor, the Y-direction conductor and the sense conductor are formed of a superconductor material, and the sense conductor has a Josephson junction (superconduction weak link) positioned above the information storage unit.

Abstract: A manufacturing method for the thin film superconductor is disclosed in which photons having energies larger than ultraviolet rays are irradiated to the thin film superconductor on or after formation of the thin film. Further, manufacturing methods for superconductive magnetic memory, Josephson device and superconductive transistor are disclosed.

Abstract: Binary memory storage devices and cryotrons utilizing superconducting crystals exhibiting an onset of superconductivity and a relatively weak flux exclusion at a temperature T1 and the onset of relatively strong flux exclusion at T2, where T1>T2>77K, are controlled by dc magnetic fields. The preferred superconducting crystals have the formula Bi.sub.2 Sr.sub.3-z Ca.sub.z Cu.sub.2 O.sub.8+w wherein z is from about 0.1 to about 0.9 and w is greater than zero but less than about 1.

Abstract: A superconductor storage device and a memory constructed by arranging a plurality of superconductor storage devices are disclosed. The superconductor storage device is comprised of a word line, a write-in line, a first loop of superconductor composed of two branch paths of superconductor connected to the word line so as to allow a current flowing in the word line to be retained in the first loop, a weakly coupling portion inserted in at least one of the two branch paths, the weakly coupling portion being subject to the influence of a magnetic field generated by the write-in line to control the retention of the current in the first loop, and a second loop of normal conductor provided so as to be magnetically coupled with the first loop, the second loop including an input path and an output path which allow the application of a voltage to the second loop and two branch paths of normal conductor which makes a loop-wise connection between the input path and the output path.

Abstract: A thin film magnetic array memory affords relatively high packing densities while avoiding the problem of magnetic domain creep through the use of thin films of superconducting material disposed on the work lines of the memory. The superconducting films shunt magnetic fields generated by currents carried within the word lines and prevent these fields from adversely affecting adjacent memory cells in the array. By constraining the magnetic fields with the use of the superconducting films, the word lines can be packed close to one another in the array structure, thereby increasing the amount of information that can be stored in a unit area of the array.

Abstract: This invention relates to a magnetic memory including a first superconductor wire, a second superconductor wire disposed in such a manner as to cross the first superconductor wire substantially orthogonally, a first magnetic film disposed at the point of intersection between the first and second superconductor wires and a second magnetic film interposed between the first magnetic film and the first or second superconductor films, wherein at least one of the uniaxial magnetic anisotropy within the plane of the films and coercive force of the first and second magnetic films is mutually different. Furthermore, a superconductor film containing a large number of microscopic Josephson junctions is disposed between the first and second magnetic films or on the other side of the superconductor wire connected to the magnetic film, and a lead wire for applying a current is connected to the superconductor film.

Abstract: A noble unit cell structure in a magnetic memory is disclosed, in which a ferromagnetic film is sandwiched between first and second wires at a cross-over area, and third and fourth wires are provided so as to sandwich the first wire. The third wire is contacted with the first wire so as to form a ring portion surrounding the ferromagnetic film and the second wire. The fourth wire is isolated from the first wire. At least the first, second and third wires are made of superconductive material. The ferromagnetic film has a uniaxial anisotropy along the second wire and its magnetization direction can be reversed by applying pulse currents to the second and fourth wires in an information writing process. In a reading process, the magnetization direction of the ferromagnetic film can be recognized by detecting either one of a superconductive state or a normal conductive state at the ring portion of the first and third wires.

Abstract: A process is disclosed of producing on a crystalline silicon substrate a barrier layer triad capable of protecting a rare earth alkaline earth copper oxide conductive coating from direct interaction with the substrate. A silica layer of at least 2000 .ANG. in thickness is deposited on the silicon substrate, and followed by deposition on the silica layer of a Group 4 heavy metal to form a layer having a thickness in the range of from 1500 to 3000 .ANG.. Heating the layers in the absence of a reactive atmosphere to permit oxygen migration from the silica layer forms a barrier layer triad consisting of a silica first triad layer located adjacent the silicon substrate, a heavy Group 4 metal oxide third triad layer remote from the silicon substrate, and a Group 4 heavy metal silicide second triad layer interposed between the first and third triad layers.

Abstract: This fast-access data storage circuit is made of a semiconductor material with a two-dimensional carrier gas between two of its layers. The material is rendered superconducting by a suitable choice of the temperature and magnetic field conditions. The circuit is formed by a plurality of memory cells, each of which is formed by two selection transistors, a semiconductor loop, ohmic contacts and a grid which is arranged on the loop and one of the contacts. The superconductivity reduces the access time. One selection controls the reading of data or the writing of a state "1" in the loop, while the other selection transistor controls the cancellation of the data and hence the writing of a state "0" by means of the grid arranged on the loop.