Abstract: A superconducting circuit includes a first component having a first connection point. The first connection point has a first width. The superconducting circuit includes a second component having a second connection point. The second connection point has a second width that is larger than the first width. The superconducting circuit includes a superconducting connector shaped to reduce current crowding. The superconducting connector electrically connects the first connection point and the second connection point. The superconducting connector includes a first taper positioned adjacent the first connection point and having a non-linear shape and a second taper positioned adjacent the second connection point.

Abstract: An active cooling structure, comprising a non-superconducting layer, a superconducting layer, and an array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions. The non-superconducting layer may comprise a plurality of non-superconducting traces. The superconducting layer may comprise a plurality of superconducting traces. The array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions may be located between the plurality of non-superconducting traces and the plurality of superconducting traces.

Abstract: A Josephson memory array and logic circuits use quasi-long-Josephson-junction interconnects to propagate signals at fast speeds and low energy expense, while permitting for memory arrays as dense fabrics of relatively simple unit cell sub-circuits, which include ? Josephson junctions, connected together by the interconnects. Each of the unit cell sub-circuits can be configured as a looped or linear arrangement. The unit cell sub-circuits and interconnects provide a fast, dense memory technology for reciprocal quantum logic (RQL), suitable for low-level caches and other memories collocated with an RQL processor.

Abstract: A method for programming a resistive random access memory including a matrix of memory cells. This method includes a programming procedure that includes applying a programming voltage ramp to the memory cells of a part at least of the matrix, the programming voltage ramp starting at a first non-zero voltage value, called start voltage, and ending at a second voltage value, called stop voltage, greater in absolute value than the first voltage value. The stop voltage is determined such that each memory cell of said at least one part of the matrix has a first probability between 1/(10N) and 1/N of having a programming voltage greater in absolute value than the stop voltage (Vstop), N being the number of memory cells in the at least one part of the matrix.

Abstract: Superconducting computing system housed in a liquid hydrogen environment and related aspects are described. An example superconducting computing system includes a housing, arranged inside a liquid hydrogen environment, where a lower pressure is maintained inside the housing than a pressure outside the housing. The superconducting computing system further includes a substrate, arranged inside the housing, having a surface, where a plurality of components attached to the surface is configured to provide at least one of a computing or a storage functionality, and the substrate further comprises a plurality of circuit traces for interconnecting at least a subset of the plurality of the components. The housing is configured such that each of the plurality of components is configured to operate at a first temperature, where the first temperature is below 4.2 Kelvin, despite the liquid hydrogen environment having a second temperature greater than 4.2 Kelvin.

Abstract: A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

Abstract: One example includes a superconducting bidirectional current driver. The current driver includes a first direction superconducting latch that is activated in response to a first activation signal and a second direction superconducting latch that is activated in response to a second activation signal. The second direction superconducting latch is activated to provide a first current path of an input current through the first direction superconducting latch and through a bidirectional current load in a first direction. The first direction superconducting latch is activated to provide a second current path of the input current through the second direction superconducting latch and through the bidirectional current load in a second direction opposite the first direction.

Abstract: One example includes a memory circuit. The memory circuit includes a memory array in which contiguous rows of the memory array are organized as a write-bypass portion that comprises a first portion of the rows and a main memory portion that includes a remaining portion of the rows. A given data word is stored in each of a row in the write-bypass portion and another row in the main memory portion during a data write operation in response to word-write signals and bit-write signals associated with each of the respective plurality of contiguous columns. The circuit also includes a control logic configured to store data associated with storage locations of the given data word in each of the row in the write-bypass portion and the other row in the main memory portion to facilitate access of the given data word during a data read operation.

Abstract: A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

Abstract: One embodiment describes a JMRAM memory cell system. The system includes a phase hysteretic magnetic Josephson junction (PHMJJ) that stores one of a first binary state and a second binary state in response to a write current provided during a data write operation and to provide a superconducting phase based on the stored digital state. The system also includes a directional write element configured to provide a directional bias current during the data write operation to provide the superconducting phase of the PHMJJ in a predetermined direction corresponding to the first binary state. The system further includes at least one Josephson junction having a critical current that is based on the superconducting phase of the PHMJJ and being configured to provide an output corresponding to the stored digital state in response to a read current that is provided during a read operation.

Abstract: A magnetic memory system includes a superconductor circuit and one or more magnetic memory elements to store data. To write data, a driver circuit in the superconductor circuit generates a magnetic signal for transmission over a superconductor link extending between the superconductor circuit and the magnetic memory element. To read data, a sensing circuit in the superconductor circuit monitors a superconductor link extending from sensing circuit to the magnetic memory element. The magnetic memory element can be a spin-transfer type magnetic memory element.

Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Abstract: A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.

Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.

Abstract: A device for storing data using nanoparticle shuttle memory having a nanotube. The nanotube has a first end and a second end. A first electrode is electrically connected to the first end of the nanotube. A second electrode is electrically connected to the second end of the nanotube. The nanotube has an enclosed nanoparticle shuttle. A switched voltage source is electrically connected to the first electrode and the second electrode, whereby a voltage may be controllably applied across the nanotube. A resistance meter is also connected to the first electrode and the second electrode, whereby the electrical resistance across the nanotube can be determined.

Abstract: A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Abstract: A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.

Abstract: In a superconducting random access memory according to this invention, drive lines such as a word line and a bit line, and a sense line for accessing a memory cell array are each divided into a plurality of blocks and an in-block signal propagation circuit having a level-logic drive circuit and sense circuit each with high load drive capability is used for signal propagation in each of the blocks. Further, for long-distance signal propagation between the blocks, superconducting passive transmission lines formed by single flux quantum (SFQ) devices and capable of high-speed operation are used. As a result, the high-speed operation as a whole is enabled. It is possible to additionally use splitters or confluence buffers and latch circuits and, further, a binary tree structure may be adopted.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Abstract: A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.

Abstract: A method for computing using a quantum system comprising a plurality of superconducting qubits is provided. Quantum system can be in any one of at least two configurations including (i) an initialization Hamiltonian H0 and (ii) a problem Hamiltonian HP. The plurality of superconducting qubits are arranged with respect to one another, with a predetermined number of couplings between respective pairs of superconducting qubits in the plurality of qubits, such that the plurality of superconducting qubits, coupled by the predetermined number of couplings, collectively define a computational problem to be solved. In the method, quantum system is initialized to the initialization Hamiltonian HO. Quantum system is then adiabatically changed until it is described by the ground state of the problem Hamiltonian HP. The quantum state of quantum system is then readout thereby solving the computational problem to be solved.

Abstract: The present invention involves a quantum computing apparatus that includes a substrate attached to which is a flux shield upon which is at least one element of circuitry. The flux shield has an aperture. Inside the aperture is a superconducting structure. The superconducting structure and the circuitry interact so that a change in a state of the superconducting structure can be detected by the circuitry. The present invention provides a method for initializing and measuring the state of a superconducting structure by adjusting and measuring the current in an element of circuitry coupled to the structure by a flux shield. The present invention provides a mechanism for coupling qubits. In embodiments of the present invention, qubits are selectively coupled by a coupling circuit that can be on a second substrate. The coupling of the qubit to the coupling circuit is enhanced by the presence of a flux shield.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Abstract: There is provided a high sensitive magnetic field sensor which has a Josephson junction section (2) using a bismuth 2212 oxide high-temperature superconductor single-crystal (1) and is operated based on a periodical variation in a Josephson vortex flow resistance and in which the variation is caused by an electric current which is passed vertical to a Josephson junction surface and, at the same time, a magnetic field which is applied approximately parallel to the Josephson junction surface. The sensor detects a corresponding magnetic field, using a curve which represents a relation between a Josephson vortex flow resistance and a magnetic field and has been obtained beforehand by measurements, and a resistance value which is measured in a state in which an electric current is passed, and can observe a little change of magnetic field in a high magnetic field area.

Abstract: The present invention provides a method and apparatus for writing a programmable conductor random access memory (PCRAM) element. After a read operation of the memory element a complement logical state from that read is written back to the memory element. In one embodiment the memory element is then again written back to its original state. In another embodiment logic circuitry keeps track of whether the original logic state or its complement are stored in the memory element so that during the next read the stored logic will be correctly read.

Abstract: A rapid SFQ one-way buffer (13, 1, 4, 5, 15, 2 & 9), is combined with a Josephson transmission line (17,3, 19, 16, 21 & 4) that is lightly loaded (RL) to provide a superconductor driver capable of producing double flux quantum output pulses. Each SFQ pulse applied to the input of the one-way buffer propagates through the Josephson transmission line to generate a double flux quantum pulse at the transmission line output.

Abstract: A magnetoquenched superconductor device or cell includes a superconductor element disposed on a substrate and a bilayer ferromagnetic film which provides uniaxial switching. The bilayer film is formed by a first ferromagnetic film disposed on and isolated from the superconductor element; and a second ferromagnetic film disposed on and separated from the first ferromagnetic film. The first and second films are magnetically coupled and have magnetizations which are switchable between a parallel relation wherein the films produce additive magnetic fringe fields that form a weak link in a portion of the superconductor element and an antiparallel relation wherein one of the films substantially absorbs the fringe field of the other film and the resultant fringe fields in the vicinity of the superconductor are such that a weak link is not formed in the superconductor. A number of two dimensional memory arrays are provided which use rows and columns of the devices.

Abstract: A superconducting circuit device of a voltage-type logic device is large in current driving capability and, accordingly, electric power consumption; however, the switching speed is not so fast, and a superconducting circuit device of a fluxoid-type logic device is small in current driving capability and, accordingly, the electric power consumption; however the switching speed is faster than that of the superconducting circuit device of the voltage-type logic device, wherein the superconducting circuit device of the voltage-type logic device and the superconducting circuit device of the fluxoid-type logic device are selectively used in a superconducting circuit such as a superconducting random access memory, a superconducting NOR circuit and a superconducting signal converting circuit so as to realize small electric power consumption and high-speed switching action.

Abstract: A superconducting cell (10) is provided which has a storage loop (12), a read-out loop (14), and a direct coupling element between the storage loop (12) and read-out loop (14). The direct coupling element is preferably an inductor (30) common to the storage loop (12) and read-out loop (14). The superconducting cell (10) is preferably a vortex-transitional superconducting memory cell. In the superconducting cell (10) a first address line (18) is directly connected to the storage loop (12) and a second address line (16) is electromagnetically coupled to the storage loop (12). The storage loop (12) has a first switchable storage element (20) to switch the superconducting cell (10) into the storing state, when currents on the first and second address lines (18), (16) have the same polarity, and into the reading state, when currents on the first and second address lines (18), (16) have different polarity.

Abstract: A prior-art electronic circuit component comprising an insulating film and a circuit conductive layer made of a superconducting metal suffers low reliability resulting from insufficient adhesion between these layers. An electronic circuit component of the invention comprises an insulating film made of a high polymer material having a dielectric constant of 2.5 or less, a base metal layer formed of copper on the insulating film, having a thickness of 0.01 to 0.3 .mu.m, and a circuit conductive layer formed of at least one of niobium and niobium nitride on the base metal layer. The electronic circuit component of the invention can accomplish an increased adhesion between the insulating film and the circuit conductive layer.

Abstract: The instant invention is a switch, comprising: (1) a pathway of a superconductive material; and (2) a ferromagnet, where the ferromagnet is adapted for having at least a first magnetization state and a second magnetization state, where fringe fields from the ferromagnet in the first magnetization state do not exceed a predetermined magnetic field in the superconductive pathway to convert at least a portion of the superconductive pathway to the normal state; where fringe fields from the ferromagnet in the second magnetization state exceed the predetermined magnetic field in the superconductive pathway to convert at least a portion of the superconductive pathway to the normal state.

Abstract: A multi-state Josephson memory in a superconductor integrated circuit includes a plurality of superconductive quantum interference device (SQUID) memory cells 2 each having a SQUID 4 characterized by a SQUID loop inductance L and a junction critical current I.sub.c, which determine the number of memory states that can be stored in the SQUID 4. A gate current I.sub.g is transmitted to the superconductive inductors 6 and 8 of the SQUID 4 to perform a read operation by crossing a designated number of current threshold boundaries corresponding to the memory state stored in the SQUID, so that the Josephson junction 12 of the SQUID 4 generates a number of pulses corresponding to the memory state. A control current I.sub.con writes data to the SQUID 4 through a control current input 16, and is preferably magnetically coupled to the SQUID 4 through superconductive inductor pairs 18, 6 and 20, 8. In a preferred embodiment, a plurality of SQUID memory cells 70a, 70b, . . .

Abstract: A memory cell comprises at least three conducting layers (20) spaced apart by insulating layers (10), a first voltage application means (24) for applying a predetermined voltage between first and third conducting layers (20a, 20c) of the at least three conducting layers, no tunneling current flowing directly between the first and third conducting layers, and a second voltage application means (5) connected to a second conducting layer (20b) of at least three conducting layers, a tunneling current being able to flow between the first and second conducting layers and between the second and third conducting layers. Within these conducting layers (20), quantum-mechanical confinement of free electrons has been made.

Abstract: An apparatus and a method for writing and reading digital information on a magnetic memory are disclosed. In the apparatus, no mechanical contact between the memory and a magnetic detection means is made because the magnetic state of a respective domain is detected by detecting change of the whole magnetic fluxes induced by entire domains formed on the memory. The writing and reading operation are carried out by scanning the domain with beam irradiation in order to destruct superconductivity or ferromagnetic characteristics of the domain resulting in trapping or releasing of magnetic fluxes. The change in magnetic flux is detected by the detection means.

Abstract: A magnetic memory cell 10 is provided, which includes a layer 12 of superconducting material. A current path 22 is formed insulatively adjacent layer 12 of superconducting material, such that a current passed through current path 22 induces a magnetic field of a selected magnitude and selected orientation in layer 12 of superconducting material.

Abstract: A hybrid superconducting-semiconducting field effect transistor-like circuit element comprised of a superconducting field effect transistor and a closely associated cryogenic semiconductor inverter for providing signal gain is described. The hybrid circuit functions nearly as an ideal pass gate in cryogenic cross-bar applications.

Abstract: A new type of superconducting memory is described. The composition of superconducting ceramic material used in the memory has been altered in order to expedite the formation of non-superconducting regions formed of grain boundaries. Non-superconducting regions may also be formed of lattice defects. Magnetic flux is trapped within the non-superconducting regions (grain boundaries or lattice defects). Information can be stored in terms of whether or not magnetic flux is trapped.

Abstract: A three-port Josephson memory cell has one input port (a data line) and two output ports (first and second sense lines). The memory cell receives a write enable pulse on a write line to store a bit of data from the data line as circulating supercurrent. The memory cell also receives a first read enable pulse on a first read line to enable assertion of the stored data onto the first sense line, and receives a second read enable pulse on a second read line to enable assertion of the stored data onto the second sense line.

Abstract: A novel nonvolatile memory element or cell comprising a memory means consisting of at least one superconducting ring (21, 22) and a detector means consisting of a MOSFET. The superconducting ring and the MOSFET are arranged in such a manner that a magnetic flux created by the superconducting ring (21, 22) passes through a channel zone of the MOSFET. Information is held in the superconducting ring in a form of permanent current and is detected electrically as variation in the conductivity of the channel zone of the MOSFET.

Abstract: A magnetic memory cell including an information storage unit of a three-layer structure having two magnetic thin films and a non-magnetic thin film interposed between the two thin films, an X-direction conductor and a Y-direction conductor intersecting each other at a position of the information storage unit, and a sense conductor located at a side of the X-direction conductor opposite to the Y-direction conductor. The sense conductor is separated from the X-direction conductor and extending to overlap the X-direction conductor. The two magnetic thin films have an equal saturation magnetic flux amount and an uniaxial magnetic anisotropy in the film plane, but are different from each other in either one of a magnetic anisotropy and a coercive force. The X-direction conductor, the Y-direction conductor and the sense conductor are formed of a superconductor material, and the sense conductor has a Josephson junction (superconduction weak link) positioned above the information storage unit.

Abstract: A superconducting memory circuit includes a superconducting loop composed of first and second superconducting lines, and bias lines are connected to connection points of the first and second lines. Inductance or critical current values of the first and second lines are different from each other. When a current is supplied to the bias lines, the current is divided and flows in the loop to maintain a magnetic flux thereof at zero. If the current is further increased, a current flowing in one superconducting line reaches the critical current value of itself prior to the other superconducting line, and a larger current flows in the other superconducting line such that a superconducting state is not destroyed. Therefore, a magnetic flux is generated in the loop. If the current of the bias lines is shut-off in this state, a persistent current flows in the loop to maintain the magnetic flux. Thus, "1" can be written.

Abstract: Binary memory storage devices and cryotrons utilizing superconducting crystals exhibiting an onset of superconductivity and a relatively weak flux exclusion at a temperature T1 and the onset of relatively strong flux exclusion at T2, where T1>T2>77K, are controlled by dc magnetic fields. The preferred superconducting crystals have the formula Bi.sub.2 Sr.sub.3-z Ca.sub.z Cu.sub.2 O.sub.8+w wherein z is from about 0.1 to about 0.9 and w is greater than zero but less than about 1.

Abstract: A superconductor storage device and a memory constructed by arranging a plurality of superconductor storage devices are disclosed. The superconductor storage device is comprised of a word line, a write-in line, a first loop of superconductor composed of two branch paths of superconductor connected to the word line so as to allow a current flowing in the word line to be retained in the first loop, a weakly coupling portion inserted in at least one of the two branch paths, the weakly coupling portion being subject to the influence of a magnetic field generated by the write-in line to control the retention of the current in the first loop, and a second loop of normal conductor provided so as to be magnetically coupled with the first loop, the second loop including an input path and an output path which allow the application of a voltage to the second loop and two branch paths of normal conductor which makes a loop-wise connection between the input path and the output path.

Abstract: A logic device includes a ceramic superconducting element having magneto-resistive characteristics, and three electrodes provided adjacent the ceramic superconducting element, and constructed in such a manner that a current is applied to one of the three electrode so that a magnetic field greater than a threshold magnetic field is normally applied to the ceramic superconducting element, and the other electrodes are used for increasing and decreasing the magnetic field. A memory device includes a superconducting loop at least one portion thereof being formed by a ceramic superconducting element having grain boundaries, and an electrode provided in approximation to said ceramic superconducting element, whereby a current flowing through a portion of said superconducting loop which is other than said ceramic superconducting element can be captured in said superconducting loop by a control of a magnetic field generated by the current flowing through said electrode.

Abstract: This invention relates to a magnetic memory including a first superconductor wire, a second superconductor wire disposed in such a manner as to cross the first superconductor wire substantially orthogonally, a first magnetic film disposed at the point of intersection between the first and second superconductor wires and a second magnetic film interposed between the first magnetic film and the first or second superconductor films, wherein at least one of the uniaxial magnetic anisotropy within the plane of the films and coercive force of the first and second magnetic films is mutually different. Furthermore, a superconductor film containing a large number of microscopic Josephson junctions is disposed between the first and second magnetic films or on the other side of the superconductor wire connected to the magnetic film, and a lead wire for applying a current is connected to the superconductor film.

Abstract: A noble unit cell structure in a magnetic memory is disclosed, in which a ferromagnetic film is sandwiched between first and second wires at a cross-over area, and third and fourth wires are provided so as to sandwich the first wire. The third wire is contacted with the first wire so as to form a ring portion surrounding the ferromagnetic film and the second wire. The fourth wire is isolated from the first wire. At least the first, second and third wires are made of superconductive material. The ferromagnetic film has a uniaxial anisotropy along the second wire and its magnetization direction can be reversed by applying pulse currents to the second and fourth wires in an information writing process. In a reading process, the magnetization direction of the ferromagnetic film can be recognized by detecting either one of a superconductive state or a normal conductive state at the ring portion of the first and third wires.

Abstract: A read only memory device includes a first electrode and a second electrode arranged in an overlapping relation with the first electrode so as to be geometrically in connection at an intersection therewith corresponding to a storage location for one type of data. At least one of the first and second electrodes is formed of a ceramics system high temperature superconductor. A prescribed one of the two electrodes which is formed of the high temperature superconductor has a high resistance region for insulating the first and second electrodes from each other at an intersection corresponding to a storage location for another type of stored data. The high resistance region is formed by irradiating an intersection with a focused ion beam.

Abstract: A combination of optical interconnect technology with superconducting matal to form a superconducting neural network array. Superconducting material in a matrix has the superconducting current decreased in one filament of the matrix by interaction of the Cooper pairs with radiation controlled by a spatial light modulator. This decrease in current results in a switch of current, in a relative sense, to another filament in the matrix. This "switching" mechanism can be used in a digital or analog fashion in a superconducting computer application.