Abstract: The field programmable read-only memory device includes a memory cell having a switching element for storing bit information. The switching element provides a switchable electrical connection between a word line and a bit line and includes a static body and a movable connecting element. The switchable electrical connection is non-volatile.

Abstract: Field effect devices having a drain controlled via a nanotube switching element. Under one embodiment, a field effect device includes a source region and a drain region of a first semiconductor type and a channel region disposed therebetween of a second semiconductor type. The source region is connected to a corresponding terminal. A gate structure is disposed over the channel region and connected to a corresponding terminal. A nanotube switching element is responsive to a first control terminal and a second control terminal and is electrically positioned in series between the drain region and a terminal corresponding to the drain region. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the drain region and its corresponding terminal.

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.

Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.

Abstract: An electromechanical switch is described, which comprises a conductive body and a plurality of carbon nanotubes being separate to each other, each of the carbon nanotubes being connected to at least one common terminal electrode with at least one of its ends, wherein in an open state of the switch each of the carbon nanotubes substantially projects along a surface of the conductive body and keeps up a gap to said surface, and wherein in a closed state of the switch at least one carbon nanotube is bend in a direction of the surface to close an electrical contact between said terminal electrode and the conductive body. The size of the gap between the respective carbon nanotube and the surface is different for each one of the plurality of carbon nanotubes.

Abstract: A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.

Abstract: An electromechanical switch is described, which comprises a conductive body and a plurality of carbon nanotubes being separate to each other, each of the carbon nanotubes being connected to at least one common terminal electrode with at least one of its ends, wherein in an open state of the switch each of the carbon nanotubes substantially projects along a surface of the conductive body and keeps up a gap to said surface, and wherein in a closed state of the switch at least one carbon nanotube is bend in a direction of the surface to close an electrical contact between said terminal electrode and the conductive body. The size of the gap between the respective carbon nanotube and the surface is different for each one of the plurality of carbon nanotubes.

Abstract: A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.

Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.

Abstract: A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.

Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.

Abstract: A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.

Abstract: Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to controllably form an electrically conductive channel between the input node and the output node. The channel at least includes said nanotube channel element. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node.

Abstract: Circuit arrays having cells with combinations of transistors and nanotube switches. Under one embodiment, cells are arranged as pairs with the nanotube switching elements of the pair being cross coupled so that the set electrode of one nanotube switching element is coupled to the release electrode of the other and the release electrode of the one nanotube switching element being coupled to the set electrode of the other. The nanotube articles are coupled to the reference line, and the source of one field effect transistor of a pair is coupled to the set electrode to one of the two nanotube switching elements and the source of the other field effect transistor of the pair is coupled to the release electrode to the one of the two nanotube switching elements.

Abstract: Embodiments discussed herein generally relate to utilizing non-volatile memory elements to continuously drive other circuitry. There are many advantages to utilizing non-volatile memory to continuously drive other circuitry. For example, back end of the line (BEOL) compatible process may be used to fabricate the non-volatile memory elements that does not affect any front end of the line (FEOL) devices. This allows for an earlier integration of non-volatile technology into the latest state-of-the-art semiconductor process nodes. This is specifically important for FPGA and CPLDs, which make use of the latest process nodes.

Abstract: Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes conductive terminals, a nanotube article and control circuitry capable of controllably form and unform an electrically conductive channel between the conductive terminals. The electronic memory is a volatile storage device capable of storing a logic state in response to electrical stimulus. In certain embodiment the electronic memory has cross-coupled first and second inverters in electrical communication with the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or can operate in a shadow memory or store mode (e.g., when power is interrupted) to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode where the state of the nanotube switching elements may be transferred to the electronic memory.

Abstract: A solid-state semiconductor device operable without loss arising from junction-to junction (e.g., source-to-drain) leakage current includes a movable MEMS switch or relay armature structure carrying at least one electrical contact corresponding to a semiconductor device junction. The switch or relay armature is movable from a first position corresponding to a first switch state to a second position corresponding to a second switch state. The semiconductor device also includes an actuation circuit configured to act on the cantilever switch, changing the switch from a first contact-conducting state to a second non-contact-conducting state by physically separating the switch's electrical contact from the semiconductor device junction, thus eliminating the conductive path for leakage current losses.

Abstract: A nanomechanical device includes a nanostructure, such as a MWNT, located between two electrodes. The device switches from an OFF state to an ON state by extension of at least one inner shell of the nanostructure relative to at least one outer shell of the nanostructure upon an application of a voltage between the electrodes. If desired, the device may also switch from the ON state to the OFF state upon an application of a gate voltage to a gate electrode located adjacent to the nanostructure.

Abstract: There are provided a memory device capable of writing and reading data at a low voltage and a method of manufacturing the same. The memory device comprises: a bit line formed in one direction; a plurality of word lines provided crosswise above the bit line, the word lines formed in parallel with a vacant space formed therebetween; a flip electrode electrically connected to the bit line, formed over one of the word lines above the bit line to pass the vacant space, and configured to be bent in one direction with respect to the plurality of word lines by electric fields induced between the plurality of word lines; and a contact part protruding from a lower end of the flip electrode concentrates charges induced by the flip electrode in response to charges applied by the word line to selectively bring the word line into contact with the flip electrode.

Abstract: Nanoelectromechanical (NEM) memory cells are provided by anchoring a conductive nanometer-scale beam (e.g., a nanotube) to a base and allowing a portion of the beam to move. A charge containment layer is provided in the vicinity of this free-moving portion. To read if a charge is stored in the charge containment layer, a charge is formed on the beam. If a charge is stored then forces between the charged beam and the charge containment layer will displace the free-moving portion of the beam. This movement may be sensed by a sense contact. Alternatively, the beam may contact a sense contact at an ambient frequency when no charge is stored. Changing the amount of charge stored may change this contact rate. The contract rate may be sensed to determine the amount of stored charge.

Abstract: Circuit arrays having cells with combinations of transistors and nanotube switches. Under one embodiment, a circuit array includes a plurality of cells arranged in an organization of words, each word having a plurality of bits. Each cell is responsive to a bit line, word line, reference line, and release line. Bit lines are arranged orthogonally relative to word lines and each word line and bit line are shared among a plurality of cells. Each cell is selectable via the activation of the bit line and word line. Each cell includes a field effect transistor coupled to a nanotube switching element. The nanotube switching element is switchable to at least two physical positions at least in part in response to electrical stimulation via the reference line and release line. Information state of the cell is non-volatilely stored via the respective physical position of the nanotube switching element.

Abstract: Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to controllably form an electrically conductive channel between the input node and the output node. The channel at least includes said nanotube channel element. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. Under another embodiment of the invention, the control electrode is arranged in relation to the nanotube channel element to form said conductive channel by causing electromechanical deflection of said nanotube channel element.

Abstract: Field effect devices having a drain controlled via a nanotube switching element. Under one embodiment, a field effect device includes a source region and a drain region of a first semiconductor type and a channel region disposed therebetween of a second semiconductor type. The source region is connected to a corresponding terminal. A gate structure is disposed over the channel region and connected to a corresponding terminal. A nanotube switching element is responsive to a first control terminal and a second control terminal and is electrically positioned in series between the drain region and a terminal corresponding to the drain region. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the drain region and its corresponding terminal.

Abstract: A random access memory cell includes first and second nanotube switching elements and an electronic memory with cross-coupled first and second inverters. Each nanotube switching element includes a nanotube channel element having at least one electrically conductive nanotube, and a set electrode and a release electrode disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between a channel electrode and an output node. Input nodes of the first and second inverters are coupled to the set electrodes and the output nodes of the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or in a shadow memory or store mode to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode to transfer the state of the nanotube switching elements to the electronic memory.

Abstract: Nanoelectromechanical (NEM) memory cells are provided by anchoring a conductive nanometer-scale beam (e.g., a nanotube) to a base and allowing a portion of the beam to move. A charge containment layer is provided in the vicinity of this free-moving portion. To read if a charge is stored in the charge containment layer, a charge is formed on the beam. If a charge is stored then forces between the charged beam and the charge containment layer will displace the free-moving portion of the beam. This movement may be sensed by a sense contact. Alternatively, the beam may contact a sense contact at an ambient frequency when no charge is stored. Changing the amount of charge stored may change this contact rate. The contract rate may be sensed to determine the amount of stored charge.

Abstract: A phase-change memory element including a phase-change material. The phase-change memory element has a plurality of memory state wherein each of the memory states has a corresponding threshold voltage. The threshold voltages may be used to determine the current memory state of the memory element. The phase-change material may include a chalcogen element.

Abstract: The memory (80) is intended to be read or modified by an electronic logical system of a pocket calculator. It comprises a plurality of bistable electromechanical flip-flop circuits (82). Each flip-flop circuit (82) comprises an input for setting at 1 (S) and an input for setting a zero (R) and an output (78). The inputs are connected individually to a multiplexor (702) controlled by a control circuit (701). The control circuit (701) is connected in two directions with a central processor via a bus (51). The control circuit (701) manages readings and writings to the memory (80).The memory is intended to memorize data which have to be retained in the calculator in a reliable and convenient way, even if the supply is cut off. The calculator is, for example, intended to make calculations concerning the application of the Ogino method, the data to be memorized being the durations of previous cycles and the date of the last period.