Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

Abstract: A electromechanical relay device (100) comprising a source electrode (102), a beam (104) mounted on the source electrode at a first end and electrically coupled to the source electrode; a first drain electrode (112) located adjacent a second end of the beam, wherein a first contact (110) on the beam is arranged to be separated from a second contact (112) on the first drain electrode when the relay device is in a first condition; a first gate electrode (106 arranged to cause the beam to deflect, to electrically couple the first contact and the second contact such that the device is in a second condition; and wherein the first and second contacts are each coated with a layer of nanocrystalline graphite.

Abstract: A temperature compensation circuit may comprise a temperature sensor to sense a temperature signal of a memristor crossbar array, a signal converter to convert the temperature signal to an electrical control signal, and a voltage compensation circuit to determine a compensation voltage based on the electrical control signal and pre-calibrated temperature data of the memristor crossbar array.

Abstract: A method for providing magnetic junctions is described. Each magnetic junction includes a free layer. A first portion of a stack for the magnetic junctions is provided. The first portion of a stack includes magnetic layer(s) for the free layer. A hard mask is provided. The hard mask covers a part of the first portion of the stack corresponding to the magnetic junctions. The hard mask includes aperture(s) exposing a second part of the first portion of the stack corresponding to spacing(s) between the magnetic junctions. The spacing(s) are not more than fifty nanometers. The second part of the first portion of the stack is etched. A remaining part of the first portion of the stack forms a first portion of each magnetic junction. This first portion of each magnetic junction includes the free layer. A second portion of the stack for the magnetic junctions is also provided.

Abstract: A magnetic memory according to an embodiment includes: a conductive nonmagnetic layer including a first terminal, a second terminal, and a region between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer disposed between the region and the first magnetic layer; and a nonmagnetic intermediate layer disposed between the first magnetic layer and the second magnetic layer; a transistor including a third terminal, a fourth terminal, and a control terminal, the third terminal being electrically connected to the first terminal; a first wiring electrically connected to the first magnetic layer and the fourth terminal; a second wiring electrically connected to the control terminal; and a third wiring electrically connected to the second terminal.

Abstract: A three-dimensional flash memory system is disclosed.

Abstract: Techniques and examples pertaining to variation calibration for envelope tracking on chip are described. Envelope tracking (ET) statistics among multiple wireless-capable mobile devices (e.g., smartphones) may be collected in laboratory. Optimal ET parameters may be determined based on ET statistics. An ET setting file may be generated for ET factory calibration. In production lines, the ET setting file may be loaded into each mobile device for ET factory calibration.

Abstract: A storage element is provided. The storage element includes a memory layer having a first magnetization state of a first material; a fixed magnetization layer having a second magnetization state of a second material; an intermediate layer including a nonmagnetic material and provided between the memory layer and the fixed magnetization layer; wherein the first material includes Co—Fe—B alloy, and at least one of a non-magnetic metal and an oxide.

Abstract: The invention relates, inter alia, to a memory cell (10) comprising at least one binary memory area for storing bit information. According to the invention it is provided that the memory area (SB) can optionally store holes or electrons and allows a recombination of holes and electrons, the charge carrier type of the charge carriers stored in the memory area defines the bit information of the memory area, and a charge carrier injection device (PN) is present, by means of which optionally holes or electrons can be injected into the memory area (SB) and the bit information can thus be changed.

Abstract: In one embodiment of the invention, there is provided a method for manufacturing a magnetic memory device, comprising: depositing a carbon layer comprising amorphous carbon on a substrate; annealing the carbon layer to activate dopants contained therein; and selectively etching portions of the carbon layer to forms lines of spaced apart carbon conductors.

Abstract: A storage element is provided. The storage element includes a memory layer having a first magnetization state of a first material; a fixed magnetization layer having a second magnetization state of a second material; an intermediate layer including a nonmagnetic material and provided between the memory layer and the fixed magnetization layer; wherein the first material includes Co—Fe—B alloy, and at least one of a non-magnetic metal and an oxide.

Abstract: The present invention relates to a magnetic tunnel junction device and a manufacturing method thereof. The magnetic tunnel junction device includes: i) a first magnetic layer including a compound having a chemical formula of (A100-xBx)100-yCy; ii) an insulating layer deposited on the first magnetic layer; and iii) a second magnetic layer deposited on the insulating layer and including a compound having a chemical formula of (A100-xBx)100-yCy. The first and second magnetic layers have perpendicular magnetic anisotropy, A and B are respectively metal elements, and C is at least one amorphizing element selected from a group consisting of boron (B), carbon (C), tantalum (Ta), and hafnium (Hf).

Abstract: There is disclosed a memory element including a layered structure including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer; and an insulating layer provided between the memory layer. An electron that is spin-polarized is injected in a lamination direction of a layered structure, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, in regard to the insulating layer that comes into contact with the memory layer, and the other side layer with which the memory layer comes into contact at a side opposite to the insulating layer, at least an interface that comes into contact with the memory layer is formed of an oxide film, and the memory layer includes at least one of non-magnetic metal and oxide in addition to a Co—Fe—B magnetic layer.

Abstract: In one embodiment, a non-volatile memory bitcell includes a program electrode, an erase electrode, a cantilever electrode connected to a bi-stable cantilever positioned between the program electrode and the erase electrode, and switching means connected to the program electrode arranged to apply a voltage potential onto the program electrode, or to detect or to prevent the flow of current from the cantilever to the program electrode. The switching means may comprise a switch having a first node, a second node, and a control node, wherein voltage is applied to the control node to activate the switch to provide a connection between the first node and the second node. The switching means may comprise a pass-gate. The switching means may comprise an NMOS transistor. The switching means may comprise a PMOS transistor. The switching means may comprise a MEMS switch.

Abstract: A memory mat (101) includes a main body portion (200) that includes a first capacitor (203A), a linear conductive film (204) that is formed between the main body portion (200) and a peripheral circuit (104), and a second capacitor (203B) that is formed to be in contact with the conductive film (204) at a bottom of the second capacitor (203B). The first capacitor (203A) is in contact with a contact layer (202) at a bottom of the first capacitor (203A).

Abstract: A nonvolatile memory element includes a first and a second electrode layers, and a variable resistance layer provided between the first and the second electrode layers and having a resistance value reversibly changing according to application of an electrical pulse, wherein the variable resistance layer includes a first variable resistance layer contacting the first electrode layer and comprising an oxygen-deficient first metal oxide, and a second variable resistance layer contacting the first variable resistance layer and comprising a second metal oxide having a smaller oxygen deficiency than the first metal oxide, and including host layers and an inserted layer between each of adjacent pairs of the host layers, wherein the second metal oxide of the inserted layer has a larger oxygen deficiency than the second metal oxide of the host layer, and the first metal oxide has a larger oxygen deficiency than the second metal oxide of the host layer.

Abstract: Various embodiments comprise apparatuses having at least two resistance change memory (RCM) cells. In one embodiment, an apparatus includes at least two electrical contacts coupled to each of the RCM cells. A memory cell material is disposed between pairs of each of the electrical contacts coupled to each of the RCM cells. The memory cell material is capable of forming a conductive pathway between the electrical contacts with at least a portion of the memory cell material arranged to cross-couple a conductive pathway between select ones of the at least two electrical contacts electrically coupled to each of the at least two RCM cells. Additional apparatuses and methods are described.

Abstract: A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).

Abstract: Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools.

Abstract: The field programmable read-only memory device includes a memory cell having a switching element for storing bit information. The switching element provides a switchable electrical connection between a word line and a bit line and includes a static body and a movable connecting element. The switchable electrical connection is non-volatile.

Abstract: The present invention discloses a mask-ROM with reserved space (mask-ROMRS). For small content revision, the present invention salvages the original data-mask by writing the data-pattern of new content into a reserved mask-region which originally has no data-pattern.

Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits.

Abstract: A memory chip and methods of fabricating a memory device with different programming performance and retention characteristics on a single wafer. One method includes depositing a first bounded area of phase change material on the wafer and depositing a second bounded area of phase change material on the wafer. The method includes modifying the chemical composition of a switching volume of the first bounded area of phase change material. The method includes forming a first memory cell in the first bounded area of phase change material with a modified switching volume of phase change material and a second memory cell in the second bounded area of phase change material with an unmodified switching volume of phase change material such that the first memory cell has a first retention property and the second memory cell has a second retention property. The first retention property is different from the second retention property.

Abstract: An apparatus has a support and a plurality of bendable and conductive microstructures extending from the support. Two adjacent microstructures of the plurality of microstructures define a detectable first state if they are not bent such that end portions thereof, which are distal with respect to the support, do not touch each other, and the two adjacent microstructures of the plurality of microstructures define a detectable second state if they are bent such that the end portions thereof, which are distal with respect to the support, touch each other and are fixed to each other.

Abstract: Field effect devices having a drain controlled via a nanotube switching element. Under one embodiment, a field effect device includes a source region and a drain region of a first semiconductor type and a channel region disposed therebetween of a second semiconductor type. The source region is connected to a corresponding terminal. A gate structure is disposed over the channel region and connected to a corresponding terminal. A nanotube switching element is responsive to a first control terminal and a second control terminal and is electrically positioned in series between the drain region and a terminal corresponding to the drain region. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the drain region and its corresponding terminal.

Abstract: A nanoelectromechanical device is provided. The nanoelectromechanical device includes a nanotube, a first contact, and a first actuator. The nanotube includes a first end, the first end supported by a first structure, a second end opposite the first end, and a first portion. The first actuator is configured to apply a first force to the nanotube, the first force causing the nanotube to buckle such that the first portion couples to the first contact.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.

Abstract: A phase change memory cell has more than one memory region each being a narrowed region of phase change memory material extending between first and second electrodes. Each of the plurality of memory regions can be programmed to be in a low resistance state or a high resistance state by applying suitable programming conditions of current and/or voltage. The resistances of the high resistance states and the programming conditions to convert the high resistance states to the low resistance state are different in each of the plurality of memory regions.

Abstract: An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs).

Abstract: Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.

Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type, which are disposed to be separated from each other in the first semiconductor layer, a first electrode electrically connected to the second semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, through application of a voltage equal to or higher than a predetermined threshold between the first electrode and the second electrode.

Abstract: Systems and methods for operating a nanometer-scale cantilever beam with a gate electrode. An example system includes a drive circuit coupled to the gate electrode where a drive signal from the circuit may cause the beam to oscillate at or near the beam's resonance frequency. The drive signal includes an AC component, and may include a DC component as well. An alternative example system includes a nanometer-scale cantilever beam, where the beam oscillates to contact a plurality of drain regions.

Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.

Abstract: Various embodiments comprise apparatuses having at least two resistance change memory (RCM) cells. In one embodiment, an apparatus includes at least two electrical contacts coupled to each of the RCM cells. A memory cell material is disposed between pairs of each of the electrical contacts coupled to each of the RCM cells. The memory cell material is capable of forming a conductive pathway between the electrical contacts with at least a portion of the memory cell material arranged to cross-couple a conductive pathway between select ones of the at least two electrical contacts electrically coupled to each of the at least two RCM cells. Additional apparatuses and methods are described.

Abstract: An integrated circuit can include at least one programmable metallization cell (PMC) comprising an ion conducting material and a metal dissolvable in the ion conducting material, selectively connected to a shunt node; and a biasing circuit comprising a current source coupled to the shunt node configurable to provide a first current in a first type operation, and a voltage regulator coupled to the shunt node configured to regulate a potential at the shunt node; wherein in the first type operation, the voltage regulator shunts current with respect to the shunt node in a same direction as a current flow of the at least one PMC.

Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.

Abstract: An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs).

Abstract: Devices and components that can interact with or modify propagation of electromagnetic waves are provided. The design, fabrication and structures of the devices exploit the properties of reactive composite materials (RCM) and reaction products thereof.

Abstract: A nonvolatile memory element which can be initialized at low voltage includes a variable resistance layer (116) located between a lower electrode (105) and an upper electrode (107) and having a resistance value that reversibly changes based on electrical signals applied between these electrodes. The variable resistance layer (116) includes at least two layers: a first variable resistance layer (1161) including a first transition metal oxide (116b); and a second variable resistance layer (1162) including a second transition metal oxide (116a) and a third transition metal oxide (116c). The second transition metal oxide (116a) has an oxygen deficiency higher than either oxygen deficiency of the first transition metal oxide (116b) or the third transition metal oxide (116c), and the second transition metal oxide (116a) and the third transition metal oxide (116c) are in contact with the first variable resistance layer (1161).

Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.

Abstract: A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.

Abstract: Nanoelectromechanical systems are disclosed that utilize vertically grown or placed nanometer-scale beams. The beams may be configured and arranged for use in a variety of applications, such as batteries, generators, transistors, switching assemblies, and sensors. In some generator applications, nanometer-scale beams may be fixed to a base and grown to a desired height. The beams may produce an electric potential as the beams vibrate, and may provide the electric potential to an electrical contact located at a suitable height above the base. In other embodiments, vertical beams may be grown or placed on side-by-side traces, and an electrical connection may be formed between the side-by-side traces when beams on separate traces vibrate and contact one another.

Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.

Abstract: An electromechanical switch is described, which comprises a conductive body and a plurality of carbon nanotubes being separate to each other, each of the carbon nanotubes being connected to at least one common terminal electrode with at least one of its ends, wherein in an open state of the switch each of the carbon nanotubes substantially projects along a surface of the conductive body and keeps up a gap to said surface, and wherein in a closed state of the switch at least one carbon nanotube is bend in a direction of the surface to close an electrical contact between said terminal electrode and the conductive body. The size of the gap between the respective carbon nanotube and the surface is different for each one of the plurality of carbon nanotubes.

Abstract: Systems and methods for operating a nanometer-scale cantilever beam with a gate electrode. An example system includes a drive circuit coupled to the gate electrode where a drive signal from the circuit may cause the beam to oscillate at or near the beam's resonance frequency. The drive signal includes an AC component, and may include a DC component as well. An alternative example system includes a nanometer-scale cantilever beam, where the beam oscillates to contact a plurality of drain regions.

Abstract: An integrated circuit may include: access circuits that couple first electrodes of a plurality of programmable metallization cells (PMC) to access paths in parallel, each PMC comprising a solid ion conducting material formed between the first electrode and a second electrode; a plurality of write circuits, each coupled to a different access path, and each coupling the corresponding access path to a first voltage in response to input write data having a first value and to a second voltage in response to the input write data having a second value; and a node setting circuit that maintains second electrodes of the PMCs at a substantially constant third voltage while write circuits couple the access paths to the first or second voltages.

Abstract: A computer motherboard includes a printed circuit board which includes a central processing unit (CPU) socket and a group of memory slots. The group of memory slots includes an in-line type memory slot and a surface mounted device (SMD) type memory slot. The in-line type memory slot includes a number of plated through holes. The SMD type memory slot is set between the in-line type memory slot and the CPU socket. The through holes of the in-line type memory slot are connected to the CPU socket through traces, pads of the SMD type memory slot are connected to corresponding through holes of the in-line type memory slot having the same pin definition.

Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.

Abstract: A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

Abstract: A non-volatile logic circuit includes a control electrode, a ferroelectric layer disposed on the control electrode, a semiconductor layer disposed on the ferroelectric layer, a power electrode and an output electrode disposed on the semiconductor layer, and first to fourth input electrodes disposed on the semiconductor layer. The first and second input electrodes receive first and second inputs, respectively. The third and fourth input electrodes receive inversion signals of the second and first input signal, respectively. A resistance value of the semiconductor layer between the power electrode and the output electrode varies according to the first input signal and the second input signal so that an exclusive-OR signal of the first and second input signals is output from the output electrode.