Isotropic Patents (Class 365/172)
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Patent number: 9739481Abstract: A venturi nozzle for a gas combustor includes an orificed gas nozzle, a venturi tube and one or more support members. The orificed gas nozzle has a longitudinal axis, an inlet and an outlet. The venturi tube is aligned with the longitudinal axis and has an entrance proximate to the outlet of the orificed gas nozzle and an exit. The support member(s) are attached between the orificed gas nozzle and the venturi tube to create a gap between the venturi tube and the orificed gas nozzle. In some embodiments, two or more venturi nozzles can be combined together in various configurations into a nozzle assembly or multi-nozzle gas combustor and attached, mounted or disposed within a stack, chimney or vented enclosure. The wall(s) of the stack, chimney or vented enclosure may include one or more openings, cut outs or vents to provide primary and secondary air to the venturi nozzles.Type: GrantFiled: July 15, 2016Date of Patent: August 22, 2017Assignee: FLAME COMMANDER CORP.Inventors: Jerry M. Lang, David W. Scott, Bradley C. Smith
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Patent number: 9040178Abstract: A TMR sensor that includes a free layer having at least one B-containing (BC) layer made of CoFeB, CoFeBM, CoB, COBM, or CoBLM, and a plurality of non-B containing (NBC) layers made of CoFe, CoFeM, or CoFeLM is disclosed where L and M are one of Ni, Ta, Ti, W, Zr, Hf, Tb, or Nb. One embodiment is represented by (NBC/BC)n where n?2. A second embodiment is represented by (NBC/BC)n/NBC where n?1. In every embodiment, a NBC layer contacts the tunnel barrier and NBC layers each with a thickness from 2 to 8 Angstroms are formed in alternating fashion with one or more BC layers each 10 to 80 Angstroms thick. Total free layer thickness is <100 Angstroms. The free layer configuration described herein enables a significant noise reduction (SNR enhancement) while realizing a high TMR ratio, low magnetostriction, low RA, and low Hc values.Type: GrantFiled: September 22, 2008Date of Patent: May 26, 2015Assignee: Headway Technologies, Inc.Inventors: Tong Zhao, Hui-Chuan Wang, Yu-Chen Zhou, Min Li, Kunliang Zhang
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Patent number: 9036308Abstract: Various embodiments may be generally directed to a magnetic sensor constructed with a decoupling layer that has a predetermined first morphology. A magnetic free layer can be deposited contactingly adjacent to the decoupling layer with the magnetic free layer configured to have at least a first sub-layer having a predetermined second morphology.Type: GrantFiled: September 21, 2011Date of Patent: May 19, 2015Assignee: Seagate Technology LLCInventors: Mark William Covington, Mark Thomas Kief, Wonjoon Jung
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Spin-transfer torque magnetic random access memory (STTMRAM) with perpendicular laminated free layer
Patent number: 9025371Abstract: A perpendicular spin-transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.Type: GrantFiled: January 30, 2015Date of Patent: May 5, 2015Assignee: Avalanche Technology, Inc.Inventors: Yiming Huai, Rajiv Yadav Ranjan, Roger K. Malmhall -
Patent number: 9017831Abstract: A thin-film magnetic oscillation element includes a pinned magnetic layer, a free magnetic layer, a nonmagnetic spacer layer provided between the pinned magnetic layer and the free magnetic layer, and a pair of electrodes, in which the easy axis of magnetization of the pinned magnetic layer lies in an in-plane direction of the plane of the pinned magnetic layer, and the easy axis of magnetization of the free magnetic layer lies in a direction normal to the plane of the free magnetic layer. Preferably, the relationship between the saturation magnetization Ms and the magnetic anisotropy field Ha of the free magnetic layer satisfies 1.257 Ms<Ha<12.57 Ms. More preferably, the free magnetic layer is composed of an alloy or a stacked film containing at least one element selected from Co, Ni, Fe, and B.Type: GrantFiled: February 27, 2013Date of Patent: April 28, 2015Assignee: TDK CorporationInventors: Katsuyuki Nakada, Takahiro Suwa, Kuniyasu Ito, Yuji Kakinuma, Masato Takahashi
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Patent number: 9017832Abstract: Various embodiments may be generally directed to a magnetic element capable of optimized magnetoresistive data reading. Such a magnetic element may be configured at least with a magnetoresistive stack that has an electrode lamination having at least a transition metal layer disposed between a magnetically free layer of the magnetoresistive stack and an electrode layer of the electrode lamination.Type: GrantFiled: January 31, 2013Date of Patent: April 28, 2015Assignee: Seagate Technology LLCInventors: Eric Walter Singleton, Liwen Tan, Jae-Young Yi
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Spin-transfer torque magnetic random access memory (STTMRAM) with perpendicular laminated free layer
Patent number: 8982616Abstract: A perpendicular spin transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.Type: GrantFiled: November 26, 2012Date of Patent: March 17, 2015Assignee: Avalanche Technology, Inc.Inventors: Rajiv Yadav Ranjan, Roger Klas Malmhall, Yiming Huai -
Patent number: 8975091Abstract: The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention.Type: GrantFiled: September 9, 2014Date of Patent: March 10, 2015Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Min-Hwa Chi, Mieno Fumitake
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Patent number: 8947921Abstract: The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line.Type: GrantFiled: January 14, 2014Date of Patent: February 3, 2015Assignee: Crocus Technology SAInventor: Bertrand Cambou
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Patent number: 8907436Abstract: Provided are magnetic memory devices with a perpendicular magnetic tunnel junction. The device includes a magnetic tunnel junction including a free layer structure, a pinned layer structure, and a tunnel barrier therebetween. The pinned layer structure may include a first magnetic layer having an intrinsic perpendicular magnetization property, a second magnetic layer having an intrinsic in-plane magnetization property, and an exchange coupling layer interposed between the first and second magnetic layers. The exchange coupling layer may have a thickness maximizing an antiferromagnetic exchange coupling between the first and second magnetic layers, and the second magnetic layer may exhibit a perpendicular magnetization direction, due at least in part to the antiferromagnetic exchange coupling with the first magnetic layer.Type: GrantFiled: July 2, 2013Date of Patent: December 9, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: SeChung Oh, Ki Woong Kim, Younghyun Kim, Whankyun Kim, Sang Hwan Park
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Patent number: 8895323Abstract: A method for forming MRAM (magnetoresistive random access memory) devices is provided. A bottom electrode assembly is formed. A magnetic junction assembly is formed, comprising, depositing a magnetic junction assembly layer over the bottom electrode assembly, forming a patterned mask over the magnetic junction assembly layer, etching the magnetic junction assembly layer to form the magnetic junction assembly with gaps, gap filling the magnetic junction assembly, and planarizing the magnetic junction assembly. A top electrode assembly is formed.Type: GrantFiled: December 14, 2012Date of Patent: November 25, 2014Assignee: Lam Research CorporationInventor: Joydeep Guha
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Patent number: 8860155Abstract: The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention.Type: GrantFiled: March 22, 2012Date of Patent: October 14, 2014Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Chi Min-Hwa, Mieno Fumitake
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Patent number: 8836058Abstract: A magnetic device includes a first electrode portion, a free layer portion arranged on the first electrode portion, the free layer portion including a magnetic insulating material, a reference layer portion contacting the free layer portion, the reference layer portion including a magnetic metallic layer, and a second electrode portion arranged on the reference layer portion.Type: GrantFiled: November 29, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Marcin J. Gajek, Daniel C. Worledge
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Patent number: 8836060Abstract: The present disclosure provides a spin device including: a graphene; a first ferromagnetic electrode and a second electrode that are in electrical contact with and sandwich the graphene; a third ferromagnetic electrode and a fourth electrode that sandwich the graphene at a position apart from the first and second electrodes in electrical contact with the graphene; a current applying portion that applies an electric current between the first ferromagnetic electrode and the second electrode; and a voltage-signal detecting portion that detects spin accumulation information as a voltage signal via the third ferromagnetic electrode and the fourth electrode. The spin accumulation information is generated, by application of the electric current, in a part of the graphene that is sandwiched between the third and fourth electrodes. The first and third ferromagnetic electrodes are disposed on the same surface of the graphene, and the second and fourth electrodes are non-magnetic or ferromagnetic electrodes.Type: GrantFiled: February 28, 2013Date of Patent: September 16, 2014Assignee: Panasonic CorporationInventors: Akihiro Odagawa, Nozomu Matsukawa
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Patent number: 8823119Abstract: A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure.Type: GrantFiled: November 21, 2012Date of Patent: September 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-joon Kim, Hyung-joon Kwon
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Patent number: 8791535Abstract: A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90?atan(?)) degrees.Type: GrantFiled: August 19, 2013Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Yoshiaki Asao
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Patent number: 8765490Abstract: The present disclosure describes a semiconductor MRAM device and a manufacturing method. The device reduces magnetic field induction “interference” (disturbance) phenomenon between adjacent magnetic tunnel junctions when data is written and read. This semiconductor MRAM device comprises a magnetic tunnel junction unit and a magnetic shielding material layer covering the sidewalls of the magnetic tunnel junction unit. The method for manufacturing a semiconductor device comprises: forming a magnetic tunnel junction unit, depositing an isolation dielectric layer to cover the top and the sidewall of the magnetic tunnel junction unit, and depositing a magnetic shielding material layer on the isolation dielectric layer.Type: GrantFiled: October 17, 2012Date of Patent: July 1, 2014Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Gavin Zeng
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Patent number: 8730716Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.Type: GrantFiled: June 28, 2013Date of Patent: May 20, 2014Assignee: Avalanche Technology, Inc.Inventors: Parviz Keshtbod, Ebrahim Abedifard
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Patent number: 8710604Abstract: In accordance with an embodiment, a magnetoresistive element includes a lower electrode, a first magnetic layer on the lower electrode, a first diffusion prevention layer on the first magnetic layer, a first interfacial magnetic layer on the first metal layer, a nonmagnetic layer on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second diffusion prevention layer on the second interfacial magnetic layer, a second magnetic layer on the second diffusion prevention layer, and an upper electrode layer on the second magnetic layer. The ratio of a crystal-oriented part to the other part in the second interfacial magnetic layer is higher than the ratio of a crystal-oriented part to the other part in the first interfacial magnetic layer.Type: GrantFiled: March 20, 2012Date of Patent: April 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno, Tadashi Kai
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Patent number: 8709617Abstract: In accordance with one aspect of the invention, a magnetic memory element records information in a spin valve structure having a free layer, a pinning layer, and a nonmagnetic layer sandwiched therebetween. The magnetic memory element further has, on the free layer, a separate nonmagnetic layer and a magnetic change layer having magnetic characteristics which change according to temperature. Multiple cutouts, including one cutout with a different shape, are provided in a peripheral portion of the spin valve structure. A method of driving the magnetic memory element is characterized in that information is recorded by applying unipolar electric pulses.Type: GrantFiled: September 5, 2008Date of Patent: April 29, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Yasushi Ogimoto, Haruo Kawakami
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Patent number: 8686524Abstract: A magnetic stack having a ferromagnetic free layer, a metal oxide layer that is antiferromagnetic at a first temperature and non-magnetic at a second temperature higher than the first temperature, a ferromagnetic pinned reference layer, and a non-magnetic spacer layer between the free layer and the reference layer. During a writing process, the metal oxide layer is non-magnetic. For magnetic memory cells, such as magnetic tunnel junction cells, the metal oxide layer provides reduced switching currents.Type: GrantFiled: June 8, 2012Date of Patent: April 1, 2014Assignee: Seagate Technology LLCInventors: Xiaohua Lou, Yuankai Zheng, Wenzhong Zhu, Wei Tian, Zheng Gao
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Patent number: 8679653Abstract: A spin-valve element has a pair of ferromagnetic layers having mutually different coercive forces, sandwiching an insulating layer or a nonmagnetic layer therebetween. The in-plane shape of the spin-valve element is substantially circular in shape but is provided, in the peripheral portion, with a plurality of cutouts NS, NW, NE, NN. Preferably, the shape of at least one cutout be made different from that of others. Moreover, a storage device that employs such a spin-valve element is provided.Type: GrantFiled: September 5, 2008Date of Patent: March 25, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Haruo Kawakami, Yasushi Ogimoto
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Patent number: 8634234Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.Type: GrantFiled: June 28, 2013Date of Patent: January 21, 2014Assignee: Avalanche Technology, Inc.Inventors: Parviz Keshtbod, Ebrahim Abedifard
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Patent number: 8630112Abstract: The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line.Type: GrantFiled: October 26, 2011Date of Patent: January 14, 2014Assignee: Crocus Technology SAInventor: Bertrand Cambou
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Patent number: 8611147Abstract: A spin-torque transfer memory random access memory (STTMRAM) element, employed in a STTMRAM array, receives electric current for storage of digital information, the STTMRAM element has a magnetic tunnel junction (MTJ). The MTJ includes an anti-ferromagnetic (AF) layer, a fixed layer having a magnetization that is substantially fixed in one direction and that comprises a first magnetic layer, an AF coupling layer and a second magnetic layer, a barrier layer formed upon the fixed layer, and a free layer. The free layer is synthetic and has a high-polarization magnetic layer, a low-crystallization magnetic layer, a non-magnetic separation layer, and a magnetic layer, wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer.Type: GrantFiled: March 22, 2013Date of Patent: December 17, 2013Assignee: Avalanche Technology, Inc.Inventors: Rajiv Yadav Ranjan, Roger Klas Malmhall, Yiming Huai
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Patent number: 8609262Abstract: A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation and containing an oxygen surfactant layer to form a more uniform MgO layer and lower breakdown distribution percent. A CoFeB/NCC/CoFeB composite free layer with a middle nanocurrent channel layer minimizes Jc0 while enabling thermal stability, write voltage, read voltage, and Hc values that satisfy 64 Mb design requirements. The NCC layer has RM grains in an insulator matrix where R is Co, Fe, or Ni, and M is a metal such as Si or Al. NCC thickness is maintained around the minimum RM grain size to avoid RM granules not having sufficient diameter to bridge the distance between upper and lower CoFeB layers. A second NCC layer and third CoFeB layer may be included in the free layer or a second NCC layer may be inserted below the Ru capping layer.Type: GrantFiled: July 17, 2009Date of Patent: December 17, 2013Assignee: MagIC Technologies, Inc.Inventors: Cheng T. Horng, Ru-Ying Tong, Guangli Liu, Robert Beach, Witold Kula, Tai Min
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Patent number: 8592929Abstract: A spin transfer torque magnetic random access memory (STT-MRAM) device includes magnetic tunnel junctions (MTJs) with reduced switching current asymmetry. At least one switching asymmetry balance layer (SABL) near the free layer of the MTJ reduces a first switching current Ic(p-ap) causing the value of the first switching current to be nearly equal to the value of a second switching current Ic(ap-p) without increasing the average switching current of the device. The SABL may be a non-magnetic switching asymmetry balance layer (NM-SABL) and/or a magnetic switching asymmetry balance layer (M-SABL).Type: GrantFiled: January 27, 2012Date of Patent: November 26, 2013Assignee: QUALCOMM IncorporatedInventors: Wei-Chuan Chen, Kangho Lee, Xiaochun Zhu, Seung H. Kang
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Patent number: 8592930Abstract: A magnetic memory element includes: a first magnetization free layer; a non-magnetic layer; a reference layer; a first magnetization fixed layer group; and a first blocking layer. The first magnetization free layer is composed of ferromagnetic material with perpendicular magnetic anisotropy and includes a first magnetization fixed region, a second magnetization fixed region and a magnetization free region. The non-magnetic layer is provided near the first magnetization free layer. The reference layer is composed of ferromagnetic material and provided on the non-magnetic layer. The first magnetization fixed layer group is provided near the first magnetization fixed region. The first blocking layer is provided being sandwiched between the first magnetization fixed layer group and the first magnetization fixed region or in the first magnetization fixed layer group.Type: GrantFiled: October 21, 2010Date of Patent: November 26, 2013Assignee: NEC CorporationInventors: Shunsuke Fukami, Tetsuhiro Suzuki, Kiyokazu Nagahara, Norikazu Ohshima, Nobuyuki Ishiwata
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Patent number: 8551626Abstract: A magnetoresistive device having a high giant magnetoresistance (GMR) value and a moderate low resistance area product (RA) includes a first magnetic layer, a second magnetic layer, and a current confined path (CCP) spacer layer positioned between the first magnetic layer and the second magnetic layer. The spacer layer includes copper current confined paths extending between the first magnetic layer and the second magnetic layer in a matrix of magnesium oxide. The spacer layer is formed by a mixture copper and magnesium oxide, which is heattreated to form the copper current confined paths within the magnesium oxide matrix.Type: GrantFiled: June 25, 2009Date of Patent: October 8, 2013Assignee: Seagate Technology LLCInventors: Qing He, Yonghua Chen, Juren Ding
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Patent number: 8546897Abstract: A magnetic memory element includes a memory layer, a reference layer, and a spin-injection layer provided between the memory layer and the reference layer. The reference layer has a structure in which at least two CoPt layers containing 20 atomic % or more and 50 atomic % or less of Pt and having a thickness of 1 nm or more and 5 nm or less are stacked with a Ru layer provided therebetween. The thickness of the Ru layer is 0.45±0.05 nm or 0.9±0.1 nm. In addition, the axis of 3-fold crystal symmetry of the CoPt layers is oriented perpendicularly to the film surface. The reference layer includes a high spin polarization layer of 1.5 nm or less containing Co or Fe as a main component at an interface with the spin-injection layer.Type: GrantFiled: July 29, 2011Date of Patent: October 1, 2013Assignee: Sony CorporationInventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
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Patent number: 8542524Abstract: A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.Type: GrantFiled: December 21, 2010Date of Patent: September 24, 2013Assignee: Avalanche Technology, Inc.Inventors: Parviz Keshtbod, Roger Klas Malmhall, Rajiv Yadav Ranjan
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Patent number: 8542526Abstract: A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.Type: GrantFiled: February 8, 2013Date of Patent: September 24, 2013Assignee: Avalanche Technology, Inc.Inventors: Parviz Keshtbod, Roger Klas Malmhall, Rajiv Yadav Ranjan
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Patent number: 8536668Abstract: A magnetic layer that includes a seed layer comprising at least tantalum and a free magnetic layer comprising at least iron. The free magnetic layer is grown on top of the seed layer and the free magnetic layer is perpendicularly magnetized. The magnetic layer may be included in a magnetic tunnel junction (MTJ) stack.Type: GrantFiled: August 9, 2012Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventor: Daniel C. Worledge
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Patent number: 8507113Abstract: The present invention is directed to align crystal c-axes in magnetic layers near two opposed junction wall surfaces of a magnetoresistive element so as to be almost perpendicular to the junction wall surfaces. A magnetic sensor stack body has, on sides of opposed junction wall surfaces of a magnetoresistive element, field regions for applying a bias magnetic field to the element. The field region has first and second magnetic layers having magnetic particles having crystal c-axes, the first magnetic layer is disposed adjacent to the junction wall surface in the field region, the crystal c-axes in the first magnetic layer are aligned and oriented along an ABS in a film plane, the second magnetic layer is disposed adjacent to the first magnetic layer in the field region, and the crystal c-axis directions in the second magnetic layer are distributed at random in a plane.Type: GrantFiled: May 28, 2010Date of Patent: August 13, 2013Assignee: Canon Anelva CorporationInventors: Einstein Noel Abarra, Tetsuya Endo
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Patent number: 8497139Abstract: A magnetic memory device including a memory layer having a vertical magnetization on the layer surface, of which the direction of magnetization is changed according to information; and a reference layer provided against the memory layer, and being a basis of information while having a vertical magnetization on the layer surface, wherein the memory device memorizes the information by reversing the magnetization of the memory layer by a spin torque generated when a current flows between layers made from the memory layer, the nonmagnetization layer and the reference layer, and a coercive force of the memory layer at a memorization temperature is 0.7 times or less than a coercive force at room temperature, and a heat conductivity of a center portion of an electrode formed on one side of the memory layer in the direction of the layer surface is lower than a heat conductivity of surroundings thereof.Type: GrantFiled: July 28, 2011Date of Patent: July 30, 2013Assignee: Sony CorporationInventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
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Patent number: 8477529Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.Type: GrantFiled: September 19, 2012Date of Patent: July 2, 2013Assignee: Avalanche Technology, Inc.Inventors: Parviz Keshtbod, Ebrahim Abedifard
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Patent number: 8470462Abstract: A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation process. A Co10Fe70B20/NCC/Co10Fe70B20, Co10Fe70B20/NCC/Co10Fe70B20/NCC, or Co10Fe70B20/NCC/Co10Fe70B20/NCC/Co10Fe70B20 free layer configuration where NCC is a nanocurrent channel layer made of Fe(20%)-SiO2 is used to minimize Jc0 while enabling higher thermal stability, write voltage, read voltage, Ho, and Hc values that satisfy 64 Mb design requirements. The NCC layer is about 10 Angstroms thick to match the minimum Fe(Si) grain diameter size. The MTJ is annealed with a temperature of about 330° C. to maintain a high magnetoresistive ratio while maximizing Hk?(interfacial) for the free layer thereby reducing Heff and lowering the switching current. The Co10Fe70B20 layers are sputter deposited with a low pressure process with a power of about 15 Watts and an Ar flow rate of 40 standard cubic centimeters per minute to lower Heff for the free layer.Type: GrantFiled: November 30, 2010Date of Patent: June 25, 2013Assignee: MagIC Technologies, Inc.Inventors: Cheng T. Horng, Ru-Ying Tong, Guenole Jan
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Patent number: 8435652Abstract: A magnetic stack structure is disclosed. The magnetic stack structure includes two metal layers and a free layer sandwiched by the two metal layers. The thickness of the free layer is 1-30 nm. The thickness of the metal layers are 0.1-20 nm respectively.Type: GrantFiled: July 9, 2009Date of Patent: May 7, 2013Assignee: National Yunlin University of Science and TechnologyInventors: Te-Ho Wu, Lin-Hsiu Ye, Ching-Ming Lee
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Patent number: 8427866Abstract: There are provided magnetic storage elements capable of performing a high-reliability write operation by inhibiting erroneous reversal of data of the magnetic storage element put in a semi-selected state, and a magnetic storage device using this. A recording layer having an easy axis and a hard axis overlaps at least one of a first or second conductive layer at the entire region thereof in plan view. First endpoints of a first line segment along the easy axis and maximum in dimension overlapping the recording layer in plan view don't overlap the second conductive layer in plan view. At least one of second endpoints of a pair of endpoints of a second line segment passing through the middle point of the first line segment, orthogonal to the first line segment in plan view, and overlapping the recording layer in plan view doesn't overlap the first conductive layer in plan view.Type: GrantFiled: February 15, 2012Date of Patent: April 23, 2013Assignee: Renesas Electronics CorporationInventors: Takashi Takenaga, Takeharu Kuroiwa, Taisuke Furukawa
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Patent number: 8422287Abstract: An MRAM array structure and a method of its operation that is not subject to accidental writing on half-selected elements. Each element of the MRAM is an MTJ (magnetic tunneling junction) cell operating in accord with an STT (spin torque transfer) scheme for changing its free layer magnetization state and each cell is patterned to have a C-shape in the horizontal plane. The cell thereby operates by C-mode switching to provide stability against accidental writing by half-selection. During operation, switching of a cell's magnetization is accomplished with the assist of the pulsed magnetic fields of additional word lines that are formed either orthogonal to or parallel to the existing bit lines and that can carry currents in either direction as required to provide the assist.Type: GrantFiled: September 9, 2010Date of Patent: April 16, 2013Assignee: MagIC Technologies, Inc.Inventors: Tai Min, Qiang Chen, Po Kang Wang
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Low-crystallization temperature MTJ for spin-transfer torque magnetic random access memory (STTMRAM)
Patent number: 8422286Abstract: A spin-torque transfer memory random access memory (STTMRAM) element is disclosed and has a fixed layer, a barrier layer formed upon the fixed layer, and a free layer comprised of a low-crystallization temperature alloy of CoFeB—Z where Z is below 25 atomic percent of one or more of titanium, (Ti), yittrium (Y), zirconium (Zr), and vanadium (V), wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer.Type: GrantFiled: April 2, 2012Date of Patent: April 16, 2013Assignee: Avalanche Technology, Inc.Inventors: Rajiv Yadav Ranjan, Roger Klas Malmhall -
Patent number: 8422285Abstract: A method and system for providing a magnetic junction usable in a magnetic memory are described. The magnetic junction includes first and second pinned layers, first and second nonmagnetic spacer layers, and a free layer. The pinned layers are nonmagnetic layer-free and self-pinned. In some aspects, the magnetic junction is configured to allow the free and second pinned layers to be switched between stable magnetic states when write currents are passed therethrough. The magnetic junction has greater than two stable states. In other aspects, the magnetic junction includes at least third and fourth spacer layers, a second free layer therebetween, and a third pinned layer having a pinned layer magnetic moment, being nonmagnetic layer-free, and being coupled to the second pinned layer. The magnetic junction is configured to allow the free layers to be switched between stable magnetic states when write currents are passed therethrough.Type: GrantFiled: February 23, 2011Date of Patent: April 16, 2013Assignee: Grandis, Inc.Inventors: Dmytro Apalkov, Xueti Tang, Vladimir Nikitin, Alexander A. G. Driskill-Smith, Steven M. Watts, David Druist
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Patent number: 8416618Abstract: The invention relates to a writable magnetic element comprising a stack of layers presenting a write magnetic layer, wherein the stack has a central layer of at least one magnetic material presenting a direction of magnetization that is parallel or perpendicular to the plane of the central layer, said central layer being sandwiched between first and second outer layers of non-magnetic materials, the first outer layer comprising a first non-magnetic material and the second outer layer comprising a second non-magnetic material that is different from the first non-magnetic material, at least the second non-magnetic material being electrically conductive, wherein it includes a device for causing current to flow through the second outer layer and the central layer in a current flow direction parallel to the plane of the central layer, and a device for applying a magnetic field having a component along a magnetic field direction that is either parallel or perpendicular to the plane of the central layer and the currType: GrantFiled: October 6, 2010Date of Patent: April 9, 2013Assignees: Centre National de la Recherche Scientifique, Commissariat a l'Energie Atomique et aux Energies Alternatives, Universite Joseph Fourier, Institut Catala de Nanotechnologia (ICN), Institucio Catalana de Recerca I Estudis Avancats (ICREA)Inventors: Gilles Gaudin, Ioan Mihai Miron, Pietro Gambardella, Alain Schuhl
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Patent number: 8411497Abstract: A method and system for providing a magnetic memory are described. The method and system include providing magnetic storage cells, bit lines coupled with the magnetic storage cells, preset lines, and word lines coupled with the magnetic storage cells. Each magnetic storage cell includes magnetic element(s). The bit lines drive write current(s) through selected storage cell(s) of the magnetic storage cells to write to the selected storage cell(s). The preset lines drive preset current(s) in proximity to but not through the selected storage cell(s). The preset current(s) generate magnetic field(s) to orient the magnetic element(s) of the selected storage cell(s) in a direction. The word lines enable the selected storage cell(s) for writing. Either the bit lines reside between the preset lines and the storage cells or the preset lines reside between the storage cells and on a storage cell side of the bit lines.Type: GrantFiled: May 5, 2010Date of Patent: April 2, 2013Assignee: Grandis, Inc.Inventors: Adrian E. Ong, Xueti Tang
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Patent number: 8411499Abstract: [Object] To provide a recording method for a magnetic memory device including a recording layer that is capable of changing a magnetization direction and holds information as a magnetization direction of a magnetic body and a magnetization reference layer that is provided with respect to the recording layer with an insulation layer interposed therebetween and becomes a reference of the magnetization direction, the magnetic memory device being recorded with information by a current flowing between the recording layer and the magnetization reference layer via the insulation layer, the recording method being capable of maintaining, even when a write pulse considerably higher than an inversion threshold value is applied, a write error rate of 10?25 or less that is obtained when a write pulse a little larger than the inversion threshold value is applied. [Solving Means] While taking time of 2 ns or more, write power injected at a time a write pulse falls is reduced gradually.Type: GrantFiled: April 15, 2009Date of Patent: April 2, 2013Assignee: Sony CorporationInventors: Hiroyuki Ohmori, Masanori Hosomi, Tetsuya Yamamoto, Yutaka Higo, Kazutaka Yamane, Yuki Oishi, Hiroshi Kano
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Patent number: 8374025Abstract: A spin-torque transfer memory random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have either in-plane or perpendicular anisotropy.Type: GrantFiled: May 13, 2010Date of Patent: February 12, 2013Assignee: Avalanche Technology, Inc.Inventors: Rajiv Yadav Ranjan, Roger Klas Malmhall
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Patent number: 8335105Abstract: By inserting a spin polarizing layer (typically pure iron) within the free layer of a MTJ or GMR memory cell, dR/R can be improved without significantly affecting other free layer properties such as Hc. Additional performance improvements can be achieved by also inserting a surfactant layer (typically oxygen) within the free layer.Type: GrantFiled: March 7, 2007Date of Patent: December 18, 2012Assignee: Headway Technologies, Inc.Inventors: Hui-Chuan Wang, Tong Zhao, Kunliang Zhang, Min Li
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Patent number: 8331141Abstract: A multi-bit cell of magnetic random access memory comprises a magnetic tunnel junction element including a first and second free layer comprising a changeable magnetization oriented substantially perpendicular to a layer plane in its equilibrium state and a switching current, a first and second tunnel barrier layer, and a pinned layer comprising a fixed magnetization oriented substantially perpendicular to a layer plane, the pinned layer is disposed between the first and second free layers and is separated from the free layers by one of the tunnel barrier layers, a selection transistor electrically connected to a word line, and a bit line intersecting the word line. The magnetic tunnel junction element is disposed between the bit line and the selection transistor and is electrically connected to the bit line and the selection transistor, wherein the first and second free layers have substantially different switching currents.Type: GrantFiled: July 27, 2010Date of Patent: December 11, 2012Inventor: Alexander Mikhailovich Shukh
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Patent number: 8310862Abstract: It is made possible to provide a highly reliable magnetoresistive effect element and a magnetic memory that operate with low power consumption and current writing and without element destruction. The magnetoresistive effect element includes a first magnetization pinned layer comprising at least one magnetic layer and in which a magnetization direction is pinned, a magnetization free layer in which a magnetization direction is changeable, a tunnel barrier layer provided between the first magnetization pinned layer and the magnetization free layer, a non-magnetic metal layer provided on a first region in an opposite surface of the magnetization free layer from the tunnel barrier layer, a dielectric layer provided on a second region other than the first region in the opposite surface of the magnetization free layer from the tunnel barrier layer; and a second magnetization pinned layer provided to cover opposite surfaces of the non-magnetic metal layer and the dielectric layer from the magnetization free layer.Type: GrantFiled: June 10, 2009Date of Patent: November 13, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Saito, Hideyuki Sugiyama, Tomoaki Inokuchi
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Patent number: 8289757Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.Type: GrantFiled: May 12, 2010Date of Patent: October 16, 2012Assignee: Avalanche Technology, Inc.Inventors: Parviz Keshtbod, Ebrahim Abedifard