Magnetic Thin Film Patents (Class 365/171)
  • Patent number: 11366949
    Abstract: Embodiments of the present invention disclose an MRAM cell layout for 32 nm, 45 nm, and 65 nm CMOS process technology.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: June 21, 2022
    Assignee: III HOLDINGS 1, LLC
    Inventor: Krishnakumar Mani
  • Patent number: 11355694
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, and containing magnesium (Mg) and oxygen (O). The nonmagnetic layer further contains an additive element selected from fluorine (F), sulfur (S), hydrogen (H) and lithium (Li).
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: June 7, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tadaomi Daibou, Yasushi Nakasaki, Tadashi Kai, Hiroki Kawai, Takamitsu Ishihara, Junichi Ito
  • Patent number: 11315616
    Abstract: To provide a control circuit capable of not only suppressing an increase in power consumption with a simple configuration but also preventing erroneous writing and destruction of a memory element. Provided is a control circuit that outputs a signal for discharging charges accumulated in a source line and a bit line according to activation of a word line, and outputs a signal for making the source line and the bit line be in a floating state by a start of writing or reading, with respect to a memory cell including the source line, the bit line, a transistor that is provided between the source line and the bit line, and switches on and off by a potential of the word line, and a memory element connected to the transistor in series.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 26, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hiroyuki Tezuka
  • Patent number: 11283010
    Abstract: A magnetic memory element having a magnetic free layer and a magnetic reference layer with a non-magnetic barrier layer between the magnetic reference layer and the magnetic free layer. A spin current layer (which may be a precessional spin current layer) is located adjacent to the magnetic free layer and is separated from the magnetic free layer by a non-magnetic coupling layer. A material layer adjacent to and in contact with the spin current layer, has a material composition and thickness that are chosen to provide a desired effective magnetization in the spin current layer. The material layer, which may be a capping layer or a seed layer, can be constructed of a material other than tantalum which may include one or more of Zr, Mo, Ru, Rh, Pd, Hf, W, Ir, Pt and/or alloys and/or nitrides of these elements.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: March 22, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Jorge Vasquez, Bartlomiej Adam Kardasz, Cheng Wei Chiu, Mustafa Pinarbasi
  • Patent number: 11280639
    Abstract: A system includes a multiturn counter that can store a magnetic state associated with a number of accumulated turns of a magnetic field. The multiturn counter includes a plurality of magnetoresistive elements electrically coupled in series with each other. A matrix of electrical connections is arranged to connect magnetoresistive elements of the plurality of magnetoresistive elements to other magnetoresistive elements of the plurality of magnetoresistive elements.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: March 22, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventor: Jochen Schmitt
  • Patent number: 11264562
    Abstract: A magnetic memory device includes a first electrode, a second electrode, and a layer stack located between the first electrode and the second electrode. The layer stack includes a reference layer, a tunnel barrier layer, a free layer, and a magnetoelectric multiferroic layer including at least one crystalline grain. The magnetization of the magnetoelectric multiferroic layer may be axial, canted, or in-plane. For axial or canted magnetization of the magnetoelectric multiferroic layer, a deterministic switching of the free layer may be achieved through coupling with the axial component of magnetization of the magnetoelectric multiferroic layer. Alternatively, the in-plane magnetization of the magnetoelectric multiferroic layer may be employed to induce precession of the magnetization angle of the free layer.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 1, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Bhagwati Prasad, Alan Kalitsov, Neil Smith
  • Patent number: 11232894
    Abstract: Disclosed is a method for generating, from a first electric current having a first frequency, a plurality of second currents each having a second respective frequency component, the method including the following steps: supplying a frequency distributor including a first set of pillars including a layer made from a first magnetic material and having a resonance frequency; exciting each pillar of the first set with an electromagnetic field having the first frequency, the ratio between twice the resonance frequency of each pillar of the first set and the first frequency being equal, to within ten percent, to a first natural integer; and generating, by each pillar of the first set, a second frequency component in the second respective current.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: January 25, 2022
    Assignees: THALES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Paolo Bortolotti, Julien Kermorvant, Vincent Cros, Bruno Marcilhac, Romain Lebrun
  • Patent number: 11233192
    Abstract: A hall bar device for a memory or logic application can include a gate electrode, a boron-doped chromia layer on the gate electrode; and a hall bar structure with four legs on the boron-doped chromia layer. For a memory application, the hall bar device can be written to by applying a pulse voltage across the gate electrode and one leg of the hall bar structure in the absence of an applied magnetic field; and can be read from by measuring a voltage across the one leg of the hall bar structure and its opposite leg.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: January 25, 2022
    Assignee: BOARD OF REGENTS OF THE UNIVERSITY OF NEBRASKA
    Inventors: Christian Binek, Ather Mahmood, William Echtenkamp
  • Patent number: 11227892
    Abstract: A method is presented for preventing excessive cap dielectric loss in memory areas and logic areas of a device. The method includes forming a first conductive line with top via and a conductive pad over a dielectric layer, wherein the conductive pad includes a microstud, depositing a dielectric cap in direct contact with the first conductive line and the conductive pad, and constructing a top electrode, a magnetic tunnel junction (MTJ) stack, and a bottom electrode in vertical alignment with the microstud of the conductive pad.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: January 18, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashim Dutta, Chih-Chao Yang, Ekmini A. De Silva, Dominik Metzler
  • Patent number: 11201282
    Abstract: Magnetic memory devices and methods are provided. In one aspect, a memory device may comprise a control circuitry and at least one array of memory structures. Each memory structure may comprise a metal layer and a first magnetic tunnel junction (MTJ) disposed on the metal layer. The metal layer may include a first region and a second region. Electrical resistivity of at least a first part of the first region is different from electrical resistivity of the second region. The first magnetic tunnel junction (MTJ) may comprise a first free layer adjacent to the metal layer, a first barrier layer adjacent to the first free layer, and a first reference layer adjacent to the first barrier layer. The first free layer is in contact with the first region of the metal layer.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: December 14, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Dan Yu
  • Patent number: 11171605
    Abstract: A spin torque oscillator includes a first electrode, a second electrode and a device layer stack located between the first electrode and the second electrode. The device layer stack includes a spin polarization layer including a first ferromagnetic material, an assist layer including a third ferromagnetic material, a ferromagnetic oscillation layer including a second ferromagnetic material located between the spin polarization layer and the assist layer, a nonmagnetic spacer layer located between the spin polarization layer and the ferromagnetic oscillation, and a nonmagnetic coupling layer located between the ferromagnetic oscillation layer and the assist layer. The assist layer is antiferromagnetically coupled to the ferromagnetic oscillation layer through the non-magnetic coupling layer, and the assist layer has a magnetization that is coupled to a magnetization of the ferromagnetic oscillation layer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 9, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yuankai Zheng, Zheng Gao, Susumu Okamura, James Freitag
  • Patent number: 11151296
    Abstract: A memory cell array includes a first column of memory cells, a second column of memory cells, a first bit line, a second bit line and a source line. The second column of memory cells is separated from the first column of memory cells in a first direction. The first column of memory cells and the second column of memory cells are arranged in a second direction. The first bit line is coupled to the first column of memory cells, and extends in the second direction. The second bit line is coupled to the second column of memory cells, and extends in the second direction. The source line extends in the second direction, is coupled to the first column of memory cells and the second column of memory cells.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Hsiang Weng, Yu-Der Chih
  • Patent number: 11133041
    Abstract: Embodiments of a memory, and calibration and operation methods thereof for reading data in memory cells are disclosed. In an example, an apparatus comprises transistors, and a charge sharing circuit coupled to the transistors through gate terminals of the transistors. The charge sharing circuit comprises a programmable electrical source, a first switch coupled to the programmable electrical source, a capacitor coupled to the first switch, and a second switch coupled to the capacitor, the first switch, and the gate terminals of the transistors. The programmable electrical source is configured to provide electrical charges to the capacitor when the first switch is turned on and the second switch is turned off. The capacitor is configured to provide at least a portion of the electrical charges to the gate terminals of the transistors when the first switch is turned off and the second switch is turned on.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: September 28, 2021
    Assignee: WUXI PETABYTE TECHNOLOGIES CO, LTD.
    Inventor: Feng Pan
  • Patent number: 11094877
    Abstract: This invention is about a method to make an MRAM element with small dimension, by making an MTJ as close as possible to the via, ideally aligning the MTJ and the via in a direction perpendicular to the wafer surface, for making the MRAM element dimension as small as possible. The invention provides a process scheme to flatten the interface of bottom electrode during film deposition, which ensures a good deposition of atomically smooth MTJ multilayer as close as possible to an associated via which otherwise might be atomically rough. The flattening scheme is first to deposit a thin amorphous conducting layer in the middle of BE deposition and immediately to bombard the amorphous layer by low energy ions to provide kinetic energy for surface atom diffusion to move from high point to low kinks. With such surface flattening scheme, not only the MRAM element can be made extremely small, but its device performance and magnetic stability can also be greatly improved.
    Type: Grant
    Filed: March 26, 2016
    Date of Patent: August 17, 2021
    Assignee: T3Memory USA, Inc.
    Inventor: Rongfu Xiao
  • Patent number: 11087811
    Abstract: An analog Magnetoresistive Random Access Memory (MRAM) cell is provided. The analog MRAM cell includes a magnetic free layer having a first domain having a first magnetization direction, a second domain having a second magnetization direction opposite to the first magnetization direction and a domain wall located between the first domain and the second domain. The analog MRAM cell further includes a magnetically pinned layer. The analog MRAM cell also includes an insulating tunnel barrier between the magnetic free layer and the magnetically pinned layer. The analog MRAM cell additionally includes an electrode located adjacent to the magnetic free layer configured to generate heat by supplying current to decrease a conductance of the magnetic free layer.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Akiyo Iwashina, Atsuya Okazaki, Takeo Yasuda
  • Patent number: 11074950
    Abstract: A metamagnetic tunneling-based spin valve device for multistate magnetic memory comprising an electronic memory logic element with four stable resistance states. A metamagnetic tunneling-based spin valve device for multistate magnetic memory comprising a layer of a metamagnetic material, a layer of a nonmagnetic material on the layer of a metamagnetic material, and a layer of a ferromagnetic material on the layer of a nonmagnetic material. A method of making a metamagnetic tunneling-based spin valve device for multistate magnetic memory.
    Type: Grant
    Filed: April 13, 2019
    Date of Patent: July 27, 2021
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Olaf M. J. van 't Erve, Steven P. Bennett, Adam L. Friedman
  • Patent number: 11056642
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, and the tunnel barrier layer has a spinel structure represented by a composition formula of AIn2Ox(0<x?4), and an A-site is a non-magnetic divalent cation which is one or more selected from a group consisting of magnesium, zinc and cadmium.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: July 6, 2021
    Assignee: TDK CORPORATION
    Inventors: Tomoyuki Sasaki, Katsuyuki Nakada, Tatsuo Shibata
  • Patent number: 11037715
    Abstract: A magnetic sensor includes a plurality of magnetic detection elements, and a plurality of magnetic field generators associated with the plurality of magnetic detection elements. Each of the plurality of magnetic field generators includes a first ferromagnetic material section and a first antiferromagnetic material section. The first antiferromagnetic material section is in contact with and exchange-coupled to the first ferromagnetic material section. The first ferromagnetic material section has an overall magnetization. The plurality of magnetic field generators includes first and second magnetic field generators configured so that the overall magnetization of the first ferromagnetic material section of the first magnetic field generator is in a different direction from the overall magnetization of the first ferromagnetic material section of the second magnetic field generator.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: June 15, 2021
    Assignee: TDK CORPORATION
    Inventor: Yosuke Komasaki
  • Patent number: 11038099
    Abstract: An apparatus is provided which comprises: a first magnet with perpendicular magnetic anisotropy (PMA); a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba-Bychkov effect; a second magnet with PMA; a magnetoelectric layer adjacent to the second magnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
  • Patent number: 11029847
    Abstract: In high performance computing, the potential compute power in a data center will scale to and beyond a billion-billion calculations per second (“Exascale” computing levels). Limitations caused by hierarchical memory architectures where data is temporarily stored in slower or less available memories will increasingly limit high performance computing systems from approaching their maximum potential processing capabilities. Furthermore, time spent and power consumed copying data into and out of a slower tier memory will increase costs associated with high performance computing at an accelerating rate. New technologies, such as the novel Zero Copy Architecture disclosed herein, where each compute node writes locally for performance, yet can quickly access data globally with low latency will be required. The result is the ability to perform burst buffer operations and in situ analytics, visualization and computational steering without the need for a data copy or movement.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: June 8, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kirill Malkin, Steve Dean, Michael Woodacre, Eng Lim Goh
  • Patent number: 11017826
    Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first counter magnetic layer is provided between the third portion and the first magnetic layer in a first direction crossing a second direction. The second direction is from the first portion toward the second portion. The first nonmagnetic layer is provided between the first magnetic layer and the first counter magnetic layer. The third portion includes a first position, and a second position between the first position and the first counter magnetic layer in the first direction. A second concentration of boron at the second position is lower than a first concentration of boron at the first position.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 25, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yushi Kato, Soichi Oikawa, Hiroaki Yoda
  • Patent number: 11017853
    Abstract: A memory device and an operating method of the memory device, the memory device including a memory cell array including a plurality of memory cells respectively arranged at points at which a plurality of word lines and a plurality of bit lines cross; and a control logic circuit configured to precharge a selected word line connected to a selected memory cell and precharge a selected bit line connected to the selected memory cell in a read operation, wherein the control logic circuit is further configured to precharge a first unselected word line among unselected word lines to a second voltage when the selected word line is precharged to a first voltage, a level of the first voltage is lower than a level of a third voltage applied to an unselected bit line when the selected word line is precharged to the first voltage, and a level of the second voltage is higher than the level of the third voltage.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Ryul Kim, Moo-Sung Kim
  • Patent number: 11004510
    Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zengtao T. Liu, Kirk D. Prall
  • Patent number: 10998490
    Abstract: A magnetic element includes a first magnetic layer and a first nonmagnetic layer. An angle ?0 between a first direction and the magnetization direction of the first magnetic layer satisfies 0°<?0<90° or 90°<?0<180° in a state in which neither a voltage nor a magnetic field is substantially applied to the first magnetic layer; and the first direction is from the first nonmagnetic layer toward the first magnetic layer. A resistance·area of the first nonmagnetic layer is 10 ??m2 or more.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: May 4, 2021
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Rie Matsumoto, Takayuki Nozaki, Shinji Yuasa, Hiroshi Imamura
  • Patent number: 10971245
    Abstract: A system and method for testing a magnetic memory cell in a bit cell array to determine whether the electrical resistance values of the memory cell are within acceptable parameters. The system and method allows for the determination of the electrical resistance of the memory cell without parasitic resistance associated with that memory cell in order to accurately determine the electrical resistance of the memory cell.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 6, 2021
    Assignee: SPIN MEMORY, INC.
    Inventor: Minh Quang Tran
  • Patent number: 10971681
    Abstract: A method for manufacturing an array of magnetic memory elements, wherein first memory element types are formed in a first region and second type of magnetic memory element types are formed in a second region. A shadow-mask is used during deposition to limit the deposition of at least one layer of memory element material to only the second region wherein the second memory element types are to be formed. The method can include depositing full film magnetic memory element layers over an entire substrate and then using the shadow-mask to deposit at least one performance altering material in the second memory element region. Alternatively, a first shadow-mask can be used to deposit a series of first memory element layers in a first region, and a second shadow-mask can be used to deposit a plurality of second memory element layers in a second region.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: April 6, 2021
    Assignee: SPIN MEMORY, INC.
    Inventors: Kadriye Deniz Bozdag, Eric Michael Ryan, Kuk-Hwan Kim
  • Patent number: 10964748
    Abstract: A magnetoresistive memory device includes a first electrode, a second electrode, and a layer stack containing an electric field-modulated magnetic transition layer and a ferroelectric insulator layer located between the first electrode and the second electrode, The electric field-modulated magnetic transition layer includes a non-metallic magnetic material having a ferromagnetic state and a non-ferromagnetic state with a state transition therebetween that depends on an external electric field.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: March 30, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Bhagwati Prasad, Alan Kalitsov
  • Patent number: 10953319
    Abstract: A STT-MRAM comprises apparatus, a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a bias voltage controlled perpendicular anisotropy of a recording layer through an interlayer interaction to achieve a lower spin-transfer switching current. The anisotropy modification layer is under an electric field along a perpendicular direction with a proper voltage between a digital line and a bit line from a control circuitry, accordingly, the energy switch barrier is reduced in the spin-transfer recording while maintaining a high thermal stability and a good retention.
    Type: Grant
    Filed: January 12, 2014
    Date of Patent: March 23, 2021
    Inventor: Yimin Guo
  • Patent number: 10950661
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a memory cell, wherein the memory cell includes a transistor having a source and a drain, a first resistive unit in electrical communication with the source, and a second resistive unit in electrical communication with the drain. The first resistive unit includes a first bottom electrode, a first top electrode, and a first resistive element positioned between the first bottom electrode and the first top electrode. The second resistive unit includes a second bottom electrode, a second top electrode, and a second resistive element positioned between the second bottom electrode and the second top electrode.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: March 16, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lanxiang Wang, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 10943632
    Abstract: A magnetic storage device includes a memory cell with a magnetoresistive effect element and a switching element connected in series. The magnetoresistive effect element is configured to change from a first resistance state to a second resistance state that is lower in resistance than the first resistance state in response to a first write operation flowing current in a first direction through the memory cell and to change from the second resistance state to the first resistance state in response to a second write operation flowing current in a second direction through the memory cell. The switching element has a first voltage drop associated with current flows in the first direction and has a second voltage drop associated with current flows the second direction that is lower than the first voltage drop.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hironobu Furuhashi
  • Patent number: 10901049
    Abstract: A magnetic sensor includes: a substrate; and first and second magnetoresistive devices on one surface of the substrate. Each of the first and second magnetoresistive devices includes: a fixed layer having an easy magnetization axis perpendicular to the one surface and having a fixed magnetization direction; a free layer having a variable magnetization direction; and an intermediate layer made of a non-magnetic material and arranged between the fixed layer and the free layer. The fixed layer includes a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer arranged between the first ferromagnetic layer and the second ferromagnetic layer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: January 26, 2021
    Assignees: DENSO CORPORATION, TOHOKU UNIVERSITY
    Inventors: Takamoto Furuichi, Kenichi Ao, Ryuichiro Abe, Yasuo Ando, Mikihiko Oogane, Takafumi Nakano
  • Patent number: 10891997
    Abstract: An memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A first circuit provides a first voltage on an addressed bit line of the plurality of bit lines during a write cycle, wherein the addressed bit line corresponds to an addressed memory cell.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 12, 2021
    Assignee: Spin Memory, Inc.
    Inventors: Neal Berger, Mourad El Baraji, Lester Crudele, Benjamin Louie
  • Patent number: 10878930
    Abstract: A layout method includes: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Sheng Chang, Yao-Jen Yang, Shao-Yu Chou, Yih Wang
  • Patent number: 10861527
    Abstract: Systems and methods for reducing write error rate in MeRAM applications in accordance with various embodiments of the invention are illustrated. One embodiment includes a method for a writing mechanism for a magnetoelectric random access memory cell, the method including applying a voltage of a given polarity for a given period of time across a magnetoelectric junction bit of the magnetoelectric random access memory cell, wherein application of the voltage of the given polarity across the magnetoelectric junction bit reduces the perpendicular magnetic anisotropy and magnetic coercivity of the ferromagnetic free layer through a voltage controlled magnetic anisotropy effect, and lowering the applied voltage of the given polarity before the end of the given period of time, wherein the given period of time is approximately half of a precessional period of the ferromagnetic free layer.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: December 8, 2020
    Assignee: Inston, Inc.
    Inventors: Albert Lee, Hochul Lee
  • Patent number: 10861521
    Abstract: A magnetic storage element includes a first magnetic layer having a magnetization easy axis in a direction perpendicular to a surface of the first magnetic layer. A first non-magnetic layer is on the first magnetic layer. A second magnetic layer is on the first non-magnetic layer and has a fixed magnetization direction. A second non-magnetic layer is on the second magnetic layer. A third magnetic layer is on the second non-magnetic layer and has a fixed magnetization direction perpendicular to a surface of the third magnetic layer. A third non-magnetic layer is on the third magnetic layer. A storage layer on the third non-magnetic layer and having a variable magnetization direction with a magnetization easy axis in a direction perpendicular to a surface of the storage layer. Change in a magnetization direction of the first magnetic layer is easier than in the storage layer.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: December 8, 2020
    Assignee: Sony Corporation
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Hiroyuki Uchida
  • Patent number: 10849527
    Abstract: According to one embodiment, a magnetic sensor includes a first sensor element and a first interconnect. The first sensor element includes a first magnetic layer, a first opposing magnetic layer, and a first nonmagnetic layer provided between the first magnetic layer and the first opposing magnetic layer. A first magnetization of the first magnetic layer is aligned with a first length direction crossing a first stacking direction from the first magnetic layer toward the first opposing magnetic layer. At least a portion of the first interconnect extends along the first length direction. The first interconnect cross direction crosses the first length direction and is from the first sensor element toward the portion of the first interconnect. A first electrical resistance of the first sensor element changes according to an alternating current flowing in the first interconnect and a sensed magnetic field applied to the first sensor element.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: December 1, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Iwasaki, Akira Kikitsu, Satoshi Shirotori
  • Patent number: 10818329
    Abstract: A magnetic tunnel junction with out-of-plane magnetisation includes a storage layer; a reference layer; and a tunnel barrier layer. The two magnetisation states of the storage layer are separated by an energy barrier including a contribution due to the shape anisotropy of the storage layer and a contribution of interfacial origin for each interface of the storage layer. The storage layer has a thickness comprised between 0.8 and 8 times a characteristic dimension of a planar section of the tunnel junction. The contribution to the energy barrier due to the shape anisotropy of the storage layer is at least two times greater and preferably at least 4 times greater than the contributions to the energy barrier of interfacial origin.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: October 27, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS), INSTITUT POLYTECHNIQUE DE GRENOBLE
    Inventors: Nicolas Perrissin-Fabert, Bernard Dieny, Lucian Prejbeanu, Ricardo Sousa
  • Patent number: 10811069
    Abstract: Structures for a non-volatile memory and methods for forming and using such structures. The structure includes a bitcell having a non-volatile memory element and a transmission gate. The transmission gate includes an n-type field-effect transistor and a p-type field effect transistor. The n-type field-effect transistor has a first drain region, a first source region, and a first gate electrode. The p-type field-effect transistor has a second drain region, a second source region coupled in parallel with the first source region, and a second gate electrode. The first drain region of the n-type field-effect transistor and the second drain region of the p-type field-effect transistor are coupled in parallel with the non-volatile memory element.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: October 20, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Harsh N. Patel, Bipul C. Paul
  • Patent number: 10796748
    Abstract: Methods, devices, and systems are disclosed that generally perform a time delay determination of a voltage change on a signal node to determine a corresponding signal value on another node causing the voltage change. In an example the circuit device includes a first circuit configured to couple, when enabled, a signal value onto a first node, and a read circuit having an input coupled to the first node. The read circuit is configured to effect a voltage transition of a signal node at a variable rate corresponding to the voltage of the first node, and to determine the signal value based upon a time-to-transition measurement of the signal node.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: October 6, 2020
    Assignee: R&D 3 LLC
    Inventor: Ravindraraj Ramaraju
  • Patent number: 10790013
    Abstract: An SRAM cell in a bit interleaved memory architecture with two phase sequential write scheme to achieve 100% write ability and the SNM target with bit interleaved architecture in SRAM.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: September 29, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Prashant Dubey, Ishita Satishchandra Desai, Shivangi Mittal, Surya Prakash Gupta, Jamil Kawa
  • Patent number: 10777606
    Abstract: A first memory device includes a first magnetoresistive cell having a plurality of deposition layers. A second memory device includes a second magnetoresistive cell having a plurality of deposition layers. Each of the plurality of deposition layers of the second magnetoresistive cell corresponds to one of the plurality of deposition layers of the first magnetoresistive cell. One of the plurality of deposition layers of the second magnetoresistive cell is thinner than a corresponding deposition layer of the plurality of deposition layers of the first magnetoresistive cell.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jae hoon Kim
  • Patent number: 10770651
    Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bilayers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: MD Tofizur Rahman, Christopher J. Wiegand, Kaan Oguz, Daniel G. Ouellette, Brian Maertz, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Oleg Golonzka, Tahir Ghani
  • Patent number: 10763425
    Abstract: An example device for performing a write operation, the device including a Magnetic Tunnel Junction (MTJ) element and processing circuitry. The MTJ element including a free structure, a pinned structure, and a tunnel barrier arranged between the free structure and the pinned structure. The processing circuitry is configured to receive an instruction to set the MTJ element to a low-resistance state and provide a write voltage to the MTJ element such that the tunnel barrier breaks down to generate a low-resistance channel between the free structure and the pinned structure.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: September 1, 2020
    Assignee: Honeywell International Inc.
    Inventor: Romney R. Katti
  • Patent number: 10740017
    Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 11, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Chando Park, Wei-Chuan Chen, Sungryul Kim, Adam Edward Newham, Seung Hyuk Kang, Rashid Ahmed Akbar Attar
  • Patent number: 10734571
    Abstract: Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Joel D. Chudow, Daniel C. Worledge
  • Patent number: 10714202
    Abstract: A magnetic memory included a conductive line that extends in a first direction along a substrate. A first columnar body is in a memory cell array region of the substrate and extends in a second direction from the substrate. A first end of the first columnar body contacts the conductive line. The first columnar body is comprised of a first magnetic material and has magnetic domains adjacent to one another along a length of the first columnar body in the second direction. A second columnar body is in a peripheral region of the substrate and extending in the second direction from the substrate. A first end of the second columnar body contacts the conductive line, and a second end is connected to a control circuit. The second columnar body also is comprised of the first magnetic material.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: July 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshihiro Ueda
  • Patent number: 10706914
    Abstract: A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Hsin-Chih Yu, Shu-Ru Wang
  • Patent number: 10706923
    Abstract: A resistive random-access memory (RRAM) system includes an RRAM cell. The RRAM cell includes a first select line and a second select line, a word line, a bit line, a first resistive memory device, a first switching device, a second resistive memory device, a second switching device, and a comparator. The first resistive memory device is coupled between a first access node and the bit line. The first switching device is coupled between the first select line and the first access node. The second resistive memory device is coupled between a second access node and the bit line. The second switching device is coupled between the second select line and the second access node. The comparator includes a first input coupled to the bit line, a second input, and an output.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 7, 2020
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Jae-sun Seo, Shimeng Yu
  • Patent number: 10658013
    Abstract: The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 19, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Frederick Neumeyer
  • Patent number: RE47975
    Abstract: An STTMRAM element includes a magnetic tunnel junction (MTJ) having a perpendicular magnetic orientation. The MTJ includes a barrier layer, a free layer formed on top of the barrier layer and having a magnetic orientation that is perpendicular and switchable relative to the magnetic orientation of the fixed layer. The magnetic orientation of the free layer switches when electrical current flows through the STTMRAM element. A switching-enhancing layer (SEL), separated from the free layer by a spacer layer, is formed on top of the free layer and has an in-plane magnetic orientation and generates magneto-static fields onto the free layer, causing the magnetic moments of the outer edges of the free layer to tilt with an in-plane component while minimally disturbing the magnetic moment at the center of the free layer to ease the switching of the free layer and to reduce the threshold voltage/current.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 5, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Jing Zhang, Yiming Huai, Rajiv Yadav Ranjan, Yuchen Zhou, Zihui Wang, Xiaojie Hao