Magnetic Thin Film Patents (Class 365/171)
  • Patent number: 10971681
    Abstract: A method for manufacturing an array of magnetic memory elements, wherein first memory element types are formed in a first region and second type of magnetic memory element types are formed in a second region. A shadow-mask is used during deposition to limit the deposition of at least one layer of memory element material to only the second region wherein the second memory element types are to be formed. The method can include depositing full film magnetic memory element layers over an entire substrate and then using the shadow-mask to deposit at least one performance altering material in the second memory element region. Alternatively, a first shadow-mask can be used to deposit a series of first memory element layers in a first region, and a second shadow-mask can be used to deposit a plurality of second memory element layers in a second region.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: April 6, 2021
    Assignee: SPIN MEMORY, INC.
    Inventors: Kadriye Deniz Bozdag, Eric Michael Ryan, Kuk-Hwan Kim
  • Patent number: 10971245
    Abstract: A system and method for testing a magnetic memory cell in a bit cell array to determine whether the electrical resistance values of the memory cell are within acceptable parameters. The system and method allows for the determination of the electrical resistance of the memory cell without parasitic resistance associated with that memory cell in order to accurately determine the electrical resistance of the memory cell.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 6, 2021
    Assignee: SPIN MEMORY, INC.
    Inventor: Minh Quang Tran
  • Patent number: 10964748
    Abstract: A magnetoresistive memory device includes a first electrode, a second electrode, and a layer stack containing an electric field-modulated magnetic transition layer and a ferroelectric insulator layer located between the first electrode and the second electrode, The electric field-modulated magnetic transition layer includes a non-metallic magnetic material having a ferromagnetic state and a non-ferromagnetic state with a state transition therebetween that depends on an external electric field.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: March 30, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Bhagwati Prasad, Alan Kalitsov
  • Patent number: 10953319
    Abstract: A STT-MRAM comprises apparatus, a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a bias voltage controlled perpendicular anisotropy of a recording layer through an interlayer interaction to achieve a lower spin-transfer switching current. The anisotropy modification layer is under an electric field along a perpendicular direction with a proper voltage between a digital line and a bit line from a control circuitry, accordingly, the energy switch barrier is reduced in the spin-transfer recording while maintaining a high thermal stability and a good retention.
    Type: Grant
    Filed: January 12, 2014
    Date of Patent: March 23, 2021
    Inventor: Yimin Guo
  • Patent number: 10950661
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a memory cell, wherein the memory cell includes a transistor having a source and a drain, a first resistive unit in electrical communication with the source, and a second resistive unit in electrical communication with the drain. The first resistive unit includes a first bottom electrode, a first top electrode, and a first resistive element positioned between the first bottom electrode and the first top electrode. The second resistive unit includes a second bottom electrode, a second top electrode, and a second resistive element positioned between the second bottom electrode and the second top electrode.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: March 16, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lanxiang Wang, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 10943632
    Abstract: A magnetic storage device includes a memory cell with a magnetoresistive effect element and a switching element connected in series. The magnetoresistive effect element is configured to change from a first resistance state to a second resistance state that is lower in resistance than the first resistance state in response to a first write operation flowing current in a first direction through the memory cell and to change from the second resistance state to the first resistance state in response to a second write operation flowing current in a second direction through the memory cell. The switching element has a first voltage drop associated with current flows in the first direction and has a second voltage drop associated with current flows the second direction that is lower than the first voltage drop.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hironobu Furuhashi
  • Patent number: 10901049
    Abstract: A magnetic sensor includes: a substrate; and first and second magnetoresistive devices on one surface of the substrate. Each of the first and second magnetoresistive devices includes: a fixed layer having an easy magnetization axis perpendicular to the one surface and having a fixed magnetization direction; a free layer having a variable magnetization direction; and an intermediate layer made of a non-magnetic material and arranged between the fixed layer and the free layer. The fixed layer includes a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer arranged between the first ferromagnetic layer and the second ferromagnetic layer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: January 26, 2021
    Assignees: DENSO CORPORATION, TOHOKU UNIVERSITY
    Inventors: Takamoto Furuichi, Kenichi Ao, Ryuichiro Abe, Yasuo Ando, Mikihiko Oogane, Takafumi Nakano
  • Patent number: 10891997
    Abstract: An memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A first circuit provides a first voltage on an addressed bit line of the plurality of bit lines during a write cycle, wherein the addressed bit line corresponds to an addressed memory cell.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 12, 2021
    Assignee: Spin Memory, Inc.
    Inventors: Neal Berger, Mourad El Baraji, Lester Crudele, Benjamin Louie
  • Patent number: 10878930
    Abstract: A layout method includes: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Sheng Chang, Yao-Jen Yang, Shao-Yu Chou, Yih Wang
  • Patent number: 10861527
    Abstract: Systems and methods for reducing write error rate in MeRAM applications in accordance with various embodiments of the invention are illustrated. One embodiment includes a method for a writing mechanism for a magnetoelectric random access memory cell, the method including applying a voltage of a given polarity for a given period of time across a magnetoelectric junction bit of the magnetoelectric random access memory cell, wherein application of the voltage of the given polarity across the magnetoelectric junction bit reduces the perpendicular magnetic anisotropy and magnetic coercivity of the ferromagnetic free layer through a voltage controlled magnetic anisotropy effect, and lowering the applied voltage of the given polarity before the end of the given period of time, wherein the given period of time is approximately half of a precessional period of the ferromagnetic free layer.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: December 8, 2020
    Assignee: Inston, Inc.
    Inventors: Albert Lee, Hochul Lee
  • Patent number: 10861521
    Abstract: A magnetic storage element includes a first magnetic layer having a magnetization easy axis in a direction perpendicular to a surface of the first magnetic layer. A first non-magnetic layer is on the first magnetic layer. A second magnetic layer is on the first non-magnetic layer and has a fixed magnetization direction. A second non-magnetic layer is on the second magnetic layer. A third magnetic layer is on the second non-magnetic layer and has a fixed magnetization direction perpendicular to a surface of the third magnetic layer. A third non-magnetic layer is on the third magnetic layer. A storage layer on the third non-magnetic layer and having a variable magnetization direction with a magnetization easy axis in a direction perpendicular to a surface of the storage layer. Change in a magnetization direction of the first magnetic layer is easier than in the storage layer.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: December 8, 2020
    Assignee: Sony Corporation
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Hiroyuki Uchida
  • Patent number: 10849527
    Abstract: According to one embodiment, a magnetic sensor includes a first sensor element and a first interconnect. The first sensor element includes a first magnetic layer, a first opposing magnetic layer, and a first nonmagnetic layer provided between the first magnetic layer and the first opposing magnetic layer. A first magnetization of the first magnetic layer is aligned with a first length direction crossing a first stacking direction from the first magnetic layer toward the first opposing magnetic layer. At least a portion of the first interconnect extends along the first length direction. The first interconnect cross direction crosses the first length direction and is from the first sensor element toward the portion of the first interconnect. A first electrical resistance of the first sensor element changes according to an alternating current flowing in the first interconnect and a sensed magnetic field applied to the first sensor element.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: December 1, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Iwasaki, Akira Kikitsu, Satoshi Shirotori
  • Patent number: 10818329
    Abstract: A magnetic tunnel junction with out-of-plane magnetisation includes a storage layer; a reference layer; and a tunnel barrier layer. The two magnetisation states of the storage layer are separated by an energy barrier including a contribution due to the shape anisotropy of the storage layer and a contribution of interfacial origin for each interface of the storage layer. The storage layer has a thickness comprised between 0.8 and 8 times a characteristic dimension of a planar section of the tunnel junction. The contribution to the energy barrier due to the shape anisotropy of the storage layer is at least two times greater and preferably at least 4 times greater than the contributions to the energy barrier of interfacial origin.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: October 27, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS), INSTITUT POLYTECHNIQUE DE GRENOBLE
    Inventors: Nicolas Perrissin-Fabert, Bernard Dieny, Lucian Prejbeanu, Ricardo Sousa
  • Patent number: 10811069
    Abstract: Structures for a non-volatile memory and methods for forming and using such structures. The structure includes a bitcell having a non-volatile memory element and a transmission gate. The transmission gate includes an n-type field-effect transistor and a p-type field effect transistor. The n-type field-effect transistor has a first drain region, a first source region, and a first gate electrode. The p-type field-effect transistor has a second drain region, a second source region coupled in parallel with the first source region, and a second gate electrode. The first drain region of the n-type field-effect transistor and the second drain region of the p-type field-effect transistor are coupled in parallel with the non-volatile memory element.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: October 20, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Harsh N. Patel, Bipul C. Paul
  • Patent number: 10796748
    Abstract: Methods, devices, and systems are disclosed that generally perform a time delay determination of a voltage change on a signal node to determine a corresponding signal value on another node causing the voltage change. In an example the circuit device includes a first circuit configured to couple, when enabled, a signal value onto a first node, and a read circuit having an input coupled to the first node. The read circuit is configured to effect a voltage transition of a signal node at a variable rate corresponding to the voltage of the first node, and to determine the signal value based upon a time-to-transition measurement of the signal node.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: October 6, 2020
    Assignee: R&D 3 LLC
    Inventor: Ravindraraj Ramaraju
  • Patent number: 10790013
    Abstract: An SRAM cell in a bit interleaved memory architecture with two phase sequential write scheme to achieve 100% write ability and the SNM target with bit interleaved architecture in SRAM.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: September 29, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Prashant Dubey, Ishita Satishchandra Desai, Shivangi Mittal, Surya Prakash Gupta, Jamil Kawa
  • Patent number: 10777606
    Abstract: A first memory device includes a first magnetoresistive cell having a plurality of deposition layers. A second memory device includes a second magnetoresistive cell having a plurality of deposition layers. Each of the plurality of deposition layers of the second magnetoresistive cell corresponds to one of the plurality of deposition layers of the first magnetoresistive cell. One of the plurality of deposition layers of the second magnetoresistive cell is thinner than a corresponding deposition layer of the plurality of deposition layers of the first magnetoresistive cell.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jae hoon Kim
  • Patent number: 10770651
    Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bilayers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: MD Tofizur Rahman, Christopher J. Wiegand, Kaan Oguz, Daniel G. Ouellette, Brian Maertz, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Oleg Golonzka, Tahir Ghani
  • Patent number: 10763425
    Abstract: An example device for performing a write operation, the device including a Magnetic Tunnel Junction (MTJ) element and processing circuitry. The MTJ element including a free structure, a pinned structure, and a tunnel barrier arranged between the free structure and the pinned structure. The processing circuitry is configured to receive an instruction to set the MTJ element to a low-resistance state and provide a write voltage to the MTJ element such that the tunnel barrier breaks down to generate a low-resistance channel between the free structure and the pinned structure.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: September 1, 2020
    Assignee: Honeywell International Inc.
    Inventor: Romney R. Katti
  • Patent number: 10740017
    Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 11, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Chando Park, Wei-Chuan Chen, Sungryul Kim, Adam Edward Newham, Seung Hyuk Kang, Rashid Ahmed Akbar Attar
  • Patent number: 10734571
    Abstract: Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Joel D. Chudow, Daniel C. Worledge
  • Patent number: 10714202
    Abstract: A magnetic memory included a conductive line that extends in a first direction along a substrate. A first columnar body is in a memory cell array region of the substrate and extends in a second direction from the substrate. A first end of the first columnar body contacts the conductive line. The first columnar body is comprised of a first magnetic material and has magnetic domains adjacent to one another along a length of the first columnar body in the second direction. A second columnar body is in a peripheral region of the substrate and extending in the second direction from the substrate. A first end of the second columnar body contacts the conductive line, and a second end is connected to a control circuit. The second columnar body also is comprised of the first magnetic material.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: July 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshihiro Ueda
  • Patent number: 10706923
    Abstract: A resistive random-access memory (RRAM) system includes an RRAM cell. The RRAM cell includes a first select line and a second select line, a word line, a bit line, a first resistive memory device, a first switching device, a second resistive memory device, a second switching device, and a comparator. The first resistive memory device is coupled between a first access node and the bit line. The first switching device is coupled between the first select line and the first access node. The second resistive memory device is coupled between a second access node and the bit line. The second switching device is coupled between the second select line and the second access node. The comparator includes a first input coupled to the bit line, a second input, and an output.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 7, 2020
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Jae-sun Seo, Shimeng Yu
  • Patent number: 10706914
    Abstract: A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Hsin-Chih Yu, Shu-Ru Wang
  • Patent number: 10658013
    Abstract: The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 19, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Frederick Neumeyer
  • Patent number: 10593414
    Abstract: The disclosed technology generally relates to magnetic devices, and more particularly to magnetic devices configured to generate a stream of domain walls propagating along an output magnetic bus. In an aspect, a magnetic device includes a magnetic propagation layer, which in turn includes a plurality of magnetic buses. The magnetic buses include at least a first magnetic bus, a second magnetic bus, and an output magnetic bus configured to guide propagating magnetic domain walls. The magnetic propagation layer further comprises a central region in which the magnetic buses converge and are joined together. In another aspect, a method includes providing the magnetic device and generating the stream of domain walls propagating along the output magnetic bus.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: March 17, 2020
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Adrien Vaysset, Odysseas Zografos
  • Patent number: 10573399
    Abstract: A multi-bit-per-cell three-dimensional read-only memory (3D-OTPMB) comprises a plurality of dummy bit lines. It comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP array comprises at least four dummy bit lines.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: February 25, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10535390
    Abstract: The present disclosure is directed to exemplary methods of manufacturing a magnetoresistive device. In one aspect, a method may include forming one or more regions of a magnetoresistive stack on a substrate, wherein the substrate includes at least one electronic device. The method also may include performing a sole annealing process on the substrate having the one or more magnetoresistive regions formed thereon, wherein the sole annealing process is performed at a first minimum temperature. Subsequent to performing the sole annealing process, the method may include patterning or etching at least a portion of the magnetoresistive stack. Moreover, subsequent to the step of patterning or etching the portion of the magnetoresistive stack, the method may include performing all additional processing on the substrate at a second temperature below the first minimum temperature.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: January 14, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Sarin A. Deshpande, Jon Slaughter
  • Patent number: 10522589
    Abstract: A magnetoresistive element comprises a novel Boron-absorbing cap multilayer provided on the top surface of an amorphous CoFeB (or CoB, FeB) ferromagnetic recording layer. As the magnetoresistive film is thermally annealed, a crystallization process occurs to form bcc CoFe grains having epitaxial growth with (100) plane parallel to the surface of the tunnel barrier layer as Boron elements migrate into the novel cap layer. Removing the top portion of the cap layer by means of sputtering etch or RIE etch processes followed by optional oxidization process, a thin thermally stable portion of cap layer is remained on top of the recording layer with low damping constant. Accordingly, a reduced write current is achieved for spin-transfer torque MRAM application.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: December 31, 2019
    Assignee: Shanghai Ciyu Information Technologies Co., Ltd.
    Inventor: Yimin Guo
  • Patent number: 10497858
    Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications, particularly for spin-orbit-torque magnetic random access memory (SOT MRAM) applications. In one embodiment, a magnetic tunnel junction (MTJ) device structure includes a magnetic tunnel junction (MTJ) pillar structure disposed on a substrate, and a gap surrounding the MTJ pillar structure. In yet another embodiment, a magnetic tunnel junction (MTJ) device structure includes a spacer layer surrounding a patterned reference layer and a tunneling barrier layer disposed on a patterned free layer, and a gap surrounding the patterned free layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 3, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Jaesoo Ahn, Hsin-wei Tseng, Lin Xue, Mahendra Pakala
  • Patent number: 10474304
    Abstract: An electrode array device has integrated programming circuitry within the unit cells for stable connection of individual electrode elements of the unit cells to one or more control signal lines. An array of unit cells are arranged in a two-dimensional array of rows and columns. Each unit cell includes an individual electrode element that is electrically connectable to at least one function line, and programming circuitry that is integrated into the unit cell and is operable to place the unit cell in a plurality of connection states corresponding to different states of electrical connection or disconnection to the at least one function line. The unit cells are individually selectable for programming and operation in one of the plurality of connection states. The programming circuitry includes storage elements and electronic switches that are operable to place the unit cells in different connection states.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: November 12, 2019
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Diego Gallardo
  • Patent number: 10468590
    Abstract: A perpendicular synthetic antiferromagnetic (pSAF) structure and method of making such a structure is disclosed. The pSAF structure can be a first high perpendicular Magnetic Anisotropy (PMA) multilayer and a second high PMA layer separated by a thin Ruthenium layer. Each PMA layer can be a first cobalt layer and a second cobalt layer separated by a nickel/cobalt multilayer. After each of the first and second PMA layers and the Ruthenium exchange coupling layer are deposited, the resulting structure goes through a high temperature annealing step, which results in each of the first and second PMA layers having a perpendicular magnetic anisotropy.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: November 5, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Bartlomiej Adam Kardasz, Mustafa Michael Pinarbasi, Jacob Anthony Hernandez
  • Patent number: 10460796
    Abstract: A system and method for high-speed, low-power cryogenic computing are presented, comprising ultrafast energy-efficient RSFQ superconducting computing circuits, and hybrid magnetic/superconducting memory arrays and interface circuits, operating together in the same cryogenic environment. An arithmetic logic unit and register file with an ultrafast asynchronous wave-pipelined datapath is also provided. The superconducting circuits may comprise inductive elements fabricated using both a high-inductance layer and a low-inductance layer. The memory cells may comprise superconducting tunnel junctions that incorporate magnetic layers. Alternatively, the memory cells may comprise superconducting spin transfer magnetic devices (such as orthogonal spin transfer and spin-Hall effect devices). Together, these technologies may enable the production of an advanced superconducting computer that operates at clock speeds up to 100 GHz.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: October 29, 2019
    Assignee: SeeQC, Inc.
    Inventors: Oleg A. Mukhanov, Alexander F. Kirichenko, Igor V. Vernik, Ivan P. Nevirkovets, Alan M. Kadin
  • Patent number: 10424727
    Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael C. Gaidis, Janusz J. Nowak, Daniel C. Worledge
  • Patent number: 10418082
    Abstract: Data is stored in a multi-level MRAM (MLC MRAM) cell in a manner that reduces transition states that require high energy. A new data block is received, and the new data block is divided into one or more sub-groups of bits, with each sub-group comprising at least two bits. Each sub-group is assigned data bit locations in a memory store. The received bits are compared with sub-groups present at the data bit locations to determine subgroups of hot bits. For each subgroup of hot bits, an encoding flag value is determined by XORing their most significant bits. The most significant bits of each subgroup of hot bits are complemented and the encoding flag is SET. A data block is generated to establish a data group for each subgroup of hot bits including the subgroup of hot bits and the encoding flag for that subgroup.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: September 17, 2019
    Assignee: Kuwait University
    Inventors: Imtiaz Ahmad, Mahmoud Imdoukh, Mohammad G H. Alfailakawi
  • Patent number: 10410709
    Abstract: Methods, systems, and devices for operating an electronic memory apparatus are described. A logic value stored in a ferroelectric random access memory (FeRAM) cell is read onto a first sensing node of a sense amplifier. The reading is performed through a digit line coupling the FeRAM cell to the first sensing node, while the sense amplifier is in an inactive state. A second sensing node of the sense amplifier is biased to a reference voltage provided by a reference voltage source. The biasing is performed while reading the logic value stored in the FeRAM cell onto the first sensing node. The digit line is isolated from the first sensing node after the reading. The sense amplifier is activated, after isolating the digit line from the first sensing node, to amplify and sense a voltage difference between the first sensing node and the second sensing node.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Vimercati, Duane R. Mills
  • Patent number: 10325640
    Abstract: According to one embodiment, a memory device includes: a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers; and a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a current pulse to the magnetoresistive element. A first pulse pattern used in the first writing is different from a second pulse pattern used in the second writing.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: June 18, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya Kishi, Tsuneo Inaba, Daisuke Watanabe, Masahiko Nakayama, Nobuyuki Ogata, Masaru Toko, Hisanori Aikawa, Jyunichi Ozeki, Toshihiko Nagase, Young Min Eeh, Kazuya Sawada
  • Patent number: 10319903
    Abstract: Some embodiments include a magnetic tunnel junction device having a first magnetic electrode, a second magnetic electrode, and a tunnel insulator material between the first and second magnetic electrodes. A tungsten-containing material is directly against one of the magnetic electrodes. In some embodiments the tungsten-containing material may be in a first crystalline lattice arrangement, and the directly adjacent magnetic electrode may be in a second crystalline lattice arrangement different from said first crystalline lattice arrangement. In some embodiments the tungsten-containing material, the first magnetic electrode, the tunnel insulator material and the second magnetic electrode all comprise a common crystalline lattice arrangement.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Sumeet C. Pandey
  • Patent number: 10311932
    Abstract: According to one embodiment, a magnetic memory device includes a magnetic portion, a first magnetic layer, a first nonmagnetic layer, a first element portion, first to third interconnects, and a controller. In a first operation, the controller sets the first interconnect to a first potential, the second interconnect to a second potential, and the third interconnect to a third potential. An absolute value of a difference between the second potential and the third potential is greater than that between the first potential and the third potential. In a second operation, the controller sets the first interconnect to a fourth potential, the second interconnect to a fifth potential, and the third interconnect to a sixth potential. An absolute value of a difference between the fifth potential and the sixth potential is less than that between the fourth potential and the sixth potential.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Nobuyuki Umetsu, Tsuyoshi Kondo, Yasuaki Ootera, Takuya Shimada, Michael Arnaud Quinsat, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Tomoya Sanuki, Yoshihiro Ueda, Yuichi Ito, Shinji Miyano, Hideaki Aochi, Yasuhito Yoshimizu
  • Patent number: 10276781
    Abstract: Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one magnetic region (e.g., a free region or a fixed region) configured to exhibit a vertical magnetic orientation, at least one oxide-based region, which may be a tunnel junction region or an oxide capping region, and at least one magnetic interface region, which may comprise or consist of iron (Fe). In some embodiments, the magnetic interface region is spaced from at least one oxide-based region by a magnetic region. The presence of the magnetic interface region enhances the perpendicular magnetic anisotropy (PMA) strength of the magnetic cell core. In some embodiments, the PMA strength may be enhanced more than 50% compared to that of the same magnetic cell core structure lacking the magnetic interface region.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wei Chen, Sunil Murthy, Witold Kula
  • Patent number: 10263037
    Abstract: An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 16, 2019
    Assignee: SK hynix Inc.
    Inventors: Jae-Yun Yi, Dong-Joon Kim
  • Patent number: 10249364
    Abstract: Higher word line voltages facilitate write operations in spin-torque magnetic memory devices, but overdriving the gate of a selection transistor with such higher word line voltages can damage the selection transistor if the gate-to-source voltage for the selection transistor is too high. Therefore in order to support the word line voltage needed on the gate of the select transistor for an up-current write operation without exceeding limits on the gate-to-source voltage for the select transistor, the gate of the selection transistor can be driven in a two-step process. The gate of the selection transistor is first driven to a lower voltage within the limits of the gate-to-source voltage for the transistor when the source of the transistor is grounded or at a voltage near ground. A voltage is then applied across the memory cell, which results in the source of the selection transistor being raised above its initial ground or near-ground state.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: April 2, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Yaojun Zhang
  • Patent number: 10236048
    Abstract: Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes an in-plane polarization magnetic layer and a perpendicular MTJ in conjugation with a programming current pulse that comprises an alternating perturbation frequency.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 19, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Michail Tzoufras, Marcin Jan Gajek, Kadriye Deniz Bozdag, Mourad El Baraji
  • Patent number: 10230043
    Abstract: Memory devices and methods of forming the same include forming a memory stack over a bottom electrode. The memory stack has a fixed magnetic layer, a tunnel barrier layer on the fixed magnetic layer, and a free magnetic layer formed on the tunnel barrier layer. A boron-segregating layer is formed directly on the free magnetic layer. The memory stack is etched into a pillar. A top electrode is formed over the pillar.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 12, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS, CO., LTD.
    Inventors: Guohan Hu, Younghyun Kim, Chandrasekara Kothandaraman, Jeong-Heon Park
  • Patent number: 10210920
    Abstract: Magnetic tunnel junction (MTJ) devices with varied breakdown voltages in different memory arrays fabricated in a same semiconductor die to facilitate different memory applications are disclosed. In exemplary aspects disclosed herein, MTJ devices are fabricated in a semiconductor die to provide at least two different memory arrays. MTJ devices in each memory array are fabricated to have different breakdown voltages. For example, it may be desired to fabricate a One-Time-Programmable (OTP) memory array in the semiconductor die using MTJ devices having a first, lower breakdown voltage, and a separate magneto-resistive random access memory (MRAM) in a same semiconductor die with MTJ devices having a higher breakdown voltage. Thus, in this example, lower breakdown voltage MTJ devices in OTP memory array require less voltage to program, while higher breakdown voltage MTJ devices in MRAM can maintain a desired write operation margin to avoid or reduce write operations causing dielectric breakdown.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: February 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Wei-Chuan Chen, Xia Li, Wah Nam Hsu, Seung Hyuk Kang
  • Patent number: 10186317
    Abstract: A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: January 22, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Maurizio Francesco Perroni, Carmelo Paolino, Salvatore Polizzi
  • Patent number: 10170688
    Abstract: Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Joel D. Chudow, Daniel C. Worledge
  • Patent number: 10164172
    Abstract: Provided are a multi-layered magnetic thin film stack, a magnetic tunneling junction, and a data storage device. The multi-layered magnetic thin film stack includes a FePd alloy layer including an alloy of iron (Fe) and palladium (Pd); a tunneling barrier layer, which includes MgO and is disposed on the FePd alloy layer; and a Heusler alloy layer disposed between the FePd alloy layer and the tunneling barrier layer, wherein the FePd alloy layer and the Heusler alloy layer constitute a hybrid magnetic layer.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: December 25, 2018
    Assignees: SK HYNIX INC., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Jongill Hong, Taejin Bae, Sung Joon Yoon
  • Patent number: 10153017
    Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell that includes an MTJ memory element coupled to a two-terminal selector element in series. The method includes the steps of raising a cell voltage across the memory cell above a threshold voltage for the selector element to become conductive; decreasing the cell voltage to a first sensing voltage and measuring a first sensing current passing through the memory cell, the selector element being nominally conductive irrespective of the resistance state of the MTJ memory element at the first sensing voltage; and further decreasing the cell voltage to a second sensing voltage and measuring a second sensing current, the selector element being nominally conductive if the MTJ memory element is in the low resistance state or nominally insulative if the MTJ memory element is in the high resistance state at the second sensing voltage.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: December 11, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Hongxin Yang, Xiaobin Wang, Jing Zhang, Xiaojie Hao, Zihui Wang, Kimihiro Satoh
  • Patent number: RE47975
    Abstract: An STTMRAM element includes a magnetic tunnel junction (MTJ) having a perpendicular magnetic orientation. The MTJ includes a barrier layer, a free layer formed on top of the barrier layer and having a magnetic orientation that is perpendicular and switchable relative to the magnetic orientation of the fixed layer. The magnetic orientation of the free layer switches when electrical current flows through the STTMRAM element. A switching-enhancing layer (SEL), separated from the free layer by a spacer layer, is formed on top of the free layer and has an in-plane magnetic orientation and generates magneto-static fields onto the free layer, causing the magnetic moments of the outer edges of the free layer to tilt with an in-plane component while minimally disturbing the magnetic moment at the center of the free layer to ease the switching of the free layer and to reduce the threshold voltage/current.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 5, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Jing Zhang, Yiming Huai, Rajiv Yadav Ranjan, Yuchen Zhou, Zihui Wang, Xiaojie Hao