Multiple Magnetic Storage Layers Patents (Class 365/173)
  • Patent number: 11776604
    Abstract: A magnetic recording array includes a plurality of units. Each unit has a first magnetoresistance effect element, second magnetoresistance effect element, and writing transistor. Each of the first magnetoresistance effect element and the second magnetoresistance effect element has a wiring and a laminate which is laminated on the wiring. The writing transistor is connected to each of the wiring of the first magnetoresistance effect element and the wiring of the second magnetoresistance effect element. The wiring of the first magnetoresistance effect element and the wiring of the second magnetoresistance effect element are electrically connected in series at the time of writing, and a writing current flows through each of the wirings. A direction of a writing current flowing in the wiring of the first magnetoresistance effect element and a direction of a writing current flowing in the wiring of the second magnetoresistance effect element are opposite to each other.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: October 3, 2023
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 11651808
    Abstract: A semiconductor memory device includes a memory cell including a switching element and a resistance change element. A first circuit supplies a constant current to the memory cell for an amount of time and a second circuit applies a constant voltage to the memory cell for an amount of time. The semiconductor memory device places the memory cell into an ON state by applying, while applying a first current to the memory cell by the first circuit, a first voltage to the memory cell by the second circuit and performs readout on the memory cell in the ON state by the first current.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: May 16, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Ryousuke Takizawa
  • Patent number: 11599299
    Abstract: Some embodiments provide a three-dimensional (3D) circuit that has data lines of one or more memory circuits on a different IC die than the IC die(s) on which the memory blocks of the memory circuit(s) are defined. In some embodiments, the 3D circuit includes a first IC die with a first set of two or more memory blocks that have a first set of data lines. The 3D circuit also includes a second IC die that is stacked with the first IC dies and that includes a second set of two or more memory blocks with a second set of data lines. The 3D circuit further includes a third IC die that is stacked with the first and second IC dies and that includes a third set of data lines, which connect through several z-axis connections with the first and second sets of data lines to carry data to and from the first and second memory block sets when data is being written to and read from the first and second memory block sets.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 7, 2023
    Assignee: Invensas LLC
    Inventors: Javier A. DeLaCruz, David E. Fisch
  • Patent number: 11502091
    Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: November 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11481191
    Abstract: According to one embodiment, an arithmetic device includes a first computational circuit including a first string, the first string having a first magnetoresistive effect element on a first conducting layer; a second computational circuit including a second strings, the second string having second magnetoresistive effect element on a second conducting layer; a third computational circuit executing computational processing using a first signal from the first computational circuit and a second signal from the second computational circuit; and a control circuit. The control circuit sets a condition on write operations with respect to at least one of the first and second magnetoresistive effect elements, based on information related to write error in at least one of the first and second magnetoresistive effect elements.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 25, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazutaka Ikegami, Shinobu Fujita
  • Patent number: 11367832
    Abstract: A method of making a magnetoresistive random access memory (MRAM) device includes forming a bottom conductive layer. The method includes forming an anti-ferromagnetic layer over the bottom conductive layer and forming a tunnel layer over the anti-ferromagnetic layer. The method includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer, wherein the anti-ferromagnetic layer, the tunnel layer and the free magnetic layer are part of a magnetic tunnel junction (MTJ) unit. The method includes forming a top conductive layer over the free magnetic layer. The method includes performing at least one lithographic process to remove portions of the bottom conductive layer, the MTJ unit and the top conductive layer that is uncovered by a photoresist layer. The method includes removing a portion of a sidewall of the MTJ unit.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 11355699
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic layer in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer is constructed with a material having a face centered cubic crystal structure, such as permalloy.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: June 7, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Mustafa Pinarbasi, Bartlomiej Adam Kardasz
  • Patent number: 11309334
    Abstract: A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC c
    Type: Grant
    Filed: November 22, 2020
    Date of Patent: April 19, 2022
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 11302864
    Abstract: A device is provided that includes a semiconductor substrate on which a free magnetic element is positioned, which has first and second magnetic domains separated by a domain wall. A first magnet is positioned on the substrate near a first end of the free magnetic element, and has a first polarity and a first value of coercivity. A second magnet is positioned on the substrate near a second end of the free magnetic element, and has a second polarity, antiparallel relative to the first polarity, and a second value of coercivity different from the first value of coercivity.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mingyuan Song, Chwen Yu, Shy-Jay Lin
  • Patent number: 11271149
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic structure in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer a first and second precessional spin current ferromagnetic layer separated by a nonmagnetic precessional spin current insertion layer.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 8, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Bartlomiej Adam Kardasz, Mustafa Michael Pinarbasi
  • Patent number: 11169226
    Abstract: The present disclosure generally relates to a Wheatstone bridge that has four resistors. Each resistor includes a plurality of TMR structures. Two resistors have identical TMR structures. The remaining two resistors also have identical TMR structures, though the TMR structures are different from the other two resistors. Additionally, the two resistors that have identical TMR structures have a different amount of TMR structures as compared to the remaining two resistors that have identical TMR structures. Therefore, the working bias field for the Wheatstone bridge is non-zero.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: November 9, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yung-Hung Wang, Chih-Ching Hu, Carlos Corona
  • Patent number: 11139389
    Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A Young
  • Patent number: 11121311
    Abstract: A magnetic tunnel junction (MTJ) containing device is provided in which a conformal dielectric encapsulation liner is located on a sidewall of each of a MTJ pillar and an overlying top electrode, and a non-conformal dielectric encapsulation liner is located on the conformal dielectric encapsulation liner. This dual encapsulation liner structure prevents the bottom electrode of the MTJ containing device from being physically exposed thus eliminating the possibility that the bottom electrode can be a source of resputtered conductive metal particles that can deposit on a sidewall of the MTJ pillar. As such, electrical shorting is reduced in the MTJ containing device of the present application. Also, the dual encapsulation liner structure can mitigate chemical diffusion into the tunnel barrier material of the MTJ pillar.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nathan P. Marchack, Bruce B. Doris, Pouya Hashemi
  • Patent number: 11114608
    Abstract: Spin-Hall (SH) material is provided near free regions of magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SH material injects spin current into the free regions such that spin torque is applied to the free regions. The spin torque generated from SH material can be used to switch the free region or to act as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction, in order to improve the reliability, endurance, or both of the magnetoresistive device. Further, one or more additional regions or manufacturing steps may improve the switching efficiency and the thermal stability of magnetoresistive devices.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 7, 2021
    Assignee: Everspin Technologies Inc.
    Inventors: Jijun Sun, Shimon, Han-Jong Chia
  • Patent number: 11116081
    Abstract: An inductor comprises a planar laminated magnetic core and a conductive winding. The core includes an alternating sequence of (a) a magnetic layer having a thickness of about 100 angstroms to about 10,000 angstroms and (b) a non-magnetic layer having a thickness of about 10 angstroms to about 2,000 angstroms. Magnetic flux passes through a first magnetic layer parallel to a first easy axis of magnetization of the first magnetic layer and the magnetic flux passes through a second magnetic layer, disposed adjacent to the first magnetic layer, parallel to a second easy axis of magnetization of the second magnetic layer. The magnetic flux path extends through the first and second magnetic layers parallel to the first and second easy axes of magnetization, respectively. At least one orthogonal magnetic layer can be disposed laterally from the core such that the magnetic flux path extends through the orthogonal magnetic layer(s).
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: September 7, 2021
    Assignee: Ferric Inc.
    Inventors: Noah Sturcken, Ryan Davies, Michael Lekas
  • Patent number: 11088320
    Abstract: A process flow for forming magnetic tunnel junction (MTJ) cells with a critical dimension CD?60 nm by using a top electrode (TE) hard mask having a thickness?100 nm prior to MTJ etching is disclosed. A carbon hard mask (HM), silicon HM, and photoresist are sequentially formed on a MTJ stack of layers. A pattern of openings in the photoresist is transferred through the Si HM with a first reactive ion etch (RIE), and through the carbon HM with a second RIE. After TE material is deposited to fill the openings, a chemical mechanical process is performed to remove all layers above the carbon HM. The carbon HM is stripped and the resulting TE pillars are trimmed to a CD?60 nm while maintaining a thickness proximate to 100 nm. Thereafter, an etch process forms MTJ cells while TE thickness is maintained at ?70 nm.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Zhongjian Teng, Jesmin Haq, Yu-Jen Wang
  • Patent number: 11022662
    Abstract: A three-axis magnetic sensor which is not physically separated from each other and made of one element is provided. A spin-orbit torque is generated through an interface junction between a magnetization seed layer and a magnetization free layer, and through this, a change in an in-plane magnetic field may be sensed in the form of current or voltage in the magnetization seed layer. Further, a tunneling insulating layer and a magnetization pinned layer are formed on the magnetization free layer. The formed structure induces a tunnel magneto-resistance phenomenon. Through this, a change in a magnetic field in a vertical direction is sensed.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 1, 2021
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jin Pyo Hong, Seung Mo Yang, Hae Soo Park
  • Patent number: 11002807
    Abstract: A magnetoresistance element deposited upon a substrate includes a first stack portion having opposing first and second surfaces and including a first plurality of layers. The first stack portion has a first substantially linear response corresponding to an applied magnetic field over a first magnetic field strength range. The magnetoresistance element also includes a second stack portion having opposing first and second surfaces and including a second plurality of layers. The first surface of the second stack portion is disposed over the second surface of the first stack portion and the second stack portion has a second substantially linear response that is different than the first substantially linear response. The second substantially linear response corresponds to the applied magnetic field over a second magnetic field strength range.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: May 11, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Paolo Campiglio, Jeffrey Eagen
  • Patent number: 10923199
    Abstract: An electronic device comprises a multi-chip package including multiple memory dice that include a memory array, charging circuitry, polling circuitry and a control unit. The charging circuitry is configured to perform one or more memory events in a high current mode using a high current level or in a low current mode using a lower current level. The polling circuitry is configured to poll a power status node common to the multiple memory dice to determine availability of the high current mode. The control unit is configured to operate the charging circuitry in the high current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is available, and operate the charging circuitry in the low current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is unavailable.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo, Kalyan Kavalipurapu
  • Patent number: 10876839
    Abstract: A magnetic tunnel junction (MTJ) based sensor device includes a MTJ element and processing circuitry. The MTJ element includes a free layer, a pinned layer, and a tunnel barrier, the tunnel barrier being arranged above the pinned layer, wherein the free layer is adapted to flex away from the tunnel barrier during gyroscopic motion. The processing circuitry is configured to measure a resistance at the MTJ element and determine gyroscopic motion based on the resistance at the MTJ element.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 29, 2020
    Assignee: Honeywell International Inc.
    Inventor: Romney R. Katti
  • Patent number: 10878870
    Abstract: The various implementations described herein include magnetic memory devices and systems, and methods for propagating defects in the devices and systems. In one aspect, a magnetic memory device comprises a non-magnetic cylindrical core configured to receive a current, a plurality of magnetic layers surrounding the core, and a plurality of non-magnetic layers also surrounding the core. The magnetic layers and the non-magnetic layers are arranged in a stack coaxial with the core. Respective magnetic layers of the plurality of magnetic layers are separated by respective non-magnetic layers of the plurality of non-magnetic layers. The device further comprises an input terminal coupled to a first end of the core and a current source coupled to the input terminal. The current source is configured to supply current imparting a Spin Hall Effect (SHE) around the circumference of the core, and the SHE contributes to a magnetization of the magnetic layers.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 29, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Michail Tzoufras, Marcin Gajek
  • Patent number: 10861522
    Abstract: Provided is a storage device that includes a magnetization fixed layer, an intermediate layer, and a storage layer. The magnetization fixed layer has magnetization in an orientation perpendicular to a film surface and a constant magnetization direction. The intermediate layer includes a non-magnetic body and is disposed on the magnetization fixed layer. The storage layer includes an outer circumferential portion and a center portion. The storage layer is disposed to face the magnetization fixed layer with the intermediate layer sandwiched therebetween, and is configured to have a variable magnetization direction. The outer circumferential portion has magnetization in an orientation perpendicular to a film surface, the center portion is formed by being surrounded by the outer circumferential portion and having magnetization inclined from the orientation perpendicular to the film surface.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 8, 2020
    Assignee: SONY CORPORATION
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 10852369
    Abstract: A magnetoresistive sensor has a sensor plane in which the magnetoresistive sensor is sensitive to a magnetic field. The magnetoresistive sensor includes a reference layer having a reference magnetization that is fixed and that is aligned with an in-plane axis of the sensor plane; and a magnetic free layer disposed proximate to the reference layer, the magnetic free layer having a free layer magnetization aligned along an out-of-plane axis that is out-of-plane to the sensor plane. The free layer magnetization is configured to tilt away from the out-of-plane axis and towards the sensor plane in a presence of an external in-plane magnetic field.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: December 1, 2020
    Inventors: Wolfgang Raberg, Clemens Muehlenhoff, Juergen Zimmer
  • Patent number: 10825984
    Abstract: Structures for a sensor and methods of forming such structures. A sensing element includes a free magnetic layer, a pinned magnetic layer, and a non-magnetic conductive spacer layer between the free magnetic layer and the pinned magnetic layer. A dummy element is positioned outside of an outer boundary of the sensing element. The dummy element is detached from the sensing element.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 3, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ping Zheng, Eng Huat Toh, Samarth Agarwal, Lanxiang Wang, Shyue Seng Tan, Ruchil Kumar Jain
  • Patent number: 10672420
    Abstract: The present technology relates to a storage device that realizes both a high information retention property and a low power consumption. A storage device includes a fixed layer, a storage layer, an intermediate layer, and a heat generation layer. The fixed layer includes a first ferromagnetic layer that includes a fixed perpendicular magnetization. The storage layer includes a second ferromagnetic layer that includes a perpendicular magnetization invertible by a spin injection. The intermediate layer is formed of an insulator and is arranged between the storage layer and the fixed layer. The heat generation layer is formed of a resistance heating element and is arranged in at least one of the storage layer and the fixed layer. With this configuration, it becomes possible to provide a storage device that realizes both a high information retention property and a low power consumption.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: June 2, 2020
    Assignee: Sony Corporation
    Inventors: Kazutaka Yamane, Hiroyuki Uchida, Yutaka Higo, Hiroyuki Ohmori, Kazuhiro Bessho, Masanori Hosomi
  • Patent number: 10672448
    Abstract: According to an embodiment, a magnetic storage device includes a memory unit, a current supply circuit, a switch, and a controller. The memory unit includes a magnetic member and a switch element. The switch element is connected in series to the magnetic member, and changes to an on state in a case where a voltage equal to or larger than a predetermined value is applied in an off state. The current supply circuit supplies a current to the memory unit. The switch electrically connects or disconnects the current supply circuit and the memory unit. The controller applies a voltage for changing the switch element from the off state to the on state to the memory unit with the switch in a disconnected state, and sets the switch to be in a connected state after the switch element changes to the on state.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: June 2, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshihiro Ueda
  • Patent number: 10650937
    Abstract: Various examples are provided for superlattice conductors. In one example, a planar conductor includes a plurality of stacked layers including copper thin film layers and nickel thin film layers, where adjacent copper thin film layers of the copper thin film layers are separated by a nickel thin film layer of the plurality of nickel thin film layers. In another example, a conductor includes a plurality of radially distributed layers including a non-ferromagnetic core; a nickel layer disposed about and encircling the non-ferromagnetic core; and a copper layer disposed on and encircling the nickel layer. In another example, a hybrid conductor includes a core; and a plurality of radially distributed layers disposed about a portion of an outer surface of the core, the plurality of radially distributed layers include alternating ferromagnetic and non-ferromagnetic layers. In other hybrid conductors, the radially distributed layers can utilize magnetic and non-magnetic materials.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 12, 2020
    Assignee: THE UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC
    Inventor: Yong-Kyu Yoon
  • Patent number: 10620279
    Abstract: A magnetoresistance element deposited upon a substrate includes a first stack portion having opposing first and second surfaces and including a first plurality of layers. The first stack portion has a first substantially linear response corresponding to an applied magnetic field over a first magnetic field strength range. The magnetoresistance element also includes a second stack portion having opposing first and second surfaces and including a second plurality of layers. The first surface of the second stack portion is disposed over the second surface of the first stack portion and the second stack portion has a second substantially linear response that is different than the first substantially linear response. The second substantially linear response corresponds to the applied magnetic field over a second magnetic field strength range.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: April 14, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Paolo Campiglio, Jeffrey Eagen
  • Patent number: 10608309
    Abstract: A magnetoresistance effect device includes a first port, a second port, a magnetoresistance effect element, a first signal line that is connected to the first port and applies a high-frequency magnetic field to the magnetoresistance effect element, a second signal line that connects the second port to the magnetoresistance effect element, and a direct current application terminal that is connected to a power source configured to apply a direct current or a direct voltage in a lamination direction of the magnetoresistance effect element. The first signal line includes a plurality of high-frequency magnetic field application areas capable of applying a high-frequency magnetic field to the magnetoresistance effect element, and the plurality of high-frequency magnetic field application areas in the first signal line are disposed at positions at which high-frequency magnetic fields generated in the high-frequency magnetic field application areas reinforce each other in the magnetoresistance effect element.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: March 31, 2020
    Assignee: TDK CORPORATION
    Inventors: Takekazu Yamane, Junichiro Urabe, Tsuyoshi Suzuki, Atsushi Shimura
  • Patent number: 10580491
    Abstract: A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: March 3, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Vipin Tiwari, Hieu Van Tran, Nhan Do, Mark Reiten
  • Patent number: 10536281
    Abstract: A magnetic random access memory (MRAM) physically unclonable function (PUF) device that uses the geometric variations in magnetic memory cells to generate a random PUF response is described herein. Within the MRAM, one or more magnetic memory cells can be used for the PUF. The PUF response is generated by destabilizing the one or more magnetic memory cells and then allowing them to relax. The MRAM PUF has also a relatively small footprint among all other silicon PUFs. Timing and control signals for the MRAM PUF are also described along with power and delay characteristics for use with field and spin transfer torque driven destabilization operations.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: January 14, 2020
    Assignee: University of South Florida
    Inventors: Jayita Das, Kevin P. Scott, Drew H. Burgett, Srinath Rajaram, Sanjukta Bhanja
  • Patent number: 10516103
    Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 24, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Jijun Sun, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine, Frederick Mancoff
  • Patent number: 10483455
    Abstract: An embodiment includes a magnetic tunnel junction (MTJ) having a non-elliptical free layer with rounded corners. For example, an embodiment includes a MTJ including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; wherein the free magnetic layer includes a top surface, a bottom surface, and a sidewall circumnavigating the free magnetic layer and coupling the bottom surface to the top surface; wherein the top surface is rectangular with a plurality of rounded corners. In an embodiment, the aspect ratio of the top surface is between 4:1 and 8:1 (length to width). Such an embodiment provides ease of manufacture along with accept critical switching current (to reverse polarity of the free layer) and stability. Other embodiments are described herein.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, Ian A. Young
  • Patent number: 10475991
    Abstract: A process flow for forming magnetic tunnel junction (MTJ) cells with a critical dimension CD?60 nm by using a top electrode (TE) hard mask having a thickness ?100 nm prior to MTJ etching is disclosed. A carbon hard mask (HM), silicon HM, and photoresist are sequentially formed on a MTJ stack of layers. A pattern of openings in the photoresist is transferred through the Si HM with a first reactive ion etch (RIE), and through the carbon HM with a second RIE. After TE material is deposited to fill the openings, a chemical mechanical process is performed to remove all layers above the carbon HM. The carbon HM is stripped and the resulting TE pillars are trimmed to a CD?60 nm while maintaining a thickness proximate to 100 nm. Thereafter, an etch process forms MTJ cells while TE thickness is maintained at ?70 nm.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Yang, Zhongjian Teng, Jesmin Haq, Yu-Jen Wang
  • Patent number: 10446176
    Abstract: A lateral spin valve reader includes a detector located proximate to a bearing surface of the reader, and a spin injector located away from the bearing surface. The lateral spin valve reader also includes a channel that extends from the detector to the spin injector. The channel includes a two-dimensional semiconducting layer that extends from the detector to the spin injector.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: October 15, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: David A. Deen, Thomas Roy Boonstra
  • Patent number: 10438841
    Abstract: Amorphous multi-component metallic films can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors. Interfacial properties of AMMFs are superior to those of crystalline metal films, and therefore electric fields at the interface of an AMMF and an oxide film are more uniform. An AMMF resistor (AMNR) can be constructed as a three-layer structure including an amorphous metal, a tunneling insulator, and a crystalline metal layer. By modifying the order of the materials, the patterns of the electrodes, and the size and number of overlap areas, the I-V performance characteristics of the AMNR are adjusted. A non-coplanar AMNR has a five-layer structure that includes three metal layers separated by metal oxide tunneling insulator layers, wherein an amorphous metal thin film material is used to fabricate the middle electrodes.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: October 8, 2019
    Assignee: AMORPHYX, INC.
    Inventor: Sean William Muir
  • Patent number: 10354730
    Abstract: Some embodiments include apparatuses and methods using a substrate, a first memory cell block including first memory cell strings located over the substrate, first data lines coupled to the first memory cell strings, a second memory cell block including second memory cell strings located over the first memory cell block, second data lines coupled to the second memory cell strings, first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus, and second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry. No conductive path of the first and second conductive paths is shared by the first and second memory cell blocks.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 10304509
    Abstract: According to an embodiment, a magnetic storage device includes a memory cell including a magnetoresistive element, a selector, a first end, and a second end. The magnetoresistive element includes a first ferromagnetic layer, a second ferromagnetic layer, a third ferromagnetic layer, a first nonmagnetic layer disposed between the first ferromagnetic layer and the second ferromagnetic layer, and a second nonmagnetic layer disposed between the second ferromagnetic layer and the third ferromagnetic layer to couple the second ferromagnetic layer with the third ferromagnetic layer in an antiferromagnetic manner. The first ferromagnetic layer has a film thickness larger than a film thickness of the second ferromagnetic layer.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: May 28, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masatoshi Yoshikawa, Kuniaki Sugiura
  • Patent number: 10170162
    Abstract: A calibration circuit coupled to a sense amplifier circuit may be configured to determine a response time of the sense amplifier circuit relative to a pulse sequence. Based on the determined response time, the calibration circuit may be configured to set a level of a biasing current to a desired level in order to control the response time of the sense amplifier circuit.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: January 1, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Ali Al-Shamma, Tz-yi Liu
  • Patent number: 10157656
    Abstract: A magnetic memory cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. Steering of current is provided for programming the magnetic memory cell.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 18, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Patent number: 10134979
    Abstract: A spintronic device is disclosed. The spintronic device includes a spin current transport layer, a spin injector, and a spin detector. The spin injector includes a first tunnel barrier layer made of strontium oxide (SrO) disposed over the spin current transport layer and a first magnetic material layer disposed over the first tunnel barrier layer. The spin detector includes a second tunnel barrier layer made of SrO disposed over the spin current transport layer. A second magnetic material layer is disposed over the second tunnel barrier layer and a spin sensor has a sensor input terminal coupled to the second magnetic material layer.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: November 20, 2018
    Assignee: Ohio State Innovation Foundation
    Inventors: Roland K. Kawakami, Simranjeet Singh, Jyoti Katoch
  • Patent number: 10115898
    Abstract: A Magnetoresistive Tunnel Junction (MTJ) includes a magnetic reference layer disposed between a first electrode and a resistive layer. The junction also includes a magnetic free layer disposed between the resistive layer and a second electrode. The surface area of the free layer is less than the surface area of the reference layer.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chwen Yu
  • Patent number: 10083730
    Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element having a reference layer formed from a reference layer material having a fixed magnetization direction, along with a free layer formed from a free layer material having a switchable magnetization direction. The MTJ is configured to receive a write pulse having a write-pulse and spin-transfer-torque (WP-STT) start time, a WP-STT start segment duration and a write pulse duration. The WP-STT start segment duration is less than the write pulse duration. The fixed magnetization direction is configured to form an angle between the fixed magnetization direction and the switchable magnetization direction. The angle is sufficient to generate spin torque electrons in the reference layer material at the WP-STT start time. The spin torque electrons generated in the reference layer material is sufficient to initiate switching of the switchable magnetization direction at the WP-STT start time.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel C. Worledge
  • Patent number: 10026465
    Abstract: According to one embodiment, a nonvolatile memory includes a conductive line including a first portion, a second portion and a third portion therebetween, a storage element including a first magnetic layer, a second magnetic layer and a nonmagnetic layer therebetween, and the first magnetic layer being connected to the third portion, and a circuit flowing a write current between the first and second portions, applying a first potential to the second magnetic layer, and blocking the write current flowing between the first and second portions after changing the second magnetic layer from the first potential to a second potential.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: July 17, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoaki Inokuchi, Naoharu Shimomura, Katsuhiko Koui, Yuuzo Kamiguchi, Satoshi Shirotori, Kazutaka Ikegami, Hiroaki Yoda
  • Patent number: 9997226
    Abstract: In one embodiment, a SO-STT device has a non-symmetric device geometry. The device may be fabricated to have a non-symmetric magnetic pattern by tilting a shaped magnetic pattern (e.g., an ellipse, diamond, rectangle, etc. shaped magnetic pattern) such that the pattern's main (long and short) axes are tilted with respected to an in-plane current direction. Alternatively, the non-symmetric device geometry may be produced by locating the magnetic pattern away from the center of a current injection line. The non-symmetric may permit switching absent application of an external magnetic field. A SO-STT device with non-symmetric device geometry, or another type of SO-STT device, may further integrate an additional semiconductor, insulator or metal layer into the device's multilayer stack. By integrating the additional semiconductor, insulator or metal layer, a significant reduction of SO-STT switching current density may be achieved.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: June 12, 2018
    Assignee: National University of Singapore
    Inventors: Xuepeng Qiu, William Sylvain Legrand, Hyunsoo Yang
  • Patent number: 9911483
    Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element having a reference layer formed from a reference layer material having a fixed magnetization direction, along with a free layer formed from a free layer material having a switchable magnetization direction. The MTJ is configured to receive a write pulse having a write-pulse and spin-transfer-torque (WP-STT) start time, a WP-STT start segment duration and a write pulse duration. The WP-STT start segment duration is less than the write pulse duration. The fixed magnetization direction is configured to form an angle between the fixed magnetization direction and the switchable magnetization direction. The angle is sufficient to generate spin torque electrons in the reference layer material at the WP-STT start time. The spin torque electrons generated in the reference layer material is sufficient to initiate switching of the switchable magnetization direction at the WP-STT start time.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel C. Worledge
  • Patent number: 9905282
    Abstract: Methods of fabricating a dome-shaped MTJ TE and the resulting devices are provided. Embodiments include forming a MRAM stack having a laterally separated MTJ structures and the MRAM and a logic stack each having a SiN layer; forming first trenches through the MRAM stack to a portion of the SiN layer above an MTJ structure; forming second trenches through the SiN layer fully landing on an upper portion of the MTJ structures and removing the SiN layer of the logic stack; forming a TaN layer over the MRAM and logic stack; removing portions of the TaN layer on opposite sides of the MTJ structures and therebetween; forming an oxide layer over the MRAM and logic stacks; and forming vias through the oxide layer of the MRAM stack down the TaN layer above MTJ structures and a via through the logic stack.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 27, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Soh Yun Siah, Juan Boon Tan
  • Patent number: 9899071
    Abstract: Provided is an electric-current-controllable magnetic unit, including: a substrate, an electric-current channel disposed on the substrate, the electric-current channel including a composite heavy-metal multilayer comprising at least one heavy-metal; a capping layer disposed over the electric-current channel; and at least one ferromagnetic layer disposed between the electric-current channel and the capping layer.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: February 20, 2018
    Assignee: THE JOHNS HOPKINS UNIVERSITY
    Inventors: Qinli Ma, Yufan Li, Chia-ling Chien
  • Patent number: 9887237
    Abstract: According to an embodiment, a magnetic storage device includes a semiconductor region including a trench; a gate electrode disposed in the trench; an insulation film covering the gate electrode and provided in a manner to fill the trench; and a magnetoresistive effect element including at least a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, the non-magnetic layer in a side surface of the magnetoresistive effect element including the non-magnetic layer being provided on a top surface of the insulation film.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shintaro Sakai, Keisuke Nakatsuka, Hiroyuki Kanaya, Yoshinori Kumura, Katsuyuki Fujita
  • Patent number: 9886989
    Abstract: The present disclosure concerns a magnetic random access memory (MRAM) cell suitable for performing a thermally assisted write operation or a spin torque transfer (STT) based write operation, comprising a magnetic tunnel junction comprising a top electrode; a tunnel barrier layer comprised between a first ferromagnetic layer having a first magnetization direction, and a second ferromagnetic layer having a second magnetization direction adjustable with respect to the first magnetization direction; a front-end layer; and a magnetic or metallic layer on which the second ferromagnetic layer is deposited; the second ferromagnetic layer being comprised between the front-end layer and the tunnel barrier layer and having a thickness comprised between about 0.5 nm and about 2 nm, such that magnetic tunnel junction has a magnetoresistance larger than about 100%. The MRAM cell disclosed herein has lower power consumption compared to conventional MRAM cells.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: February 6, 2018
    Assignee: CROCUS TECHNOLOGY SA
    Inventors: Clarisse Ducruet, CĂ©line Portemont, Ioan Lucian Prejbeanu