Floating Gate Patents (Class 365/185.01)
  • Patent number: 11929119
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are stacked over one another.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: March 12, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Liang Chen, Wei Liu, Yanhong Wang, Zhiliang Xia, Wenxi Zhou, Kun Zhang, Yuancheng Yang
  • Patent number: 11734178
    Abstract: A storage device includes: a memory device including a plurality of planes, and a plurality of cache buffers and data buffers; and a memory controller for controlling the memory device to transmit first data and second data from first plane and second plane into the respective first cache buffer and second cache buffer, and control the first cache buffer and the second cache buffer to transmit the first data and the second data to the memory controller. In response to a read request for third data from a host while the first data is transmitting from the first cache buffer to the memory controller, the memory controller transmits a cache read command to the memory device such that the memory device reads the third data after the first data is completely transmitted to the memory controller, before the second data is transmitted from the second cache buffer.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: August 22, 2023
    Assignee: SK hynix Inc.
    Inventor: Chung Un Na
  • Patent number: 11721377
    Abstract: A programming method for a three-dimensional ferroelectric memory device is disclosed. The programming method includes applying a first voltage on a selected word line of a target memory cell. The target memory cell has a first logic state and a second logic state corresponding to a first threshold voltage and a second threshold voltage, respectively. The first and second threshold voltages are determined by two opposite electric polarization directions of a ferroelectric film in the target memory cell. The programming method also includes applying a second voltage on a selected bit line, where a voltage difference between the first and second voltages has a magnitude larger than a coercive voltage of the ferroelectric film such that the target memory cell is switched from the first logic state to the second logic state.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: August 8, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Qiang Tang
  • Patent number: 11714575
    Abstract: A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: August 1, 2023
    Assignee: Kioxia Corporation
    Inventors: Akio Sugahara, Masahiro Yoshihara
  • Patent number: 11687450
    Abstract: A memory controller controls an address such that a number of chips included in a memory device can increase. The memory controller includes a flash translation layer configured to translate a logical block address received from a host into a physical block address, wherein the flash translation layer determines an addressing unit of at least one of a plurality of addresses in the physical block address based on a request received from the host and a command controller configured to generate a command representing the addressing unit based on the request.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: June 27, 2023
    Assignee: SK hynix Inc.
    Inventors: Beom Ju Shin, Yun Jung Yeom
  • Patent number: 11606105
    Abstract: Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: March 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jun Tao, Niang-Chu Chen
  • Patent number: 11599401
    Abstract: An information processing system, an information processing method, and a non-transitory recording medium. The information processing system receives from a device, a number of times of writing operations to one or more memories included in the device and counter information of the device, determines whether there is a malfunction or a probability of malfunction based on the number of times of writing operations received from the device, and identifies software that causes or is likely to cause the malfunction based on the counter information in response to determination of the malfunction, or the probability of malfunction.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: March 7, 2023
    Assignee: Ricoh Company, Ltd.
    Inventor: Tomoki Yoshida
  • Patent number: 11545228
    Abstract: A storage device may include a one time programmable (OTP) memory including a plurality of OTP cells and configured to store OTP key values in the plurality of OTP cells, and an erase instruction circuit that is detachably mounted on the storage device and connected to a first node of the OTP memory. When the erase instruction circuit is removed from the storage device, the OTP memory may be configured to receive the erase instruction signal having a first logic level at the first node and permanently erase all the OTP key values stored in the plurality of OTP cells by programming the plurality of OTP cells to an identical OTP key value in response to the erase instruction signal having the first logic level.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: January 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyung Seuk Kim
  • Patent number: 11508664
    Abstract: An interconnect structure may include a graphene-metal barrier on a substrate and a conductive layer on the graphene-metal barrier. The graphene-metal barrier may include a plurality of graphene layers and metal particles on grain boundaries of each graphene layer between the plurality of graphene layers. The metal particles may be formed at a ratio of 1 atom % to 10 atom % with respect to carbon of the plurality of graphene layers.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: November 22, 2022
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Keunwook Shin, Kibum Kim, Hyunmi Kim, Hyeonjin Shin, Sanghun Lee
  • Patent number: 11416175
    Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: August 16, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Tomer Tzvi Eliash, Asaf Gueta, Inon Cohen, Yuval Grossman
  • Patent number: 11398259
    Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: July 26, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Hsin Chen, Chun-Yuan Lo, Shih-Chen Wang, Tsung-Mu Lai
  • Patent number: 11386959
    Abstract: A semiconductor storage device includes a memory string and a row decoder configured to apply voltages to first to fourth select gate lines and first and second word lines connected to the memory string. A sequencer has first mode for erasing the entire memory string and a second mode for erasing just a portion of the memory string. In the first mode, a first voltage is applied to the bit line and the source line, a second voltage lower than the first voltage is applied to the first select gate line, a third voltage is applied to the second select gate line, a fourth voltage is applied to the third select gate line, a fifth voltage lower than the first voltage is applied to the fourth select gate line, and a sixth voltage lower than the first to fifth voltages is applied to the first and second word lines.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: July 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Hideto Takekida
  • Patent number: 11347581
    Abstract: Aspects of a storage device including a controller memory, a die memory, and a plurality of accumulators corresponding to individual DQs are provided for accelerated DQ training and error detection. A controller stores first data in the controller memory, transfers second data to the die memory over an n-bit bus, and receives n bits of the second data from the die memory based on a DQS. The controller then compares n bits of the first data with n bits of the second data to produce n bit results received into respective accumulators, and the controller simultaneously updates different accumulators in response to bit mismatches. During DQ training, if an accumulator value meets a mismatch threshold, the controller modifies a DQS-DQ timing accordingly. During error detection of a read scrambled page, if an accumulator value does not meet an entropy threshold, the controller identifies an error associated with the page.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: May 31, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Robert Ellis, Atif Hussain, Venugopal Garuda, Kevin O'Toole, Todd Lindberg
  • Patent number: 11335409
    Abstract: A data erasing method of a non-volatile memory and a storage device using the same are provided. The data erasing method of the non-volatile memory includes the following steps. A boost circuit is boosted to output a damage voltage. A switch is turned on to apply the damage voltage to the non-volatile memory. The switch is connected between the boost circuit and the non-volatile memory. The non-volatile memory is destroyed by the damage voltage.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 17, 2022
    Assignee: SILICON MOTION, INC.
    Inventor: Tsai-Fa Liu
  • Patent number: 11301346
    Abstract: A system includes a processing device and a memory device coupled to the processing device. The memory device can include a cyclic buffer portion and a snapshot portion. The processing device can store time based telemetric sensor data in the cyclic buffer portion, copy an amount of the telemetric sensor data from the cyclic buffer portion to the snapshot portion in response to a trigger event, operate the cyclic buffer portion with a first trim tailored to a performance target of the cyclic buffer portion, and operate the snapshot portion with a second trim tailored to a performance target of the snapshot portion.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Todd A. Marquart, Niccolo′ Righetti, Jeffrey S. McNeil, Jr., Akira Goda, Kishore K. Muchherla, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
  • Patent number: 11233148
    Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Jack T. Kavalieros, Seung Hoon Sung, Siddharth Chouksey, Harold W. Kennel, Dipanjan Basu, Ashish Agrawal, Glenn A. Glass, Tahir Ghani, Anand S. Murthy
  • Patent number: 11227924
    Abstract: A memory device is provided. The device comprises a semiconductor fin with a first gate and a second gate disposed over the semiconductor fin. A third gate is positioned over the semiconductor fin and a lower portion of the third gate is disposed between the first and second gates.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: January 18, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 11188244
    Abstract: A memory device stores data for a host. In one approach, a trim operation is initiated for the memory device (e.g., based on a context that is determined for the memory device). During the trim operation, read and/or write tests are performed on one or more portions of a non-volatile storage media of the memory device. One or more characteristics associated with the memory device are observed during the test. Based on these observed characteristics, one or more trim settings are determined. Then, the memory device is updated to store the determined trim settings to configure subsequent read or write access to the non-volatile storage media (e.g., access performed in response to commands from a host).
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Junichi Sato
  • Patent number: 11127749
    Abstract: A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: September 21, 2021
    Assignee: Key Foundry Co., Ltd.
    Inventors: Su Jin Kim, Hye Jin Yoo
  • Patent number: 11120875
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 14, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Gou Fukano
  • Patent number: 11069693
    Abstract: A method is provided for the manufacture of an integrated semiconductor device that includes an embedded flash memory array formed in a recessed region of a semiconductor substrate, the method includes, prior to formation of floating and control gate stacks of the memory array, depositing a protective layer over layers of gate material, and depositing a self-leveling sacrificial layer over the protective layer to produce a substantially planar upper surface. The sacrificial layer is then etched to a depth that removes the sacrificial layer and leaves a substantially planar face on the protective layer. A photo mask is then deposited on the protective layer and the gate stacks are etched from the layers of gate material.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Wei Cheng Wu
  • Patent number: 11056492
    Abstract: Described herein are memory arrays where some memory cells include access transistors with one front-side and one back-side source/drain (S/D) contacts. An example memory array further includes a bitline, coupled to the first S/D region of the access transistor of a first memory cell of the memory array, and a plateline, coupled to a first capacitor electrode of a storage capacitor of the first memory cell. Because the access transistor is a transistor with one front-side and one back-side S/D contacts, the bitline may be provided in a first layer, the channel material—in a second layer, and the plateline—in a third layer, where the second layer is between the first layer and the third layer, which may allow increasing the density of memory cells in a memory array, or, conversely, reducing the footprint area of a memory array with a given density of memory cells.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Mauro J. Kobrinsky, Elliot Tan, Szuya S. Liao, Tahir Ghani, Swaminathan Sivakumar, Rajesh Kumar
  • Patent number: 11011633
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 18, 2021
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 10991421
    Abstract: A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels read from the two bitcells. If these two levels are not complementary, the comparator outputs an indicator. This indicator serves as an alert that a storage error has, or may have, occurred.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: April 27, 2021
    Assignee: Bar-Ilan University
    Inventors: Robert Giterman, Lior Atias, Adam Teman, Alexander Fish
  • Patent number: 10963776
    Abstract: An artificial neuron integrated circuit including a polarizable circuit element having a first electrode, a second electrode, and a polarizable material layer disposed between the first and second electrodes, the polarizable material layer changeable between a first polarization state and a second polarization state, in response to receiving a number of voltage pulses across the first and second electrodes, the polarizable material layer to change from one of the first and second polarization states to the other of the first and second polarization states, where each of the number of voltage pulses individually is insufficient to change the polarization state.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: March 30, 2021
    Assignee: NaMLab gGmbH
    Inventors: Halid Mulaosmanovic, Stefan Slesazeck
  • Patent number: 10964376
    Abstract: An operating method of a nonvolatile memory apparatus includes determining a first threshold voltage of a memory cell by using a first read voltage. The method includes determining a second threshold voltage of the memory cell by using a second read voltage having a different voltage level from the first read voltage based on write data and the first threshold voltage of the memory cell. The method includes writing the write data into the memory cell based on the first and second threshold voltages of the memory cell.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: March 30, 2021
    Assignee: SK hynix Inc.
    Inventor: Ho Seok Em
  • Patent number: 10892017
    Abstract: A memory device comprises: a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: January 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Wan Nam, Yong Hyuk Choi, Jun Yong Park, Jung No Im
  • Patent number: 10797073
    Abstract: According to one embodiment, a memory system includes: a semiconductor memory device; and a controller. The semiconductor memory device includes: first interconnection layers; second interconnection layers; a semiconductor pillar. The semiconductor memory device executes an operation in a first mode or in a second mode. In the first mode, the device selects a third interconnection layer among the first interconnection layers independently with a fourth interconnection layer among the second interconnection layers. In the second mode, the device selects a fifth interconnection layer among the first interconnection layers and sixth interconnection layer among the second interconnection layers in a batch. The controller sends an instruction to the device to execute the operation in the first mode or the second mode.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 6, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 10797065
    Abstract: A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 6, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshitake Yaegashi
  • Patent number: 10790390
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: September 29, 2020
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 10777281
    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a first pillar extending through the first group of conductive materials and the first group of dielectric materials, memory cells located along the first pillar, a conductive contact coupled to one of the conductive materials, and a second pillar extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, and a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion has a doping concentration less than a doping concentration of each of the first and fourth portions.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Guangyu Huang, Haitao Liu, Akira Goda
  • Patent number: 10725856
    Abstract: An example apparatus for error correction can include an array of memory cells and a controller. The controller can be configured to perform a dummy read on a portion of data stored in the array. The dummy read can include sending a portion of data on output buffers to a host. The controller can be configured to error correct the portion of data in the host. The controller can be configured to write the portion of data back to the array.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Ivan Ivanov
  • Patent number: 10678768
    Abstract: Systems, apparatuses and methods may store data. A system may include a processor communicatively coupled to an indexing structure and a datastore log separate from the indexing structure. The indexing structure may store key data corresponding to a key of a key-value pair and an address for the key-value pair. The datastore log may store the key-value pair at the address in a logical band of a plurality of independent logical bands. In addition, the system may include a memory device coupled to the processor. The memory device may include instructions, which when executed by the processor, may cause the system to execute an operation involving the key-value pair.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Peng Li, Sanjeev Trika
  • Patent number: 10680600
    Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: June 9, 2020
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George Imthurn, Mark L. Burgener, Robert B. Welstand
  • Patent number: 10630286
    Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: April 21, 2020
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George Imthurn, Mark L. Burgener, Robert B. Welstand
  • Patent number: 10622990
    Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: April 14, 2020
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George Imthurn, Mark L. Burgener, Robert B. Welstand
  • Patent number: 10580493
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 3, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Gou Fukano
  • Patent number: 10554227
    Abstract: A memory system configured to decode a data set may pause a convergence process to update reliability metric values. The memory system may utilize a positive feedback system that updates the reliability metric values by analyzing current a posteriori reliability metric values to calculate average estimated reliability characteristic values associated with a memory error model. The updates to the reliability metric values may provide increased error correction capability and faster decoding.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Alexander Bazarsky, Ariel Navon, Omer Fainzilber
  • Patent number: 10529402
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. For example, a digit line that is in electronic communication with a ferroelectric capacitor may be virtually grounded while a voltage is applied to a plate of the ferroelectric capacitor, and the ferroelectric capacitor may be isolated from the virtual ground after a threshold associated with applying the voltage to the plate is reached. A switching component (e.g., a transistor) that is in electronic communication with the digit line and virtual ground may be activated to virtually ground the digit line and deactivated to isolate the digit line from virtual ground.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christopher John Kawamura, Scott James Derner
  • Patent number: 10510767
    Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Chi Wu, Cheng-Bo Shu, Chien Hung Liu
  • Patent number: 10503431
    Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: December 10, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Sergey Anatolievich Gorobets, Neil Richard Darragh, Liam Michael Parker
  • Patent number: 10475490
    Abstract: A memory device includes memory cells and a refresh module. The memory cells are coupled to a bit line, in which at least one memory cell of the memory cells is configured to store predetermined data. The refresh module is configured to refresh the at least one memory cell if a target memory cell of the memory cells is programmed or erased, in order to keep at least one cell current of the at least one memory cell away from a predetermined verify current level.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yue-Der Chih, Cheng-Hsiung Kuo, Gu-Huan Li, Chien-Yin Liu
  • Patent number: 10468107
    Abstract: Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sau Ching Wong
  • Patent number: 10459793
    Abstract: A data storage device may include a non-volatile memory array and a controller. The non-volatile memory array may include a plurality of dies. Each die of the plurality of data dies may include a plurality of words, where a word is an access unit of a die. The controller may be configured to store user data to a respective first word of at least a first die and a second die of the plurality of data dies. A page of user data may include the user data stored at the respective first words of the at least first die and second die. The controller may also be configured to store parity data to a first portion of a first word of a third die. The controller may be further configured to store metadata to a second portion of the first word of the third die.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 29, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zvonimir Z. Bandic, Kiran Kumar Gunnam, Seung-Hwan Song
  • Patent number: 10446258
    Abstract: Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Giovanni Santin, Maria-Luisa Gallese, Luigi Pilolli
  • Patent number: 10438683
    Abstract: A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 8, 2019
    Assignee: Apple Inc.
    Inventors: Barak Sagiv, Einav Yogev, Eli Yazovitsky, Eyal Gurgi, Roi Solomon
  • Patent number: 10431298
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Patent number: 10361211
    Abstract: A semiconductor device, includes: a semiconductor substrate having a first well region; an insulating layer formed on a first portion of the semiconductor substrate, and contacted with the first well region; a semiconductor layer formed on the insulating layer; an element isolation region reaching to an inside of the first well region, in cross-section view; a first gate electrode layer formed on a first portion of the semiconductor layer via a first gate insulating film; a second gate electrode layer formed on a second portion of the semiconductor layer via a second gate insulating film, and formed on a first portion of the element isolation region; an interlayer insulating film covering the first gate electrode layer, the second gate electrode layer and a second portion of the element isolation region; and a first plug conductor layer formed in the interlayer insulating film.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: July 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiki Yamamoto
  • Patent number: 10347646
    Abstract: A structure includes a word-line, a bit-line, and an anti-fuse cell. The anti-fuse cell includes a reading device, which includes a first gate electrode connected to the word-line, a first gate dielectric underlying the first gate electrode, a drain region connected to the bit-line, and a source region. The first gate dielectric has a first thickness. The drain region and the source region are on opposite sides of the first gate electrode. The anti-fuse cell further includes a programming device including a second gate electrode connected to the word-line, and a second gate dielectric underlying the second gate electrode. The second gate dielectric has a second thickness smaller than the first thickness. The programming device further includes a source/drain region connected to the source region of the reading device.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhon Jhy Liaw, Shien-Yang Wu
  • Patent number: RE48944
    Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: February 22, 2022
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Robert B. Welstand, Mark L. Burgener