Simultaneous Operations (e.g., Read/write) Patents (Class 365/189.04)
  • Patent number: 11570047
    Abstract: Disclosed are systems, methods, and computer-readable media for assuring tenant forwarding in a network environment. Network assurance can be determined in layer 1, layer 2 and layer 3 of the networked environment including, internal-internal (e.g., inter-fabric) forwarding and internal-external (e.g., outside the fabric) forwarding in the networked environment. The network assurance can be performed using logical configurations, software configurations and/or hardware configurations.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: January 31, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Sanchay Harneja, Sanjay Sundaresan, Harsha Jagannati
  • Patent number: 11543997
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: January 3, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Patent number: 11514983
    Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells without having bit values stored in the memory cells to include an identifier of the programming mode. During the test of which of the memory cells in the set is in a lowest voltage region, which is a common operation for reading the memory cells programmed in different mode, the statistics of the memory cells found to be in the lowest voltage region can be compared to the known, different behaviors of the memory cell set programmed in different modes. A match with the behavior of one of the modes can be used to identify the matching mode as the programming mode of the set of memory cells.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Karthik Sarpatwari, Fabio Pellizzer, Nevil N. Gajera
  • Patent number: 11456021
    Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: September 27, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang Gu Jo, Donggun Kim, Yong Ju Kim, Do-Sun Hong
  • Patent number: 11449346
    Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: September 20, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Jyoti Raheja, Hideki Kanayama, Guhan Krishnan, Ruihua Peng
  • Patent number: 11438928
    Abstract: A communication device includes a radio transceiver and a processor. The radio transceiver is configured to transmit or receive wireless signals and includes a collision detection device. The collision detection device is configured to detect energy in a wireless communication channel during a first time interval before a packet is transmitted by the radio transceiver and accordingly generate a detection result. The first time interval covers a period of time for the radio transceiver to switch from a receiving state to a transmitting state. The processor is configured to adjust at least one transmission parameter according to the detection result.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: September 6, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wei-Hsuan Chang, Shau-Yu Cheng, Cheng-Deom Hasio, Tsung-Chun Cheng
  • Patent number: 11392317
    Abstract: An embodiment may involve a network interface configured to capture data packets into a binary format and a non-volatile memory configured to temporarily store the data packets received by way of the network interface. The embodiment may also involve a first array of processing elements each configured to independently and asynchronously: (i) read a chunk of data packets from the non-volatile memory, (ii) identify flows of data packets within the chunk, and (iii) generate flow representations for the flows. The embodiment may also involve a second array of processing elements configured to: (i) receive the flow representations from the first array of processing elements, (ii) identify and aggregate common flows across the flow representations into an aggregated flow representation, (iii) based on a filter specification, remove one or more of the flows from the aggregated flow representation, and (iv) write information from the aggregated flow representation to the database.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: July 19, 2022
    Assignee: fmad engineering kabushiki gaisha
    Inventor: Aaron Foo
  • Patent number: 11372781
    Abstract: A memory module includes arrays of memory devices each having a data bus coupled to the data bus of a host memory channel by means of a switching tree. The switching tree is a tree of multiplexers that are controlled to couple the data lines of a single array to the data bus. In some embodiments, a first portion of the chip enable (CE) lines of a memory module are used to enable arrays of memory devices and a second portion are used to control the switching tree. The first portion may control a switching tree coupling the first portion to the enable inputs of the arrays.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: June 28, 2022
    Assignee: PETAIO INC.
    Inventors: Ivan Eng, Xinning Song
  • Patent number: 11356097
    Abstract: A semiconductor device using a programming unit with is provided. A highly reliable semiconductor device using the programming unit is provided. A highly integrated semiconductor device using the programming unit is provided. In a semiconductor circuit having a function of changing a structure of connections between logic cells such as PLDs, connection and disconnection between the logic cells or power supply to the logic cells is controlled by a programming unit using an insulated gate field-effect transistor with a small amount of off-state current or leakage current. A transfer gate circuit may be provided in the programming unit. To lower driving voltage, a capacitor may be provided in the programming unit and the potential of the capacitor may be changed during configuration and during operation.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 7, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 11227653
    Abstract: A storage array for computational memory cells formed as a memory/processing array provides storage of the data without using the more complicated computational memory cells for storage. The storage array may have multiple columns of the storage cells coupled to a column of the computational memory cells. The storage array may have ECC circuitry.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: January 18, 2022
    Assignee: GSI Technology, inc.
    Inventors: Lee-Lean Shu, Park Soon-Kyu, Paul M. Chiang
  • Patent number: 11183234
    Abstract: An SRAM includes multiple memory cells, each memory cell includes a data storage unit; a data I/O control adapted to input data to, and output data from, a data line (BL); and multiple access controls respectively connected to at least two access control lines (WL's) and adapted to enable and disable the data input and output from the at least two WL's (WX and WY). The access controls are configured to permit data input only when both WL's are in their respective states that permit data input. A method of writing to a group of SRAM cells include sending a first write-enable signal to the cells via a first WL, sending a group of respective second write-enable signals to the respective cells, and, for each of the cells, preventing writing data to the cell if either of the first write-enable signal and respective second write enable signal is in a disable-state.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Yen-Huei Chen, Yi-Hsin Nien
  • Patent number: 11164638
    Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: November 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-Yeol Lee, Wook-Ghee Hahn
  • Patent number: 11126382
    Abstract: It discloses a technical solution of the present disclosure partitions a high-speed data code stream into a plurality of sequentially arranged data blocks so as to write the data blocks sequentially to a circular cache. The circular cache is comprised of N cache segments that share a write pointer, each cache segment owning an independent read pointer. The data blocks are sequentially written into the N cache segments; data will be continuously written to the 1st cache segment; data will be read from the cache segment at a relatively low rate and written to a corresponding SD card, thereby implementing data speed reduction; a controller will integrate the disordered data into a same SD card following the original arrangement order, thereby completing all data storage work.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 21, 2021
    Assignee: SHANDONG UNIVERSITY
    Inventors: Yong Wang, Zhe Wang, Hongyu Li, Feng Zhou
  • Patent number: 11093244
    Abstract: An apparatus includes a memory component, a delay component, and a command component coupled to the delay component. The command component can be configured to enter a received command associated with accessing a physical address in the memory component into an execution queue and mark the command as active. The command component can be configured to send the active command to the memory component to be executed. The command component can be configured to clear the active command from the execution queue in response to receiving a message from the memory component, via the delay component, indicating the active command has been executed. The delay component can be configured to delay the message from the memory component a particular period of time before sending the message to the command component.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bruce Dunlop, Gary J. Lucas, Edward C. McGlaughlin
  • Patent number: 11087830
    Abstract: A semiconductor device includes a flag pipe, a pattern mode control circuit, and a data copy control circuit. The flag pipe is configured to latch a pattern mode flag, a first pattern control flag, a second pattern control flag, a data copy flag, and an enlargement data copy flag based on a pipe input control signal and output a delayed pattern mode flag, a first delayed pattern control flag, a second delayed pattern control flag, and a synthesis data copy flag based on a pipe output control signal. The pattern mode control circuit is configured to set a first data pattern or a second data pattern based on the delayed pattern mode flag, the first delayed pattern control flag, and the second delayed pattern control flag. The data copy control circuit is configured to copy data inputted through a first data pad onto a data path electrically connected to a second data pad based on the synthesis data copy flag.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: August 10, 2021
    Assignee: SK hynix Inc.
    Inventors: Myung Kyun Kwak, Min O Kim, Min Wook Oh
  • Patent number: 11074963
    Abstract: A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m×n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: July 27, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Yu-Ping Huang, Chun-Hung Lin, Cheng-Da Huang
  • Patent number: 11036427
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a data access command which corresponds to data stored on NVRAM at a logical block address, and using content-addressable memory (CAM) to determine whether the logical block address corresponds to an active read modify write operation. In response to determining that the logical block address corresponds to an active read modify write operation, the data access command is satisfied using a first procedure. However, in response to determining that the logical block address does not correspond to an active read modify write operation, the data access command is satisfied using a second procedure. Moreover, using the CAM to determine whether the logical block address corresponds to an active read modify write operation is completed in a single clock cycle of the CAM.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kevin E. Sallese, Timothy J. Fisher
  • Patent number: 11011217
    Abstract: Control circuitry may operate to refresh memory banks and determine that a memory bank was not refreshed within a threshold time duration from the current time. The control circuitry may extend a duration of an operational mode in response to determining that the memory bank was not refreshed within the threshold time duration. In response to extending the duration of the operational mode, the control circuitry may refresh the second memory bank without refreshing the first memory bank.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Joosang Lee
  • Patent number: 10998074
    Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Corrado Villa, Shane D. Moser
  • Patent number: 10998059
    Abstract: A bias circuit includes a charging current reproduce unit, a cell current reproduce unit, a current comparator, and a bit line bias generator. The charging current reproduce unit generates a charging reference voltage according to a charging current flowing through a voltage bias transistor. The cell current reproduce unit generates a cell reference voltage according to a cell current flowing through a common source transistor. The current comparator includes a first current generator for generating a replica charging current according to the charging reference voltage, and a second current generator for generating a replica cell current according to the cell reference voltage. The bit line bias generator generates a bit line bias voltage to control a page buffer for charging a bit line according to a difference between the replica charging current and the replica cell current.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: May 4, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Weirong Chen, Qiang Tang
  • Patent number: 10956334
    Abstract: Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yihua Zhang, Jun Shen
  • Patent number: 10949496
    Abstract: In one embodiment, a matrix operation may be performed to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory. Data associated with the input matrix may be accessed using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval. The data accessed using the one or more strided memory operations may be stored in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Vijay Anand R. Korthikanti, Aravind Kalaiah, Tony L. Werner, Amir Khosrowshahi
  • Patent number: 10923184
    Abstract: An SRAM device has a voltage input terminal configured to receive a first signal at a first voltage level. A level shifter is connected to the voltage input terminal to receive the first signal, and the level shifter is configured to output a second signal at a second voltage level higher than the first voltage level. A memory cell has a word line and a bit line. The word line is connected to the output terminal of the level shifter to selectively receive the second signal at the second voltage level, and the bit line is connected to the voltage input terminal to selectively receive the first signal at the first voltage level. A sense amplifier is connected to the bit line and is configured to provide an output of the memory cell. The sense amplifier has a sense amplifier input connected to the output terminal of the level shifter to selectively receive the second signal at the second voltage level.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: February 16, 2021
    Inventors: Sanjeev Kumar Jain, Atul Katoch
  • Patent number: 10916298
    Abstract: A circuit for reducing dynamic power in SRAM and methods for using the same are disclosed. In one embodiment, a circuit for reducing dynamic power in SRAM includes a plurality of memory blocks, which includes a plurality memory banks, which in turn includes a plurality bit cells; a set of memory bank signal lines; a set of memory block signal lines shared across the plurality of memory banks in the memory block; a bridge circuit couple between the set of memory bank signal lines and the set of memory block signal lines; a set of sense amplifiers corresponding to the set of memory block signal lines, where the set of sense amplifiers are shared among the plurality of memory banks in the memory block; and a controller configured to control an access of one or more bit cells in the plurality bit cells.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: February 9, 2021
    Assignee: Ambient Scientific Inc.
    Inventor: Gajendra Prasad Singh
  • Patent number: 10902896
    Abstract: The present disclosure is related to a memory circuit. The memory includes a memory controller and a memory interface coupled between the memory controller and a memory device. The memory controller is configured to generate an output signal that is transmitted to the memory device. The memory interface includes a feedback path configured to receive the output signal and generates a feedback signal in response to the output signal and a variable reference voltage. The memory controller further includes a data register so as to sample the feedback signal in response to a clock signal having a phase with an adjustable shift.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: January 26, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ching-Sheng Cheng, Wen-Wei Lin
  • Patent number: 10884915
    Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: January 5, 2021
    Assignee: Radian Memory Systems, Inc.
    Inventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews
  • Patent number: 10877684
    Abstract: A distributed storage system stores a storage volume as segments that are allocated as needed and assigned VSIDs according to a monotonically increasing counter. The storage volume may be provisioned by an orchestration layer that manages the storage volumes as well as containers executing executable components of the storage volume. The storage volume may be replicated, such as by replicating slices of the storage volume. A primary copy of the slice may be moved from one node to another within the distributed storage system by designating it as a replica, creating a new replica at the new location which is then brought current. The new replica is then designated as the primary replica and the former primary replica may be deleted. A non-replicated storage volume may be converted to a replicated storage volume and vice versa.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: December 29, 2020
    Assignee: ROBIN SYSTEMS, INC.
    Inventors: Ripulkumar Hemantbhai Patel, Dhanashankar Venkatesan, Jagadish Kumar Mukku
  • Patent number: 10861517
    Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
  • Patent number: 10848257
    Abstract: An apparatus and method for timestamping data packets are provided. The apparatus includes an input bit counter responsive to input bits entering a physical layer (PHY) device and an output bit counter responsive to output bits transmitted by the PHY device. A timestamp for an incoming bit is calculated based on a number of bits awaiting transmission by the PHY device at the time of arrival of the incoming bit. The number of bits awaiting transmission by the PHY device is determined based on the first count and the second count.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: November 24, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Eric Baden, Ankit Bansal, Sharath Gargeshwari
  • Patent number: 10824553
    Abstract: A memory device includes a nonvolatile memory unit, a write buffer, and a controller. The controller is configured to receive a write command from a host, send a permission signal to the host after the write command is received, receive write data associated with a write command from the host in response to the permission signal, store the write data in the write buffer, and transfer the write data stored in the write buffer to the nonvolatile memory unit. The controller controls a timing of transmitting the permission signal, such that the write buffer is full for no longer than a predetermined length of time.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 3, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshihisa Kojima
  • Patent number: 10740264
    Abstract: A synchronous differential memory interconnect may include a bidirectional differential data signal bus, a unidirectional differential command and address bus, and a differential clock signal. Memory read and write data may be transmitted over the data signal bus in a serial fashion.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 11, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Reza Bacchus, Mujeeb Rehman
  • Patent number: 10740029
    Abstract: A processing system employs an expandable memory buffer that supports enlarging the memory buffer when the processing system generates a large number of long latency memory transactions. The hybrid structure of the memory buffer allows a memory controller of the processing system to store a larger number of memory transactions while still maintaining adequate transaction throughput and also ensuring a relatively small buffer footprint and power consumption. Further, the hybrid structure allows different portions of the buffer to be placed on separate integrated circuit dies, which in turn allows the memory controller to be used in a wide variety of integrated circuit configurations, including configurations that use only one portion of the memory buffer.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 11, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Gabriel H. Loh, William L. Walker
  • Patent number: 10726911
    Abstract: A memory system according to an embodiment includes a semiconductor memory and a memory controller. The semiconductor memory includes memory cells and a sequencer. Each of the memory cells stores first data when it has a first threshold voltage, and stores second data when it has a second threshold voltage. The sequencer performs a first write operation for write data. In the first write operation, the sequencer executes a program loop repeatedly and terminates the first write operation, when the verify operation for the first data has passed and the verify operation for the second data has not passed. The sequencer performs a second write operation for the write data based on a first command from the memory controller after the first write operation is terminated.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: July 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kuminori Hyodo, Kenji Sakurada, Masanobu Shirakawa, Hideki Yamada
  • Patent number: 10726905
    Abstract: The present invention relates to a method of performing a write access phase for a memory device and comprising: transferring a write data from a local input and output line to a bit line to write the data into a memory cell via the bit line by activating a column switch provided between the bit line and the local input and output line during a first period; and transferring a read data read out from the memory cell to the local input and output line via the bit line by activating the column switch during a second period; wherein the first period is longer than the second period.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Martin Brox, Milena Ivanov
  • Patent number: 10691626
    Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Bill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
  • Patent number: 10657015
    Abstract: A memory system is disclosed, comprising a primary memory module, a secondary memory module, and a controller. The controller is configured to identify addresses in the primary memory module requiring correction, and is further configured to receive a memory access request identifying an address in the primary memory module. The controller is configured to determine whether the address is identified as requiring correction and, if it is not, to direct the memory access request to the primary memory module. If the address is identified as requiring correction, the controller is configured to direct the memory access request to the secondary memory module.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 19, 2020
    Assignee: NXP B.V.
    Inventors: Ajay Kapoor, Jurgen Geerlings
  • Patent number: 10650878
    Abstract: Apparatuses and methods of for refresh control of a semiconductor device are described. An example apparatus includes a command control circuit that provides a plurality of pulses on a first control signal in series responsive to a plurality of refresh commands issued in series; a signal generation circuit that produces a plurality of pulses on a second control signal in sequence; and a refresh control circuit that receives two or more of the plurality of pulses on the first control signal during a period of time between one pulse and a succeeding pulse of the plurality of pulses on the second control signal, disables refresh operations responsive to at least one of the two or more of the plurality of first control signal and executes a refresh operation responsive to remaining one or more pulses of the two or more of the plurality of pulses on the first control signal.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Toru Ishikawa
  • Patent number: 10636480
    Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 28, 2020
    Assignee: Adesto Technologies Corporation
    Inventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
  • Patent number: 10613764
    Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes a computing resource and a memory controller coupled to a memory device. The computing resource selectively generates a hint that includes a target address of a memory request generated by the processor. The hint is sent outside the primary communication fabric to the memory controller. The hint conditionally triggers a data access in the memory device. When no page in a bank targeted by the hint is open, the memory controller processes the hint by opening a target page of the hint without retrieving data. The memory controller drops the hint if there are other pending requests that target the same page or the target page is already open.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 7, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ravindra N. Bhargava, Philip S. Park, Vydhyanathan Kalyanasundharam, James Raymond Magro
  • Patent number: 10565121
    Abstract: A cache is presented. The cache comprises a tag array configured to store one or more tag addresses; a tag control buffer configured to store cache control information; a data array configured to store data acquired from a memory device; and a write buffer configured to store information related to a write request. The tag array is configured to be accessed independently from the tag control buffer, and the data array is configured to be accessed independently from the write buffer.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: February 18, 2020
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventor: Xiaowei Jiang
  • Patent number: 10559350
    Abstract: A memory circuit according to an embodiment includes: a first inverter circuit including a first p-channel MOS transistor and a first n-channel MOS transistor; a second inverter circuit cross-coupled with the first inverter and including a second p-channel MOS transistor and a second n-channel MOS transistor; a third n-channel MOS transistor in which one of a source and drain terminals is connected to a first output terminal of the first inverter circuit, and a gate terminal is connected to a first wiring line; a fourth n-channel MOS transistor connected to the third n-channel MOS transistor; a fifth n-channel MOS transistor in which one of a source and drain terminals is connected to a second output terminal of the second inverter circuit; and a sixth n-channel MOS transistor connected to the fifth n-channel MOS transistor.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 11, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masato Oda, Shinichi Yasuda
  • Patent number: 10552047
    Abstract: A memory system includes a memory controller comprising n (where n>2) first data input/output terminals, a first semiconductor chip comprising n second data input/output terminals, each of the second data input/output terminals being connected to a respective one of the first data input/output terminals, and a second semiconductor chip comprising n third data input/output terminals, each of the third data input/output terminals being connected to a respective one of the first data input/output terminals. When a first request signal is output from the memory controller, status data of the first semiconductor chip is output from a first of the second data input/output terminals that is connected to a first of the first data input/output terminals, and status data of the second semiconductor chip is output from a second of the third data input/output terminals that is connected to a second of the first data input/output terminals.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: February 4, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuusuke Nosaka, Masanobu Shirakawa, Yoshihisa Kojima, Kiyotaka Iwasaki, Hiroshi Sukegawa
  • Patent number: 10528286
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. A set of ports includes a first port and a second port. A first port includes a first plurality of electrical contacts and a second port includes a second plurality of electrical contacts. An on-die controller communicates via a set of ports to receive command and address information and to transfer data for data operations on an array of non-volatile memory cells. An on-die controller uses a first port to receive command and address information and to transfer data. An on-die controller uses a second port to transfer data but not to receive command and address information.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: January 7, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Ravindra Arjun Madpur, Amandeep Kaur
  • Patent number: 10510402
    Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for reducing write disturbance while writing data into a first SRAM cell and accessing a second SRAM cell in a row of SRAM cells. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 17, 2019
    Assignee: Synopsys, Inc.
    Inventors: M. Sultan M. Siddiqui, Sumit Srivastav, Dattatray Ramrao Wanjul, Manankumar Suthar, Sudhir Kumar
  • Patent number: 10490252
    Abstract: Apparatuses for executing row hammer refresh are described. An example apparatus includes: memory banks, each memory bank of the memory banks includes: a latch that stores a row address; and a time based sampling circuit. The time based sampling circuit includes: a sampling timing generator that provides a timing signal of sampling a row address; and a plurality of bank sampling circuits, wherein each bank sampling circuit of the bank sampling circuits is included in a corresponding memory bank of the memory banks and provides a sampling signal to the latch in the corresponding memory bank responsive to the timing signal of sampling the row address; and an interval measurement circuit that receives an oscillation signal, measures an interval of a row hammer refresh execution based on a cycle of the oscillation signal, and further provides a steal rate timing signal for adjusting a steal rate to the sampling timing generator.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Yuan He
  • Patent number: 10488840
    Abstract: A production control apparatus includes a workpiece position detection unit, an ID generation unit, an ID notification unit, a data receiving unit, and a storage unit. The data receiving unit receives the unique IDs generated by the ID generation unit and the traceability data (actual production information) when the workpieces for which the unique IDs have been generated are processed, from the manufacturing machines to which the unique IDs have been notified by the ID notification unit. The storage unit records the unique IDs and the traceability data received by the data receiving unit in association with each other.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 26, 2019
    Assignee: FANUC CORPORATION
    Inventors: Shinsuke Sakakibara, Hiroji Nishi
  • Patent number: 10456819
    Abstract: A system comprising a memory controller coupled to a memory device is described. The memory device is coupled to, and is external to, the memory controller. The memory device includes a storage array having dual configurability to support both synchronous and asynchronous modes of operation.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: October 29, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hamid Khodabandehlou, Syed Babar Raza
  • Patent number: 10438654
    Abstract: Transpose static random access memory (SRAM) bit cells configured for horizontal and vertical read operations are disclosed. In one aspect, a transpose SRAM bit cell includes cross-coupled inverters and horizontal and vertical read access transistors. A word line in first metal layer having an axis in a first direction is electrically coupled to a gate node of the horizontal read access transistor, and a bit line in second metal layer having an axis disposed in a second direction substantially orthogonal to the first direction is electrically coupled to the horizontal read access transistor. A transpose word line in third metal layer having an axis disposed in the second direction is electrically coupled to a gate node of the vertical read access transistor, and a transpose bit line in fourth metal layer having an axis disposed in the first direction is electrically coupled to the vertical read access transistor.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: October 8, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Yandong Gao
  • Patent number: 10432337
    Abstract: An apparatus and method for timestamping data packets are provided. The apparatus includes an input bit counter responsive to input bits entering a physical layer (PHY) device and an output bit counter responsive to output bits transmitted by the PHY device. A timestamp for an incoming bit is calculated based on a number of bits awaiting transmission by the PHY device at the time of arrival of the incoming bit. The number of bits awaiting transmission by the PHY device is determined based on the first count and the second count.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: October 1, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Eric Baden, Ankit Bansal, Sharath Gargeshwari
  • Patent number: 10388357
    Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz