Simultaneous Operations (e.g., Read/write) Patents (Class 365/189.04)
  • Patent number: 10528286
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. A set of ports includes a first port and a second port. A first port includes a first plurality of electrical contacts and a second port includes a second plurality of electrical contacts. An on-die controller communicates via a set of ports to receive command and address information and to transfer data for data operations on an array of non-volatile memory cells. An on-die controller uses a first port to receive command and address information and to transfer data. An on-die controller uses a second port to transfer data but not to receive command and address information.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: January 7, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Ravindra Arjun Madpur, Amandeep Kaur
  • Patent number: 10510402
    Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for reducing write disturbance while writing data into a first SRAM cell and accessing a second SRAM cell in a row of SRAM cells. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 17, 2019
    Assignee: Synopsys, Inc.
    Inventors: M. Sultan M. Siddiqui, Sumit Srivastav, Dattatray Ramrao Wanjul, Manankumar Suthar, Sudhir Kumar
  • Patent number: 10488840
    Abstract: A production control apparatus includes a workpiece position detection unit, an ID generation unit, an ID notification unit, a data receiving unit, and a storage unit. The data receiving unit receives the unique IDs generated by the ID generation unit and the traceability data (actual production information) when the workpieces for which the unique IDs have been generated are processed, from the manufacturing machines to which the unique IDs have been notified by the ID notification unit. The storage unit records the unique IDs and the traceability data received by the data receiving unit in association with each other.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 26, 2019
    Assignee: FANUC CORPORATION
    Inventors: Shinsuke Sakakibara, Hiroji Nishi
  • Patent number: 10490252
    Abstract: Apparatuses for executing row hammer refresh are described. An example apparatus includes: memory banks, each memory bank of the memory banks includes: a latch that stores a row address; and a time based sampling circuit. The time based sampling circuit includes: a sampling timing generator that provides a timing signal of sampling a row address; and a plurality of bank sampling circuits, wherein each bank sampling circuit of the bank sampling circuits is included in a corresponding memory bank of the memory banks and provides a sampling signal to the latch in the corresponding memory bank responsive to the timing signal of sampling the row address; and an interval measurement circuit that receives an oscillation signal, measures an interval of a row hammer refresh execution based on a cycle of the oscillation signal, and further provides a steal rate timing signal for adjusting a steal rate to the sampling timing generator.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Yuan He
  • Patent number: 10456819
    Abstract: A system comprising a memory controller coupled to a memory device is described. The memory device is coupled to, and is external to, the memory controller. The memory device includes a storage array having dual configurability to support both synchronous and asynchronous modes of operation.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: October 29, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hamid Khodabandehlou, Syed Babar Raza
  • Patent number: 10438654
    Abstract: Transpose static random access memory (SRAM) bit cells configured for horizontal and vertical read operations are disclosed. In one aspect, a transpose SRAM bit cell includes cross-coupled inverters and horizontal and vertical read access transistors. A word line in first metal layer having an axis in a first direction is electrically coupled to a gate node of the horizontal read access transistor, and a bit line in second metal layer having an axis disposed in a second direction substantially orthogonal to the first direction is electrically coupled to the horizontal read access transistor. A transpose word line in third metal layer having an axis disposed in the second direction is electrically coupled to a gate node of the vertical read access transistor, and a transpose bit line in fourth metal layer having an axis disposed in the first direction is electrically coupled to the vertical read access transistor.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: October 8, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Yandong Gao
  • Patent number: 10432337
    Abstract: An apparatus and method for timestamping data packets are provided. The apparatus includes an input bit counter responsive to input bits entering a physical layer (PHY) device and an output bit counter responsive to output bits transmitted by the PHY device. A timestamp for an incoming bit is calculated based on a number of bits awaiting transmission by the PHY device at the time of arrival of the incoming bit. The number of bits awaiting transmission by the PHY device is determined based on the first count and the second count.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: October 1, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Eric Baden, Ankit Bansal, Sharath Gargeshwari
  • Patent number: 10388357
    Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
  • Patent number: 10388380
    Abstract: Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hikaru Tamura
  • Patent number: 10387064
    Abstract: A storage device includes a connector including a plurality of connection terminals connectable to an external device and a nonvolatile memory including a secure area and a normal area. The secure area is accessible when the secure signal indicates the secure mode, and the normal area is accessible when the secure signal indicates the non-secure mode. One of the plurality of connection terminals corresponds to a secure signal terminal for receiving a secure signal that indicates a secure mode or a non-secure mode.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-Soo Kim
  • Patent number: 10367506
    Abstract: A tri-state circuit that includes a control circuit coupled to a driver circuit. The driver circuit includes a first type of transistor connected in series with a second type of transistor. The control circuit receives an input data signal at an input data rate and a plurality of clock signals, and supplies a first signal and a second signal to the first type of transistor and the second type of transistor in response to the receipt of the input data signal. The control circuit further controls a tri-state switching operation of the first type of transistor and the second type of transistor such that the input data signal is selected and an output data signal is generated at an output data rate. The tri-state circuit is further utilized in other digital circuits, such as latch circuits, latch-based memory circuits or parallel-to-serial converter circuits to reduce inter symbol interference.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: July 30, 2019
    Assignee: SONY CORPORATION
    Inventor: Jeremy Gareth Chatwin
  • Patent number: 10346406
    Abstract: The systems, apparatus, methods, and computer program products described herein provide the capability for an entity to identify and autonomously contract via a blockchain database with an unknown and anonymous host device for access rights to a high volume raw data stream generated by a sensor of the host device. The systems, apparatus, methods, and computer program products further provide the capability for the entity to push or upload a software module to the host device to allow the entity to process the high volume raw data stream into a low volume data stream directly on the host device, i.e., at the source of the high volume raw data stream.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: David A. Booz, Jonathan D. Dye, Michael J. Dye, Egan F. Ford
  • Patent number: 10324835
    Abstract: A data storage device includes a first nonvolatile memory device including first LSB, CSB and MSB pages; a second nonvolatile memory device including second LSB, CSB and MSB pages; a data cache memory is configured to store data write-requested from a host device; and a control unit suitable for configuring the first and second LSB pages as an LSB super page, configuring the first and second CSB pages as a CSB super page, and configuring the first and second MSB pages as an MSB super page, wherein the control unit is configured to one-shot programs the data stored in the data cache memory in the first LSB, CSB and MSB pages when determination is made as a data stability mode, and is configured to one-shot programs data stored in the data cache memory in the LSB, CSB and MSB super pages in a performance-improving mode.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventors: Duck Hoi Koo, Yong Jin
  • Patent number: 10297314
    Abstract: An integrated circuit includes a first plurality of flip flops; a first bank of resistive memory cells, wherein each flip flop of the first plurality of flip flops uniquely corresponds to a resistive memory cell of the first bank of resistive memory cells; write circuitry configured to store data from the first plurality of flip flops to the first bank of resistive memory cells; and read circuitry configured to read data from the first bank of resistive memory cells and provide the data from the first bank for storage into the first plurality of flip flops.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: May 21, 2019
    Assignee: NXP USA, Inc.
    Inventors: Anirban Roy, Michael A. Sadd
  • Patent number: 10269420
    Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes a first decoder coupled to the first memory array, a second decoder coupled to the second memory array, and an output buffer. The first decoder obtains first data from the first memory array according a first address signal. The second decoder obtains second data from the second memory array according the first address signal. The output buffer selectively provides the first data or the second data as an output according to a control signal. The first data is complementary to the second data.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuhsiang Chen, Shao-Yu Chou, Chun-Hao Chang, Min-Shin Wu, Yu-Der Chih
  • Patent number: 10262719
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) and a method of operating the same. The DRAM includes a memory array, a refresh device and an access device. The refresh device is configured to perform a self-refresh operation on the memory array, wherein the self-refresh operation is interrupted in response to an access command. The access device is configured to access the memory array in response to the access command and the interruption of the self-refresh operation.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 16, 2019
    Assignee: Nanya Technology Corporation
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10204660
    Abstract: A device includes a memory array including a first sub-bank, a second sub-bank, a first strap cell and a data line. The first strap cell is arranged between the first sub-bank and the second sub-bank. The data line includes a first portion and a second portion. The first portion is arranged across the first sub-bank. The second portion is arranged across the second sub-bank, and is coupled to the first portion via the first strap cell.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Patent number: 10191665
    Abstract: A memory device may include a data output controller for generating a first clock signal and a second clock signal in response to a read enable clock signal, a page buffer for storing data, and outputting the data to the data output controller in synchronization with the first clock signal, and a data output buffer for receiving the data from the page buffer and outputting the received data to the external device in synchronization with the second clock signal. The first clock signal is generated in response to a data output delay control signal, the second clock signal is generated irrespective of the data output delay control signal.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 29, 2019
    Assignee: SK Hynix Inc.
    Inventor: Kyeong Min Chae
  • Patent number: 10191661
    Abstract: An integrated circuit device includes a first memory cell that stores data representative of configuration data when operating in a first mode, wherein the first memory cell stores data representative of user-accessible data when operating in a second mode. The integrated circuit device also includes a second memory cell that stores a value indicating whether the first memory cell is operating in the first mode or is operating in the second mode. The integrated circuit device further includes a switch coupled to the first memory cell and controlled by the second memory cell, wherein the switch provides a defined value to be read in place of the stored data of the first memory cell when the second memory cell stores the value indicating that the first memory cell is operating in the second mode.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: January 29, 2019
    Assignee: ALTERA CORPORATION
    Inventors: Bee Yee Ng, Gaik Ming Chan, Jeffrey Christopher Chromczak, Herman Henry Schmit
  • Patent number: 10170174
    Abstract: Apparatuses for executing row hammer refresh are described. An example apparatus includes: memory banks, each memory bank of the memory banks includes: a latch that stores a row address; and a time based sampling circuit. The time based sampling circuit includes: a sampling timing generator that provides a timing signal of sampling a row address; and a plurality of bank sampling circuits, wherein each bank sampling circuit of the bank sampling circuits is included in a corresponding memory bank of the memory banks and provides a sampling signal to the latch in the corresponding memory bank responsive to the timing signal of sampling the row address; and an interval measurement circuit that receives an oscillation signal, measures an interval of a row hammer refresh execution based on a cycle of the oscillation signal, and further provides a steal rate timing signal for adjusting a steal rate to the sampling timing generator.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Yuan He
  • Patent number: 10163490
    Abstract: P-type Field-effect Transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells (“bit cells”). Related methods and systems are also disclosed. Sense amplifiers are provided in a memory system to sense bit line voltage(s) of the bit cells for reading the data stored in the bit cells. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-effect Transistor (NFET) drive current due for like-dimensioned FETs. In this regard, in one aspect, PFET-based sense amplifiers are provided in a memory system to increase memory read times to the bit cells, and thus improve memory read performance.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: December 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Hoan Huu Nguyen, Francois Ibrahim Atallah, Keith Alan Bowman, David Joseph Winston Hansquine, Jihoon Jeong
  • Patent number: 10163385
    Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: December 25, 2018
    Assignee: Apple Inc.
    Inventors: Fenghua Zheng, Christopher P. Tann, David S. Zalatimo, James E. C. Brown, Sandro H. Pintz
  • Patent number: 10140062
    Abstract: A memory device can include: a memory array comprising a plurality of memory cells; an interface configured to receive a suspend command and first and second write commands from a host, where the second write command is of higher priority and follows the first write command; a status register configured to store an automatic resume enable bit; a memory controller configured to suspend, in response to the suspend command, a first write operation that is executing the first write command on the memory array; the memory controller being configured to execute a second write operation on the memory array in response to the second write command; and the memory controller being configured to resume the first write operation upon completion of the second write operation in response to the automatic resume enable bit being set.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 27, 2018
    Assignee: Adesto Technologies Corporation
    Inventor: Bard M. Pedersen
  • Patent number: 10140224
    Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: November 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Mukund Narasimhan, Sharad Kumar Gupta, Dharaneedharan Shanmugasundaram
  • Patent number: 10102892
    Abstract: Unlike prior RAM-based shift register circuits, the presently-disclosed shift register circuit does not require control circuits to generate write and read address signals. Instead, the presently-disclosed shift register circuit utilizes a portion of RAM to store and provide the write and read address signals. The write and read addresses are output from the data output port of the RAM, and received by the write and read address ports of the RAM. Advantageously, the presently-disclosed shift register circuit requires less area to implement because the need for write and read control circuits is eliminated.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventor: Sergey Gribok
  • Patent number: 10078448
    Abstract: Electronic devices and memory management methods thereof are provided. Memory management methods may include setting page data of a nonvolatile memory as a read/write mode, copying the page data of the nonvolatile memory to a dynamic random access memory (DRAM) and setting the page data of the DRAM copied from the nonvolatile memory as a read only mode.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: September 18, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Young Lim, Taeksoo Kim, Indong Kim, Hangu Sohn
  • Patent number: 10068636
    Abstract: The present disclosure relates to a dynamic random access memory (DRAM) array, which comprises a plurality of bit lines connectable, respectively, to at least two row buffers of the DRAM array. The two row buffers are respectively connectable to data input/output (I/O) lines and are configured to electrically connect the two row buffers to the bit lines and data I/O lines in a mutually exclusive manner.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Berkin Akin, Shigeki Tomishima
  • Patent number: 10042587
    Abstract: A memory device can include: a memory array comprising a plurality of memory cells; an interface configured to receive a suspend command and first and second write commands from a host, where the second write command is of higher priority and follows the first write command; a status register configured to store an automatic resume enable bit; a memory controller configured to suspend, in response to the suspend command, a first write operation that is executing the first write command on the memory array; the memory controller being configured to execute a second write operation on the memory array in response to the second write command; and the memory controller being configured to resume the first write operation upon completion of the second write operation in response to the automatic resume enable bit being set.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 7, 2018
    Assignee: Adesto Technologies Corporation
    Inventor: Bard M. Pedersen
  • Patent number: 10038564
    Abstract: A technique is presented for performing a physical unclonable function (PUF) using an array of SRAM cells. The technique can be viewed as an attempt to read multiple cells in a column at the same time, creating contention that is resolved according to process variation. An authentication challenge is issued to the array of SRAM cells by activating two or more wordlines concurrently. The response is simply the value that the SRAM produces from a read operation when the challenge condition is applied. The number of challenges that can be applied the array of SRAM cells grows exponentially with the number of SRAM rows and these challenges can be applied at any time without power cycling.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 31, 2018
    Assignee: The Regents of The University of Michigan
    Inventors: Daniel E. Holcomb, Kevin Fu
  • Patent number: 10037971
    Abstract: A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: July 31, 2018
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventor: Akira Ide
  • Patent number: 10032501
    Abstract: A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a corresponding one of the plurality of memory cells MC; and a control circuit that intermittently monitors accesses to the plurality of word lines WL, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines WL in a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the Row Hammer problem, etc. can be taken.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 24, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Yuan He
  • Patent number: 10025516
    Abstract: Systems and methods are disclosed for processing data access requests received from a direct access storage (DAS) interface and/or a network access storage (NAS) interface. The data access requests may be received from the DAS interface and the NAS interface substantially simultaneously. The data access requests may be scheduled based on priorities for the data access requests.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: July 17, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: John E. Maroney
  • Patent number: 10024915
    Abstract: A semiconductor device may include an inversion control signal generation circuit, a pattern control signal generation circuit, and a data input/output (I/O) circuit. The inversion control signal generation circuit may generate an inversion control signal according to a logic level combination of bit patterns included in at least one of a first address and a second address. The pattern control signal generation circuit may generate a pattern control signal from a pre-control signal in response to the inversion control signal. In response to the pattern control signal, the data input/output (I/O) circuit may generate data signals that will be output to an internal I/O line based on data signals loaded on a local I/O line.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: July 17, 2018
    Assignee: SK hynix Inc.
    Inventors: Dong Hee Han, Saeng Hwan Kim, In Tae Kim, Byoung Chul Lee, Mun Seon Jang
  • Patent number: 10026472
    Abstract: In a multi-port memory, a first pulse signal generator circuit generates a first pulse signal following input of a clock signal. A first latch circuit sets a first start signal to a first state in response to generation of the first pulse signal, and resets the first start signal to a second state in response to a first delayed signal obtained by delaying the first start signal by a delay circuit. A second pulse signal generator circuit generates a second pulse signal following input of the first delayed signal. A first latch circuit sets a second start signal to the first state and holds this state in response to generation of the second pulse signal, and resets the second start signal to the second state in response to a second delayed signal obtained by delaying the second start signal by the delay circuit. The memory operates based on start signals.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: July 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yuichiro Ishii
  • Patent number: 10013352
    Abstract: Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at least one hardware processor core and a sectored dynamic random access (DRAM) cache coupled to the at least one hardware processor core.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Sreenivas Subramoney, Jayesh Gaur, Mukesh Agrawal, Mainak Chaudhuri
  • Patent number: 10002660
    Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 19, 2018
    Assignee: Bar-Ilan University
    Inventors: Robert Giterman, Adam Teman, Pascal Meinerzhagen, Andreas Burg, Alexander Fish
  • Patent number: 9996489
    Abstract: The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 12, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yaron Shachar, Yoav Peleg, Alex Tal, Alex Umansky, Rami Zemach, Lixia Xiong, Yuchun Lu
  • Patent number: 9965785
    Abstract: Disclosed are various embodiments for customizing component configurations used in utility computing. A selection of a subset of a set of hardware components is received from a customer. A request is received from the customer to allocate a machine instance on a customized computing device within a networked plurality of computing devices. The customized computing device includes the subset of the set of hardware components. A deployment of the machine instance on the customized computing device is initiated in response to the request.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 8, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Aaron T. Evans
  • Patent number: 9959938
    Abstract: In a method of operating a semiconductor memory device, a program command is received, and a program operation is performed to increase threshold voltages of memory cells to be programmed by applying a program pulse to a word line. Page data is read from the selected memory cells by applying a verification voltage to the word line, and it is determined whether the number of memory cells corresponding to a program pass is greater than a determined number, based on the page data. A status fail signal is output based on the determination result.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: May 1, 2018
    Assignee: SK Hynix Inc.
    Inventor: Chan Woo Yang
  • Patent number: 9947376
    Abstract: Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: April 17, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Tiwari, Kyle B. Wheeler
  • Patent number: 9947410
    Abstract: A non-volatile semiconductor memory device is provided. A determination circuit 200 used to determine the suspected qualification is connected with a plurality of page buffer/sensing circuits 170 via wirings PB_UP, PB_MG, PB_DIS. The page buffer/sensing circuit 170 includes a transistor Q2 in which a reference current Iref flows through a transistor Q1 when the programming verification is unqualified. The determination circuit 200 includes a comparator CMP, a voltage of the wiring PB_UP is supplied to one of input terminals of the comparator CMP, and a reference voltage Vref is supplied to another one of the input terminals. The reference voltage Vref is generated by a reference current (Iref*N) whose amount is corresponding to an unqualified bit number (N) which is determined to be suspectedly qualified.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 17, 2018
    Assignee: Winbound Electronics Corp.
    Inventors: Kazuki Yamauchi, Naoaki Sudo
  • Patent number: 9934156
    Abstract: A host write is received which includes a write address and write data. It is determined if the write address is already stored in at least one of a plurality of open blocks. If so, a collision open block is determined at least the write data is stored in the collision open block. In the event it is determined that the write address is not already stored in at least one of the plurality of open blocks, a temperature for the host write is determined and at least the write data is stored in an open block associated with the temperature.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: April 3, 2018
    Assignee: SK Hynix Inc.
    Inventors: Fan Zhang, Chun Hok Ho, Yan Zhang
  • Patent number: 9898400
    Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: February 20, 2018
    Assignee: Rambus Inc.
    Inventors: Thomas A. Sheffler, Lawrence Lai, Liang Peng, Bohuslav Rychlik
  • Patent number: 9891654
    Abstract: An integrated circuit (IC) having a clock switch that switches the system clock between an internal clock and an external clock based on whether or not the IC has finished downloading device configuration at boot and on whether or not the internal clock is functional. Further restrictions on the use of the external clock are imposed by the clock switch based on a life-cycle state of the IC. The use of the clock switch makes it significantly more difficult for the clock to be tampered with, thereby protecting the security settings of the IC and/or preventing unauthorized access to secure data stored on the IC using an external-clock-based security attack.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: February 13, 2018
    Assignee: NXP USA, INC.
    Inventors: Rohit K. Sinha, Vandana Sapra, Mandeep Singh, Sidharth S. Singh, Neha Srivastava
  • Patent number: 9870812
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: January 16, 2018
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Patent number: 9858976
    Abstract: According to one embodiment, a nonvolatile RAM includes a memory cell array, a first circuit being allowed to access the memory cell array in a write operation using a first pulse, and a second circuit being allowed to access the memory cell array in a read operation using a second pulse, the second circuit being allowed to operate in parallel with an operation of the first circuit. A width of the first pulse is longer than a width of the second pulse.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 2, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazutaka Ikegami, Hiroki Noguchi
  • Patent number: 9852803
    Abstract: A memory system includes blocks (or other groupings) of memory cells including data memory cells and dummy memory cells. In order to mitigate program disturb or other issues, the memory system applies a gate voltage based on temperature to all or a subset of the dummy memory cells as part of a memory operation.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: December 26, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Vinh Quang Diep, Liang Pang, Ching-Huang Lu, Yingda Dong
  • Patent number: 9805769
    Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: October 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyung Lee, JungSik Kim, Youngdae Lee, Duyeul Kim, Sungmin Yim, Kwangil Park, Chulsung Park
  • Patent number: 9785361
    Abstract: Systems and methods are disclosed for processing data access requests received from a direct access storage (DAS) interface and/or a network access storage (NAS) interface. The data access requests may be received from the DAS interface and the NAS interface substantially simultaneously. The data access requests may be scheduled based on priorities for the data access requests.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: October 10, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventor: John E. Maroney
  • Patent number: 9779798
    Abstract: Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array. In response to monitoring the row activation activity, a row activation counter table is stored in a memory. The row activation counter table comprises a plurality of row address entries, each row address entry having a corresponding row activation counter. In response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering, the corresponding row address entry associated with the row activation counter exceeding the threshold is determined. A refresh operation is performed on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: October 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Yanru Li, Dexter Chun, Jungwon Suh, Alexander Gantman