Abstract: According to one embodiment, a nonvolatile RAM includes a memory cell array, a first circuit being allowed to access the memory cell array in a write operation using a first pulse, and a second circuit being allowed to access the memory cell array in a read operation using a second pulse, the second circuit being allowed to operate in parallel with an operation of the first circuit. A width of the first pulse is longer than a width of the second pulse.

Abstract: A memory system includes blocks (or other groupings) of memory cells including data memory cells and dummy memory cells. In order to mitigate program disturb or other issues, the memory system applies a gate voltage based on temperature to all or a subset of the dummy memory cells as part of a memory operation.

Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

Abstract: Systems and methods are disclosed for processing data access requests received from a direct access storage (DAS) interface and/or a network access storage (NAS) interface. The data access requests may be received from the DAS interface and the NAS interface substantially simultaneously. The data access requests may be scheduled based on priorities for the data access requests.

Abstract: Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array. In response to monitoring the row activation activity, a row activation counter table is stored in a memory. The row activation counter table comprises a plurality of row address entries, each row address entry having a corresponding row activation counter. In response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering, the corresponding row address entry associated with the row activation counter exceeding the threshold is determined. A refresh operation is performed on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.

Abstract: In view of the neural network information parallel processing, a digital perceptron device analogous to the build-in neural network hardware systems for parallel processing digital signals directly by the processor's memory content and memory perception in one feed-forward step is disclosed. The digital perceptron device of the invention applies the configurable content and perceptive non-volatile memory arrays as the memory processor hardware. The input digital signals are then broadcasted into the non-volatile content memory array for a match to output the digital signals from the perceptive non-volatile memory array as the content-perceptive digital perceptron device.

Abstract: A refresh circuit is configured to perform a first refresh operation for a plurality of memory banks. The first refresh operation may be performed within a first time period determined according to a first parameter. The refresh circuit may be configured to perform a second refresh operation for a partial number of memory banks among the plurality of memory banks. The second refresh operation may be performed for the partial number of memory banks that have completed the first refresh operation. The second refresh operation may be performed within the first time period.

Abstract: A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells, and a memory controller. The memory controller is configured to count a clock to generate a current time, program dummy data at predetermined memory cells among the plurality of memory cells at a power-off state, detect a charge loss of the predetermined memory cells when a power-on state occurs after the power-off state, and restore the current time based on the detected charge loss.

Abstract: A memory device includes a first memory bank comprising first and second memory blocks; a second memory bank comprising third and fourth memory blocks; and a bank selection unit suitable for selecting a memory bank corresponding to a bank address among the first and the second memory banks when an active command is applied, wherein the selected memory bank performs row access on a word line of an unselected memory block, while activating a word line of a memory block that is selected by a block address among memory blocks of the selected memory bank.

Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

Abstract: A memory apparatus may include first to third pads to provide first to third voltages, respectively, to internal circuits. The first pad may receive a first external voltage, and provide the first voltage. The second and third pads may receive a second external voltage. The second pad may provide the second voltage, and the third pad may provide the third voltage.

Abstract: Memory devices may send information related to refresh rates to a memory controller. The memory controller may instruct the memory devices to refresh based on the received information.

Abstract: Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.

Abstract: An interface circuit is provided. A NMOS transistor is coupled between a first bit line and a ground. A logic gate is coupled between a gate of the NMOS transistor and a second bit line. A keeper controls a voltage level of the second bit line according to a reference voltage. A tracking circuit includes a plurality of reference bit cells and a pull-up device coupled to a reference bit line. Each reference bit cell is coupled to a read word line. When a bit cell coupled to the second bit line is accessed by a specific read word line, the reference bit cell coupled to the specific read word line drains a current from the pull-up device. The tracking circuit provides the reference voltage according to the current.

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Abstract: A method for improving access performance of a non-volatile storage device when programming data of a size smaller than a fixed minimum program number (FMPN) is disclosed. The method includes the steps of: predetermining a size of a blank data section for combining with a first data section and a second data section, the total size of the first data section, the second data section and the blank data section equals the FMPN; reading out data located at the second data section; updating a new data to the first data section; combining the new data with the data at the second data section; and incorporating the combined data with the blank data of the blank data section to become a final data, and programming the final data.

Abstract: Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.

Abstract: An integrated circuit (IC) device can include a plurality of banks, each including a plurality of memory cells, and separately accessible according to a received bank address value, each bank configured to enable accesses on different phases of an internal clock signal; and a plurality of channel groups, each channel group including a plurality of channels, each channel including its own data connections, address connections, and control input connections for accessing the banks, the channels of different groups accessing the memory banks on the different phases of the internal clock signal.

Abstract: According to one embodiment, there is provided a memory system including a 1st memory group, a 2nd memory group, a power supply voltage adjustment circuit, a 1st line, a 1st switch, a 2nd line, a 3rd line, and a 4th line. The power supply voltage adjustment circuit includes a 1st terminal and a 2nd terminal. The 1st line electrically connects the 1st terminal to the 1st memory group. The 1st switch includes a 3rd terminal, a 4th terminal, and a 5th terminal. The 1st switch electrically connects the 3rd terminal to the 4th terminal when turned on. The 2nd line electrically connects the 1st terminal to the 3rd terminal. The 3rd line electrically connects the 4th terminal to the 2nd memory group. The 4th line electrically connects the 2nd terminal to the 5th terminal.

Abstract: Semiconductor devices capable of a sensing margin of a semiconductor device are described. A semiconductor device may include a plurality of mats, a plurality of sensing circuits, a plurality of connecting circuits, and a plurality of mat dividing circuits. The mats are divided into upper regions and lower regions and activated by word lines. The sensing circuits are arranged in regions among the plurality of mats and are configured to sense/amplify data applied from the plurality of mats. The connecting circuits are configured to control connections between the mats and the sensing circuits in correspondence to a plurality of bit line selection signals. The mat dividing circuits are configured to selectively connect bit lines of the upper regions and the lower regions to each other in correspondence to a plurality of mat selection signals.

Abstract: A semiconductor memory device includes a first memory bank and a second memory bank; an address counter unit including: a first address counter suitable for outputting a first counting address signal corresponding to the first memory bank; and a second address counter suitable for outputting a second counting address signal corresponding to the second memory bank; a first output control unit suitable for generating first column address signals in response to the first counting address signal during a data input operation, and generating the first column address signals in response to the second counting address signal during a data output operation; and a second output control unit generating second column address signals in response to the second counting address signal during the data input operation and the data output operation.

Abstract: Buffer designs and write/read configurations for a buffer in a network device are provided. According to one aspect, a first portion of the packet is written into a first cell of a plurality of cells of a buffer in the network device. Each of the cells has a size that is less than a minimum size of packets received by the network device. The first portion of the packet can be read from the first cell while concurrently writing a second portion of the packet to a second cell.

Abstract: Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed closer to the input/output circuit than the first FIFO.

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract: Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory bit-cell via access devices; a second sense amplifier coupled to the first sense amplifier and to the complementary resistive memory bit-cell via the access devices, wherein the second sense amplifier is operable to detect an error in the complementary resistive memory bit-cell.

Abstract: An item is determined to exist in a dataset by arranging the dataset into a plurality of subsets, each bounded by the minimum amount of memory that may be transferred between levels of memory in a memory configuration. The item and the subsets have attributes that allow for a determination of which subset the item would exist in if the item were in the dataset. A singular subset is transferred between levels of memory to determine whether the item exists in the transferred subset. If the item does not exist in the transferred subset, it is determined that the item does not exist in the dataset.

Abstract: A semiconductor device may include a first input/output (I/O) unit and a second I/O unit. The first I/O unit may include a first input path that receives a signal through a first pad and a first output path and a first I/O controller that output a signal to the first pad. The second I/O unit may include a second input path that receives a signal through a second pad and a second output path and a second I/O controller that output a signal to the second pad.

Abstract: A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.

Abstract: A static random access memory includes a first inverter and a second inverter, a first n-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. An output terminal of the first inverter is connected to an input terminal of the second inverter, and an input terminal of the first inverter is connected to an output terminal of the second inverter. The first NMOS transistor is configured to control a write signal, and the second NMOS transistor is configured to control a read signal. The first NMOS transistor is connected to the input terminal of the first inverter, the output terminal of the second inverter, a write word line, and a write bit line. The second NMOS transistor is connected to the output terminal of the first inverter, the input terminal of the second inverter, a read word line, and an internal line.

Abstract: Systems, processors, and methods for efficiently handling concurrent store and load operations within a processor. A processor comprises a load-store unit (LSU) with a banked level-one (L1) data cache. When a store operation is ready to write data to the L1 data cache, the store operation will skip the write to any banks that have a conflict with a concurrent load operation. A partial write of the store operation will be performed to those banks of the L1 data cache that do not have a conflict with a concurrent load operation. For every attempt to write the store operation, a corresponding store mask will be updated to indicate which portions of the store operation were successfully written to the L1 data cache.

Abstract: The disclosed invention provides an SRAM capable of stably generating a PUF-ID without having to be powered on/off under control. The SRAM including a plurality of write ports is provided with a plurality of word lines, each transferring write data from each of the write ports to one memory cell. Timing to negate at least two word lines (AWL, BWL), respectively coupled to two write ports, among the word lines is synchronized. Because synchronicity of writing different values to the memory cell is assured, by using a large number of such memory cells, it is possible to stably generate a PUF-ID without power on/off control.

Abstract: A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

Abstract: A built-in self-test circuit includes a command storage unit that stores commands inputted from an external device, an input/output control unit that controls the command storage unit to sequentially store the commands and sequentially output stored commands as internal commands in a test operation, and a command decoder unit that decodes the internal commands outputted from the command storage unit and outputs a test command.

Abstract: A circuit for measuring instantaneous voltage drops in an IC is disclosed. In one embodiment, a measurement circuit is configured to perform measurements of a voltage drop between a supply voltage node and reference (e.g., ground) node. The measurement circuit may perform consecutive voltage measurements over a number of clock cycles. The measurements may be compared to a reference voltage, and the results of the comparisons may be provided to a register unit. The register unit may include a number of storage locations indicating at which cycles, if any, voltage droops have occurred. Additionally, the register may store information indicating maximum and minimum voltage droops.

Abstract: A level conversion circuit is provided for generating an output signal having one of a higher output level and a lower output level in response to an input signal having one of a higher input level and a lower input level. The level conversion circuit has input circuitry which, in response to a transition of the input signal between the higher and lower input levels, output a rising transition of a temporary output signal on the output line towards the higher input level. Output control circuitry detects the rising transition of the temporary output signal and pulls the output signal to the higher output level. This arrangement allows for fast level conversion without a DC leakage path.

Abstract: Logical memories and other logic functions specified in designs are mapped to power-optimized implementations using physical memories and other device resources. A logical memory may be automatically mapped to numerous potential physical implementations. Power consumption is estimated for each potential physical implementation to select the physical implementation providing the best performance with respect to power consumption and any other design constraints. Potential physical implementations can suppress clock transitions via clock enable inputs when embedded memory is not accessed. Read-enable and write-enable signals can be converted to functionally equivalent clock enable signals. Clock enable signals can be created to deactivate unused memory access ports and to deactivate embedded memory blocks during don't-care conditions. Potential physical implementations can slice logical memory into two or more embedded memory blocks to minimize power consumption.

Abstract: An integrated circuit having an external connection pad and an active circuit for generating signals to be output from the integrated circuit by means of the pad, the integrated circuit including an interface circuit associated with the pad, the interface circuit including a latch coupled between the pad and an output of the active circuit, the latch being capable of operating in a first mode in which the state of the pad follows the state of the output of the active circuit and a second mode in which the state of the pad is held by the latch.

Abstract: Circuits for programming an electrical fuse, methods for programming an electrical fuse, and methods for designing a silicon-controlled rectifier for use in programming an electrical fuse. A programming current for the electrical fuse is directed through the electrical fuse and the silicon-controlled rectifier. Upon reaching a programmed resistance value for the electrical fuse, the silicon-controlled rectifier switches from a low-impedance state to a high-impedance state that interrupts the programming current.

Abstract: A waveform generator circuit includes a memory with address locations storing output waveform defining data bits. An address counter generates an address for sequentially addressing the address locations in the memory. The memory responds by sequentially outputting the output waveform defining data bits at the addressed locations. An output circuit receives the waveform defining data bits output from the memory and operates to generate an output signal waveform having logic state values dependent on the sequentially output waveform defining data bits.

Abstract: The invention comprises an improved process of reading out SRAM or like memory elements which utilize pre-charging of cell output buses. In the output configuration of the invention, Gray Code counter outputs are used as inputs in a decoder block, the decoder block being configured to output a valid column selection address for every two address inputs. These column outputs are mapped sequentially to the columns of the memory array, such that the columns are sequentially read out, each readout operation being interspersed with a parking interval. The Gray code address inputs reduce readout addressing errors and the parking interval creates a delay between cell readout operations that reduces glitch errors.

Abstract: A memory device includes a first memory array, a first read port, a second read port, and a control input port. The first memory array contains a plurality of memory cells arranged in an array configuration. The first read port is configured to read first data from a single memory cell during a single read cycle, and the second read port is configured to read second data from a group of memory cells controlled by a common word line. Further, the control input is configured to receive a mode signal indicating a functional mode for the memory device including a first read mode and a second read mode. When the mode signal indicates the first read mode, the first read port is used to read the first data. When the mode signal indicates the second read mode, the first read port is used to read out the first data and the second read port is used to read the second data.

Abstract: Methods and apparatuses are disclosed for multi-memory array access. One example apparatus includes a pair of input/output lines, and a first array coupled to the pair of input/output lines. The first array is configured to provide data to and receive data from the pair of input/output lines. The example apparatus further includes an access block coupled to the pair of input/output lines. The access block is configured to access a second array responsive to memory access control signals directed to the second array. The access block is configured provide data between the second array and the pair of main input/output lines responsive to the access of the second array.

Abstract: A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.

Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

Abstract: A memory device with an age-detect-and-correct (ADAC) circuit that detects skew caused by bias temperature instability fatigue (that is, bias temperature instability stress accumulated over time), and counters skew by selectively adjusting the proportion (measured temporally) of active state operation to idle state operation. Also, a memory burn-in device using a similar ADAC circuit.

Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.