Abstract: The invention provides a memory apparatus including a memory cell array and a voltage generation circuit. The voltage generation circuit is electrically connected to the memory cell array and includes an active voltage circuit and a sensing circuit. The active voltage circuit is configured to output an operating voltage to the memory cell array when the memory apparatus is in an active mode. The sensing circuit is configured to sense the operating voltage when the memory apparatus is in a standby mode and briefly activate the active voltage circuit to pull up the operating voltage after the operating voltage drops below a threshold.

Abstract: A static random-access memory (SRAM) system includes SRAM cells configured to perform exclusive NOR operations between a stored binary weight value and a provided binary input value. In some embodiments, SRAM cells are configured to perform exclusive NOR operations between a stored binary weight value and a provided ternary input value. The SRAM cells are suitable for the efficient implementation of emerging deep neural network technologies such as binary neural networks and XNOR neural networks.

Abstract: A bias voltage generator includes a first current path, a first voltage clamp device, and a first buffer. The bias voltage generator receives a reference voltage and generates a first bias voltage based on a voltage difference between the reference voltage and a first drive voltage, the first voltage clamp device generates the first drive voltage based on the first bias voltage by applying the first drive voltage to the first current path, and the first buffer receives the first bias voltage and generates a second bias voltage based on the first bias voltage. A second current path includes a resistance-based memory device, and a second voltage clamp device generates a second drive voltage based on the second bias voltage and applies the second drive voltage to the second current path.

Abstract: According to one embodiment, a memory device includes a memory cell including a resistance change memory element in which a plurality of data values according to resistance are allowed to be set, and a selector element connected to the resistance change memory element in series, a word line supplying a select signal for selecting the resistance change memory element by the selector element to the memory cell, a bit line to which a data signal according to a data value set in the resistance change memory element is read, a load circuit connected to the memory cell in series and functioning as a load, and a comparator circuit which compares a voltage obtained by the load circuit with a plurality of reference voltages.

Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline. The integrated circuit may include a write driver coupled to the bitline for writing data to the bitcell. The write driver may have an inverter and a clamping device that are arranged to clamp current after data has been written to the bitcell.

Abstract: A charge pump includes first and second multiplier stages including first and second capacitor in series with an input node, a final multiplier stage including an output capacitor in series with the second capacitor and an output node, and pre-charge circuitry. The pre-charge circuitry is configured to charge the output capacitor to a first level during an initial phase of a charging operation, wherein the first level is equal to a supply voltage of the data storage system, and decouple a charging path of the pre-charge circuitry from the output capacitor in response to the output capacitor being charged to the first level. The first and second multiplier stages are configured to increase the charge of the output capacitor to second and third levels higher than the first level during second and third phases of the charging operation.

Abstract: Methods, systems, and devices for voltage drop mitigation techniques for memory devices are described. A memory device may include an array of memory cells, a conductive line, a pull-up circuit, and an output circuit. The conductive line may be configured to convey a first voltage for performing an operation with the array of memory cells. The pull-up circuit may be configured to couple the conductive line with a voltage source during at least a portion of a duration in which the operation is performed based on a first signal that enables applying a current to the array of memory cells as part of the operation. The output circuit may be configured to output a second signal to deactivate the pull-up circuit before the operation is complete. Outputting the second signal may be based on the first signal and a difference between the first voltage and a reference voltage.

Abstract: A physically unclonable function (PUF) generator includes a first sense amplifier that has a first input terminal configured to receive a signal from a first memory cell of a plurality of memory cells, and a second input terminal configured to receive a signal from a second memory cell of the plurality of memory cells. The first sense amplifier is configured to compare accessing speeds of the first and second memory cells of the plurality of memory cells. Based on the comparison of the accessing speeds, the sense amplifier provides a first output signal for generating a PUF signature. A controller is configured to output an enable signal to the first sense amplifier, which has a first input terminal configured to receive a signal from a bit line of the first memory cell and a second input terminal configured to receive a signal from a bit line of the second memory cell.

Abstract: A high current fast read scheme can enable improved read disturb without negatively impacting read performance. In one example, a fast read scheme involves applying a higher current as soon as the cell thresholds. In one example, circuitry detects the threshold event and turns on a bypass control transistor to bypass the circuitry applying the read voltage to enable a higher voltage and therefore higher current as soon as possible. The read time can thus be decreased (or at least not increased) and read disturb improved.

Abstract: A power control system provides multiple supply voltages that are guaranteed not to violate boundary conditions regardless of the timing of voltage change commands. A first voltage (Vlogic in the embodiments described herein) is controlled conventionally, and a second voltage (Vmemory) is either selected or generated by adding a selected offset to the first voltage. Both the size of the offset, and the absolute value of the second voltage, are constrained at all times, by constraint values specific to the current voltage zone. The invention ensures a smooth transition between different voltage operating points, and ensures that the trajectory of change between specified operating points remains within predefined boundaries.

Abstract: A signal communication circuit and methods for using the same are disclosed. In one embodiment, a circuit for signal communication includes a signal line configured to transmit signals, a transmitter circuit configured to drive a transmitted signal onto the signal line, a receiver circuit configured to detect the transmitted signal based on a deviation of a received signal from a reference signal on the signal line, and the receiver circuit is further configured to use the received signal to communicate the transmitted signal.

Abstract: Methods of operating a memory, and memories configured to perform similar methods, might include initiating discharge of a global access line that is connected to a local access line through a transistor, and electrically floating a control gate of the transistor, in response to a supply voltage decreasing to a first threshold, and initiating discharge of the control gate of the transistor in response to the supply voltage decreasing to a second threshold lower than the first threshold.

Abstract: There is provided a memory unit comprising an array of memory cells and a driver circuit configured to output an output address signal that addresses a portion/subset of the array of memory cells. The driver circuit comprises a logic gate that is configured to receive one or more input address signals and to provide an output address signal in dependence upon the one or more input address signals, and wherein the logic gate is configured to output a drive voltage provided by a first of the one or more input address signals as the output address signal when the output of the logic gate is true/high.

Abstract: An input/output multiplexer is provided and coupled to a memory array through bit lines. The input/output multiplexer includes a bit-line amplifier, a level-raising circuit, and a sensing amplifier. The bit-line amplifier amplifies a voltage difference between voltage levels of first and second bit lines in a read mode. In a first selection period of the read mode, according to the amplified voltage difference, a voltage level of a first local-data terminal of the bit-line amplifier is initially at an initial level, and a voltage level of a second local-data terminal thereof decreases from the initial level toward that of a low supply voltage. The level-raising circuit raises the voltage level of the first local-data terminal from the initial level in the first selection period. The sensing amplifier generates readout data according to the raised voltage level of the first local-data terminal and the voltage level of the second local-data terminal.

Abstract: A data retention circuit includes a power switch, a first inverter and a second inverter. The power switch has a first connection terminal coupled to a power voltage, and a second connection terminal coupled to the first power terminal and a second power terminal of a second inverter. The second input terminal and the second output terminal of the second inverter are coupled to the first output terminal and the first input terminal of the first inverter, respectively. In a sleep mode, the power switch and the transistor are turned off, a first leakage current flows between the first connection terminal and the second connection terminal, a second leakage current flows between the first power terminal and the first output terminal, and the first and the second leakage currents form a steady-state voltage, higher than or equal to a data retention voltage, on a second connection terminal.

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

Abstract: A memory device includes a first switch for switching a first power voltage and transmitting the first power voltage to a common node of a first power rail. A second switch switches a second power voltage and transmits the second power voltage to the common node. A control logic generates a first control signal for controlling the first switch during initial driving of the memory device. A masking circuit controls the first switch to maintain a turn on state in at least a partial period of the initial driving period of the memory device by providing a first masking control signal obtained by masking the first control signal to the first switch.

Abstract: A device includes memory cells, a first reference switch, a second reference switch, a first reference storage unit, a second reference storage unit, and an average current circuit. The memory cells are each configured to store corresponding bit data. The first reference switch and the second reference switch are turned on when a word line is activated. The first reference storage unit generates a first signal having a first logic state when the first reference switch is turned on. The second reference storage unit generates a second signal having a second logic state when the second reference switch is turned on. The average current circuit averages the first signal and the second signal to generate a reference signal to be compared with a current indicating the bit data of one memory cell, in order to determine a logic state of the bit data of the memory cell.

Abstract: A dynamic bit-line clamping circuit for computing-in-memory applications is configured to clamp a bit line via at least one reference signal and includes a clamping node, a first clamping unit, a second clamping unit, a first feedback controlling unit and a second feedback controlling unit. The first clamping unit is electrically connected between the bit line and the clamping node. The second clamping unit is electrically connected between the clamping node and a power source voltage and includes a switch. The second feedback controlling unit is electrically connected to the clamping node and the switch. The second feedback controlling unit generates a switching signal according to the at least one reference signal and a voltage level of the clamping node. The switch is switched by the switching signal so as to clamp the voltage level of the clamping node according to the at least one reference signal.

Abstract: A memory includes a bit line connected to a memory cell and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detecting an output signal from the memory cell, a first transistor to control a current supplied to the memory cell based on a first control signal, and a second transistor. One terminal of the first transistor is connected to the first input terminal, the other terminal of the first transistor is connected to one terminal of the second transistor, the other terminal of the second transistor is connected to the bit line, and the one terminal and the other terminal of the first transistor are charged before data is read from the memory cell.

Abstract: A power control system provides multiple supply voltages that are guaranteed not to violate boundary conditions regardless of the timing of voltage change commands. A first voltage (Vlogic in the embodiments described herein) is controlled conventionally, and a second voltage (Vmemory) is either selected, or generated by adding a selected offset to the first voltage. Both the size of the offset, and the absolute value of the second voltage, are constrained at all times, by constraint values specific to the current voltage zone. The invention ensures a smooth transition between different voltage operating points, and ensures that the trajectory of change between specified operating points remains within predefined boundaries.

Abstract: The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by splitting the data into a plurality of elements, copying each of the plurality of elements into elements that are wider than before being copied, and performing a logical operation associated with the reduction operation on each of the copied elements.

Abstract: A voltage supply circuit includes a step-down circuit configured to receive a power supply voltage, step down the power supply voltage to generate a step-down voltage having a constant value lower than a value of the power supply voltage, and a booster circuit configured to boost the step-down voltage to generate an output voltage, the output voltage having a value greater than the value of the power supply voltage.

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.

Abstract: According to an embodiment, an arithmetic device is configured to receive M input signals each representing a two-state value and M coefficients to output an output signal representing a two-state value. The device includes a positive-side current source, a negative-side current source, M cross switches, a coefficient memory unit, and a comparator. The positive-side current source is configured to output a first voltage corresponding to a value of 1/L of the current output from a positive-side terminal. The negative-side current source is configured to output a second voltage corresponding to a value of 1/L of the current output from a negative-side terminal. The memory unit includes M cells corresponding to the respective M coefficients. The comparator is configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage. Each M cell includes a first resistor and a second resistor.

Abstract: A novel low power enable circuit is less sensitive to power supply variations while consuming less than 50 nA of supply current. The enable circuit includes a voltage clamp circuit which limits the supply level for a first inverter. The clamp circuit having a first input connected to a supply, a second input connected to chip enable, and a first output.

Abstract: In a malware detection device, first characters in a network traffic flow are compared with a plurality of entries within a ternary content addressable memory (TCAM), the plurality of entries including a first entry that constitutes a first segment of a malware signature. In response to an output from the first TCAM indicating that the first characters match the first entry, a variable-character expression engine determines whether second characters in the network traffic flow match a first variable-length regular expression, the variable-length regular expression corresponding to a second segment of the malware signature. A comparand value is generated that includes third characters in the network traffic flow and an expression-match value that indicates whether the second characters match the first variable-length regular expression. The TCAM compares the first comparand value with the plurality of entries therein as part of a determination whether the network traffic flow contains the malware signature.

Abstract: Disclosed are methods, systems and devices for powering up devices including non-volatile memory elements in an array of non-volatile memory elements. In one aspect, during a sequence for powering up an integrated device, non-volatile memory elements may be isolated from voltage supplies to avoid in advertent changes of memory states stored in the non-volatile memory elements.

Abstract: A semiconductor device includes an internal signal processing block suitable for generating an internal enable signal and an internal control signal that correspond to an external enable signal and an external control signal, and a monitoring unit suitable for outputting a monitoring signal that corresponds to a predetermined internal signal, based on the internal enable signal and the internal control signal, in an initial operation period.

Abstract: A resistive memory device may include a resistive cell array and an on-chip resistance measurement circuit. The resistive cell array may include a plurality of resistive memory cells. The on-chip resistance measurement circuit may be configured to generate a first current and a second current greater or less than the first current based on a cell current corresponding to a cell resistance of a first memory cell of the resistive memory cells, and to generate first and second digital signals based on the first and second current, respectively.

Abstract: A resistive memory device comprising: a memory cell having a programmable resistance representing stored data; and a read circuit configured to be connected to the memory cell via a first signal line and read the stored data, wherein the read circuit includes: a voltage controller configured to control a first voltage of the first signal line to be a constant voltage and output a signal to a sensing node; and a sense amplifier connected to the voltage controller via the sensing node, and configured to compare a sensing voltage of the sensing node with a reference voltage.

Abstract: The memory system has an overwrite operation and an operation control method thereof. A nonvolatile memory device has a plurality of memory blocks including a plurality of memory cells stacked in a direction perpendicular to a substrate. When data of memory cells connected to a word line of a selected memory block is read, the need of reclaim is determined based on an error bit level of the read data. In the case that memory cells having an erase state among the memory cells connected to the word line become a soft program state, the read data is overwritten in the memory cells connected to the word line of the selected memory block.

Abstract: Approaches for stability of cells in a Static Random Access Memory (SRAM) array are provided. A circuit includes a precharging circuit configured to precharge bitlines of a Static Random Access Memory (SRAM) array to a first voltage potential for a non-read operation and to a second voltage potential for a read operation. The first voltage potential is different than the second voltage potential.

Abstract: A memory device comprises memory banks, power gates, and bank wake-up circuits. Each of the memory banks has a core voltage supply. The power gates are coupled to the memory banks for charging the core voltage supplies and have a plurality of powering modes. The bank wake-up circuits are coupled to the power gates for selecting one of the plurality of power modes for charging the memory banks during a wake-up mode. The bank wake-up circuits sense the core voltage supplies during the wake-up mode. The bank wake-up circuits serially charge the memory banks as a function of the sensed core voltage supplies of the memory banks.

Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

Abstract: An apparatus includes a memory cell, a bit line coupled to the memory cell, and a sense amplifier configured to amplify a data signal on the bit line read out from the memory cell. The sense amplifier is operated in a first mode with a first power source voltage difference and operated in a second mode with a second power source voltage difference smaller than the first power source voltage difference.

Abstract: A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage.

Abstract: A reconfigurable circuit according to an embodiment includes: first wiring lines; second wiring lines crossing the first wiring lines; resistive change elements disposed in intersection regions of the first and second wiring lines, each of the resistive change elements including a first terminal connected to the one of the first wiring lines and a second terminal connected to the one of the second wiring lines, and being switchable between a low-resistance state and a high-resistance state; a first control circuit controlling a voltage to be applied to the first wiring lines; a second control circuit controlling a voltage to be applied to the second wiring lines; and current limiting elements corresponding to the second wiring lines, and controlling current flowing through the resistive change elements connected to the corresponding second wiring line.

Abstract: A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.

Abstract: There is provided a method for operating a magnetic memory device. The method comprises selecting a subset of magnetic memory cells of the magnetic memory device; applying a first programming voltage to the selected subset of cells for a predetermined amount of time, wherein the programming voltage is selected to exceed a threshold operating voltage thereby to cause irreversible breakdown of the subset of cells; and reading selected cells of the magnetic memory device by passing a read current through a diode connected in series with each magnetic memory cell.

Abstract: A memory circuit includes a memory cell and a data circuit. In a write operation of the memory cell, the data circuit is configured to provide a first write logical value to the first output of the data circuit and to provide a second write logical value to the second output of the data circuit. The first write logical value is different from the second write logical value. In a read operation of the memory cell, the data circuit is configured to provide a same logical value to the first output and the second output of the data circuit.

Abstract: Adiabatic logic circuit having a first and a second inputs, a first and a second outputs and at least one supply and synchronization input (Phi), with this circuit comprising: a first logic device comprising at least one first microelectromechanical and/or nanoelectromechanical switch, referred to as first mechanical switch, controlled by a first input and connected to the first output and to the supply and synchronization input, a second logic device opposite the first logic device comprising at least one second microelectromechanical or nanoelectromechanical switch, referred to as second mechanical switch, controlled by the second input and connected to the second output and to the supply and synchronization input, first and second devices for partial discharging connected respectively between the first output and the supply and synchronization input and between the second output and the supply and synchronization input.

Abstract: Disclosed herein are test control circuit, semiconductor memory device, and testing method embodiments for suppressing variations in test time while reducing the influence of a failed cell. An embodiment operates by performing a first verify of a cell selected in a predetermined order; storing an address of the cell when the first verify is a fail until the number of addresses is a predetermined number; applying a predetermined voltage to a plurality of cells of an erase unit when a next fail is determined in the first verify after the predetermined number of addresses have been stored; and performing a second verify to one or more cells indicated by the predetermined number of addresses, wherein the first verify is performed from a cell at the next fail according to the predetermined order after the second verify has finished.

Abstract: Techniques and corresponding circuitry are presented for controlling the amount of current flowing through the cells of a memory circuit during a sensing operation though a feedback arrangement. The amount of current supplied to bit lines from an external power supply by regulation circuitry is compared with a reference level. Based on this comparison, the level on the control gates of clamp transistors in the sense amp circuits is set to control the amount of current supplied to the bit lines. This can reduce device variation since the levels are replicated locally at the generator on the chip. The circuitry can also be used more generally to determine the current level drawn during a sensing operation.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: Methods, memories and systems may include charging a sense node to a logic high voltage level, and supplying charge to a bit line and to a reference bit line for a precharge period that is based, at least in part, on a time for a voltage of the reference bit line to reach a reference voltage. A memory cell that is coupled to the bit line may be selected after the precharge period, and a clamp voltage may be set based, at least in part, on the voltage of the reference bit line. If a voltage level of the bit line is less than the clamp voltage level during a sense period, charge may be drained from the sense node, and a state of the memory cell may be determined based, at least in part, on a voltage level of the sense node near an end of the sense period.

Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the digit line for a period of time while the digit line driver is caused to bias the digit line at a voltage level sufficient to enable selection of the memory cell. In addition, the control circuit can be configured to cause the access line driver to bias an access line coupled to memory cell when the voltage of the digit line is at the voltage level sufficient to enable selection of the memory cell.

Abstract: A semiconductor memory device comprises an array of memory cells arranged in rows and columns, control lines coupled to the rows of memory cells for accessing the memory cells, conductive lines coupled to the rows of memory cells for powering the memory cells, and a control circuit configured to maintain non-selected conductive lines at a first voltage level and boost a selected conductive line to a second voltage level in an access operation, the second voltage level being higher than the first voltage level.