Abstract: A semiconductor memory storage device having a plurality of storage cells for storing data, each storage cell comprising an access control device and access control circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line to: control the voltage control switching circuitry to connect the at least one capacitor to the voltage supply line such that the at least one capacitor is charged by the voltage supply line and a voltage level on the voltage supply line is reduced; and to control the access control line switching circuitry to connect the selected access control line to the voltage supply line having the reduced voltage level.

Abstract: A semiconductor memory includes a memory array having memory cells coupled to wordlines and bitlines. Each wordline has a left end and an opposing right end. A first wordline in every two adjacent wordlines has its left end connected to a left row driver and its right end connected to a right clamp circuit, and a second wordline in every two adjacent wordlines has its right end connected to a right row driver and its left end connected to a left clamp circuit, such that when the right clamp circuits are activated, the right clamp circuits clamp the corresponding wordline ends to a predetermined potential, and when the left clamp circuits are activated, the left clamp circuits clamp the corresponding wordline ends to the predetermined potential.

Abstract: A static random access memory (SRAM) test apparatus includes an array of SRAM test cells. The test cells are configured according to a layout with NMOS and PMOS transistors coupleable as inverters and responsive to a first passing gate transistor. At least one of the NMOS and PMOS transistors of a test cell at a predetermined location in the array is coupled to a fixed voltage to force a logic state of an associated inverter. A switching signal coupled to the associated inverter through a second passing gate transistor produces a detectable test current through one of the NMOS and PMOS transistors of the associated inverter of said test cell and through one of the NMOS and PMOS transistors of an associated inverter of an adjacent series-connected test cell.

Abstract: A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

Abstract: One embodiment of the present invention sets forth a clamping circuit that is used to maintain a bit line of a storage cell in a memory array at a nearly constant clamp voltage. During read operations the bit line is pulled high or low from the clamp voltage by the storage cell and a change in current on the bit line is converted by the clamping circuit to produce an amplified voltage that may be sampled to read a value stored in the storage cell. The clamping circuit maintains the nearly constant clamp voltage on the bit line. Clamping the bit line to the nearly constant clamp voltage reduces the occurrence of read disturb faults. Additionally, the clamping circuit functions with a variety of storage cells and does not require that the bit lines be precharged prior to each read operation.

Abstract: A dynamic level shifter is disclosed. In one embodiment, a dynamic level shifter circuit may receive an input signal referenced to a first voltage of a first power domain, and may output a corresponding signal referenced to a second voltage into a second power domain. The dynamic level shifter circuit may include an evaluation node that is precharged during a first phase (e.g., the low portion) of a clock signal. During the second phase (e.g., the high portion) of the clock signal, the evaluation node may be either pulled low or high, depending on the state of the input signal. A corresponding output signal, based on the evaluated level on the evaluation node, may be output into the second power domain.

Abstract: A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.

Abstract: A current control device is disclosed, which reduces a standby current of a semiconductor memory device and a turn-on current of a transistor. The current control device includes an input controller configured to combine a trigger signal and a set signal controlling a circuit operation status, and a drive unit configured to drive an output signal of the input controller, wherein the drive unit includes a current controller for selectively providing a ground voltage in response to an activation status of a pull-down driving signal.

Abstract: A semiconductor memory device comprising: a memory cell array in which memory cells each containing a variable resistive element and a rectifier element connected in series are arranged at intersections of a plurality of first wirings and a plurality of second wirings; and a control circuit for selectively driving said first wirings and said second wirings; wherein said control circuit applies a first voltage to said selected first wiring, and changes said first voltage based on the position of said selected memory cell within said memory cell array to apply a second voltage to said selected second wiring, so that a predetermined potential difference is applied to a selected memory cell arranged at the intersection between said selected first wiring and said selected second wiring.

Abstract: An integrated circuit structure comprises a static random access memory (SRAM) structure and a logic circuit. A power supply is operatively connected to the SRAM structure, and provides a first voltage to the SRAM structure. A voltage limiter is operatively connected to the power supply. The voltage limiter comprises a switching device operatively connected to the power supply. The switching device receives the first voltage and a second voltage supplied to structures external to the SRAM structure. A resistive element is operatively connected to the switching device. The switching device connects the resistive element to the power supply. The resistive element is selected to enable an output from the switching device to the logic circuit when a difference between the first voltage and the second voltage is greater than a voltage threshold value of the switching device.

Abstract: In one example embodiment, the semiconductor device includes a memory cell array having at least one memory cell disposed in a region at which at least one bit line and at least one word line cross. A sensing unit senses data stored in the at least one memory cell. The sensing unit includes a connection control unit configured to control a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit.

Abstract: The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.

Abstract: A circuit including a memory circuit, the memory circuit includes a first plurality of memory arrays and a first plurality of keepers, each keeper of the first plurality of keepers is electrically coupled with a corresponding one of the first plurality of memory arrays. The memory circuit further includes a first current limiter electrically coupled with and shared by the first plurality of keepers.

Abstract: A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter.

Abstract: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a shape of a matrix along a plurality of parallel bit lines and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data read out to the bit lines; a sense amplifier which detects a voltage or a current of the bit line and decides the read data from each of the memory cells; a clamping transistor connected between the sense amplifier and the bit lines to determine a voltage in a charging mode of the bit lines by a clamp voltage applied to a gate thereof; and a clamp voltage generation circuit which generates the clamp voltage so as to become larger as a distance from the sense amplifier to a selected one of the memory cells is longer.

Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Abstract: In one embodiment, a memory is provided that includes: a write driver for selectively driving a driven pair of bit lines selected from a plurality of bit line pairs during a write operation; a first stage clamping circuit operable to clamp a pair of internal nodes to a clamping voltage, wherein the first stage clamping circuit is further operable to unclamp the pair of internal nodes during the write operation; a bit line multiplexer for selectively coupling the driven bit line pair to the pair of internal nodes; and a second stage clamping circuit operable to clamp the plurality of bit line pairs to the clamping voltage, wherein the second stage clamping circuit is further operable to unclamp the driven bit line pair during the write operation.

Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Abstract: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch the variable resistor; and a clamp voltage generator circuit operative to generate a clamp voltage required for access to the memory cell and applied to the first and second lines. The clamp voltage generator circuit has a temperature compensation function of compensating for the temperature characteristic of the first non-ohmic element.

Abstract: A disclosed synchronous memory control apparatus for enabling reception of data read from a memory circuit in synchronism with a strobe signal from the memory circuit includes a mask circuit masking the strobe signal using a mask signal; a timing measuring circuit delaying the strobe signal in plural units of delay and latching data of each of the delayed strobe signals; and a mask generating circuit generating the mask signal. The timing measuring circuit latches the data of each of the delayed strobe signals at the first rise edge of the corresponding masked strobe signal. The mask generating circuit includes a delay circuit having plural units of delay. A start timing of the mask signal is adjusted in synchronism with an internal clock, and a signal having a delay amount corresponding to a selected unit of delay by the delay circuit is outputted as the mask signal.

Abstract: A memory device includes at least one memory cell including a storage element electrically connected with a source potential line. A drive strength of the storage element is controlled as a function of a voltage level on the source potential line. The memory device further includes a clamp circuit electrically connected between the source potential line and a voltage source. The clamp circuit is operative to regulate the voltage level on the source potential line relative to the voltage source. A control circuit of the memory device is connected with the source potential line. The control circuit is operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device. A coarseness by which the voltage level on the source potential line is adjusted is selectively controlled as a function of at least a first control signal.

Abstract: Methods, devices, and systems are provided for a power generator system. The power generator system may include a control device configured to output a first reference voltage and a second reference voltage that define a dead band range. The control device may be configured to independently adjust the first reference voltage and the second reference voltage. The power generator system may also include a power generator operably coupled to the control device, and the power generator may be configured to receive the first reference voltage and the second reference voltage and to output a voltage that is greater than or substantially equal to the first reference voltage and less than or substantially equal to the second reference voltage.

Abstract: The present invention relates to a voltage control circuit, semiconductor memory device, and method of controlling a voltage in a phase-change memory, wherein the voltage control circuit generates a controlled voltage which can be above the logic supply voltage. This voltage can limit the bit line voltage in a phase-change memory to allow the use of smaller transistors in the memory cells and in the program current part of the circuit. This results in smaller memory cells and modules.

Abstract: A method of writing into a semiconductor memory device, which includes a resistance memory element 14 which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage; a transistor 12 including a drain terminal connected to one terminal of the resistance memory element 14 and a source terminal connected to a reference voltage; and a transistor 16 including a source terminal connected to the other terminal of the resistance memory element 14.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which determines the data in the memory cell transistor via the bit line, a first bit line clamp transistor connected in series between the bit line and the sense amplifier, a second bit line clamp transistor connected in parallel to the first bit line clamp transistor and having a current driving capability higher than that of the first bit line clamp transistor, and a bit line control circuit which turns on the first bit line clamp transistor and the second bit line clamp transistor using a common gate voltage during a predetermined period from a start of charge of the bit line, and turns off only the second bit line clamp transistor when the predetermined period has elapsed.

Abstract: The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines.

Abstract: A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.

Abstract: A nonvolatile memory device includes a cell array including a plurality of phase change memory cells, a switching unit configured to select any one of the plurality of phase change memory cells, a clamping unit coupled between the switching unit and a sensing line and configured to adjust an amount of a clamping current flowing through the sensing line, a program switching unit configured to couple the switching unit to the sensing line during a program operation, a voltage driving unit configured to supply the sensing line with a write voltage corresponding to data to be written during the program operation, and supply the sensing line with a constant read voltage during a data sensing operation, and a sense amplifier configured to compare and amplify a voltage of the sensing line and a preset read reference voltage.

Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells each of which is arranged at the intersection position between a pair of complementary bit lines and a word line, and stores data between a first power supply voltage applied to a first node and a voltage applied to a virtual ground node, and a control circuit which changes the amount of current of the pair of bit lines in accordance with the amplitude of the pair of bit lines for each column in a memory macro, that is formed by arranging the plurality of memory cells in a matrix, in the data read operation of each of the plurality of memory cells.

Abstract: A memory device includes at least one memory cell including a storage element electrically connected with a source potential line. A drive strength of the storage element is controlled as a function of a voltage level on the source potential line. The memory device further includes a clamp circuit electrically connected between the source potential line and a voltage source. The clamp circuit is operative to regulate the voltage level on the source potential line relative to the voltage source. A control circuit of the memory device is connected with the source potential line. The control circuit is operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device. A coarseness by which the voltage level on the source potential line is adjusted is selectively controlled as a function of at least a first control signal.

Abstract: A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.

Abstract: A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

Abstract: One embodiment of the present invention sets forth a clamping circuit that is used to maintain a bit line of a storage cell in a memory array at a nearly constant clamp voltage. During read operations the bit line is pulled high or low from the clamp voltage by the storage cell and a change in current on the bit line is converted by the clamping circuit to produce an amplified voltage that may be sampled to read a value stored in the storage cell. The clamping circuit maintains the nearly constant clamp voltage on the bit line. Clamping the bit line to the nearly constant clamp voltage reduces the occurrence of read disturb faults. Additionally, the clamping circuit functions with a variety of storage cells and does not require that the bit lines be precharged prior to each read operation.

Abstract: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A semiconductor memory device having a status register read function includes a plurality of data output pads electrically connected to corresponding package pin, and a swap controller connected between the plurality of data output pads and a plurality of output lines that output memory-related unique information in a specific operation mode. The swap controller controls a swap according to preset swap program information when a swap is needed to match the data output pads to the package pins.

Abstract: A phase change memory device includes a plurality of programming current driving blocks each of which is configured to provide a corresponding phase change memory cell with a programming current corresponding to input data and a programming current adjusting block commonly connected to the plurality of programming current driving blocks and configured to generate a control voltage to adjust the programming current.

Abstract: A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

Abstract: A phase change memory device includes a memory cell array having a plurality of phase change memory cells, a read bias generating circuit, a clamping circuit and a clamping control signal generating circuit (CCSGC). The read bias generating circuit provides a sensing node with a read bias for reading a resistance level of a selected phase change memory cell. The clamping circuit controls an amount of clamping current flowing into a bit line connected with the selected phase change memory cell. The CCSGC provides the clamping control signal to the clamping circuit and adjusts a level of the clamping control signal.

Abstract: A sense amplifier scheme for SRAM is disclosed. In accordance with one of the embodiments of the present application, a sense amplifier circuit includes a bit line, a sense amplifier output, a power supply node having a power supply voltage, a keeper circuit including an NMOS transistor, and a noise threshold control circuit. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and maintains a voltage level of the bit line and the noise threshold control circuit lowers a trip point of the sense amplifier output.

Abstract: A non-volatile memory device and a sensing method thereof are disclosed, which can sense multi-level data using resistance variation. The non-volatile memory device includes a cell array and a sensing unit. The cell array includes a plurality of unit cells where data is read out or written. The sensing unit compares a sensing voltage corresponding to data stored in the unit cell with a reference voltage, amplifies/outputs the compared result, measures a difference in discharge time where the sensing voltage is discharged in response to a resistance value of the unit cell during an activation period of a sensing enable signal after a bit line is precharged, and senses the data in response to the measured result.

Abstract: A NAND flash memory device having a bit line and a plurality of storage cells coupled thereto. Programming circuitry is coupled to the plurality of storage cells concurrently to program two or more of the storage cells in different NAND strings associated with the same bit line.

Abstract: A semiconductor memory includes a word line coupled to memory cells that transmits a word line signal; at least one word repeater circuit that includes a first load circuit disposed on the word line; a first dummy word line disposed along the word line that transmits a first dummy word line signal; at least one dummy repeater circuit that includes a second load circuit disposed on the first dummy word line; bit lines coupled to the memory cells; column switches that couple the bit lines to data lines, respectively; a column selection line disposed along the word line that transmits a column selection signal for controlling each column switch; and at least one column repeater circuit disposed on the column selection line that outputs the column selection signal in synchronization with the first dummy word line signal input to the first dummy repeater circuit.

Abstract: An integrated circuit includes an array of memory cells with a plurality of columns and rows. A plurality of data lines is coupled to the columns in the array and a plurality of word lines is coupled to the rows in the array. Clamp transistors are coupled to respective data lines in the plurality of data lines, and adapted to prevent voltage on the respective bit lines from overshooting a target level during a precharge interval. A bias circuit is coupled to the clamp transistors on the plurality of bit lines, and arranged to apply the bias voltage in at least two phases within a precharge interval, and to prevent overshoot of the target level on the bit line.

Abstract: A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

Abstract: A semiconductor memory device including: a memory cell array in which memory cells each containing a variable resistive element and a rectifier element connected in series are arranged at intersections of a plurality of first wirings and a plurality of second wirings; and a control circuit for selectively driving said first wirings and said second wirings; wherein said control circuit applies a first voltage to said selected first wiring, and changes said first voltage based on the position of said selected memory cell within said memory cell array to apply a second voltage to said selected second wiring, so that a predetermined potential difference is applied to a selected memory cell arranged at the intersection between said selected first wiring and said selected second wiring.

Abstract: A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.

Abstract: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.