Abstract: Methods and apparatus for managing electrical loads of electronic devices are disclosed. According to one embodiment, a current load imposed by an electronic device, such as a memory device (or memory system), can be measured. Then, using the measured current load, the memory device can determine whether (and to what extent) operational performance should be limited. By limiting operational performance, the memory device is able to limit its current load so as to satisfy a specification criterion or other requirement. The electrical load management is well suited for use in portable memory products (e.g., memory cards) to manage current loads being drawn.

Abstract: An apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the contents of the storage units to each other as to whether or not the counter outputs coincide with the contents of the storage units; a holding circuit for setting an output hit signal to an active state when a coincidence signal is output from the comparator circuits and for resetting the hit signal to an inactive state in the next following clock cycle; a circuit performing control for not propagating a refresh clock signal to the counter when the hit signal is in an active state and for propagating the refresh clock signal to the counter when the hit signal is in an inactive state; a circuit for replacing an output of the counter by a row address which changes part of the counter output when the hit signal is in an activate state to replace the counter output with the row address whose refresh period is subject t

Abstract: A memory device includes a memory array with a programming region to store data. The programming region includes a plurality of memory cells and has an associated flag bit. Logic is coupled to the memory array. The logic is to compare data stored in the programming region to a desired programmed value, and to determine a number of changing bits. The logic may further set or clear the associated flag bit, depending on the number of changing bits.

Abstract: A semiconductor memory device comprising: a memory cell array having a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data read out to the bit lines; a sense amplifier which detects a voltage or a current of the bit line, and which decides the read data from each of the memory cells; a clamping transistor which is connected between the sense amplifier and the bit lines, and which determines a voltage in a charging mode of the bit lines by a clamp voltage applied to a gate thereof; and a clamp voltage generation circuit which generates the clamp voltage so as to become larger as a distance from the sense amplifier to a selected one of the memory cells is longer.

Abstract: A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp transistor. The clamp transistor has a first end, a second end and a control end. The inverter has an input end electrically connected to the second end of the clamp transistor and an output end electrically connected to the control end of the clamp transistor. The bit line is electrically connected to the second end of the clamp transistor and the input end of the inverter and has a bit-line voltage thereon. The pre-charge path is electrically connected to the first end of the clamp transistor through a node having a sensing voltage thereon.

Abstract: Systems and methods for reducing instability and writability problems arising from relative variations between voltages at which memory cells and logic components that access the memory cells operate by inhibiting memory accesses when the voltages are not within an acceptable operating range. One embodiment comprises a pipelined processor having logic components which receive power at a first voltage and a set of SRAM cells which receive power at a second voltage. A critical condition detector is configured to monitor the first and second voltages and to determine whether the ratio of these voltages is within an acceptable range. When the voltages are not within the acceptable range, an exception is generated, and an exception handler stalls the processor pipeline to inhibit accesses to the SRAM cells. When the voltages return to the acceptable range, the exception handler resumes the pipeline and completes handling of the exception.

Abstract: A high voltage generator includes: a high voltage detecting unit for detecting a level of a high voltage and outputting a high enable signal; an auto refresh control unit for enabling an auto refresh high enable signal in response to a detection signal enabled when a level of a power supplying voltage is lower than a certain level and in response to the pumping enable signal during an auto refresh operation; and a high voltage generating unit for generating a high voltage by performing a pumping operation in response to the auto refresh pumping enable signal.

Abstract: A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

Abstract: Disclosed is a nonvolatile memory device using a variable resistive element, and a data read circuit for use in variable resistive memory devices. More specifically, embodiments of the invention provide a data read circuit with one or more decoupling units to remove noise from one or more corresponding control signals. For instance, embodiments of the invention remove noise from a clamping control signal, a read bias control signal, and/or precharge signal. The disclosed decoupling units may be used alone or in any combination. Embodiments of the invention are beneficial because they can increase sensing margin and improve the reliability of read operations in memory devices with variable resistive elements.

Abstract: A method and a relative automatic regulation device regulate the reference sources in a non-volatile memory device, for example a flash memory. The method includes the following steps: providing, in the memory device, a regulation device of the reference sources and at least one start command for the entry in regulation mode; providing, on the device, at least one command for the selection of a corresponding reference source to be regulated; applying an external reference signal; starting the automatic regulation step by means of said command; detecting the result of the regulation step by means of a logic output of the memory device; if the result of the regulation of a given source is positive, proceeding, by means of the same process steps, with the regulation of another source.

Abstract: A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.

Abstract: A memory device is proposed.

Abstract: A semiconductor storage device has memory cells provided at intersections of word lines and bit lines, a precharge circuit connected to the bit lines, and a write circuit. The write circuit includes a column selection circuit controlled by a write control signal, a transistor for controlling a potential of a selected bit line so that the potential of the selected bit line is a first potential (e.g., 0 V), a capacitance element for controlling the potential of the selected bit line so that the potential of the selected bit line is a second potential (e.g., a negative potential) that is lower than the first potential, and a clamp circuit for clamping the second potential when a power supply voltage becomes high.

Abstract: A semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged therein; and a sense amplifier circuit configured to read data of the memory cell array, wherein a comparison operation is performed between read out data from the memory cell array and externally supplied expectance data in the sense amplifier circuit.

Abstract: Systems and methods for producing a boosted voltage which can be used as a boosted word line voltage for read mode operations of memory cells are disclosed. The system contains a VCC comparator, a look up table, and a boosting circuit including a set of boosting capacitors. The look up table has a list of trim codes that indicates desired boosting ratios. The boosting ratio can vary depending on a level of a supply voltage to provide a sufficient word line voltage, thereby preventing and/or mitigating delay in reading operations. The number of the capacitors in the boosting circuit can be predetermined to be turned on or off according to the trim code. Accordingly, the voltage boost circuit provides a sufficient boosted word line voltage to a core cell gate with flexibility despite fluctuation of the supply voltage level.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: Disclosed herein is a semiconductor storage device including: a memory core having memory cells to be accessed; and an interface circuit having terminals operable to input and output a chip enable signal adapted to select a chip, at least one control signal adapted to control the chip operation, a clock signal adapted to control the chip I/O operation timing and a series of data including a command, address and data; wherein the interface circuit includes at least one input holding unit adapted to hold the control signal, and the interface circuit processes the control signal after loading it temporarily into the first input holding unit.

Abstract: A semiconductor device includes a fuse part including an antifuse that is connected between a first common node to which a high voltage that is higher than an internal boost voltage is applied and a first node. The fuse part is enabled in response to a program mode selection signal and an address signal so as to fuse the antifuse in response to the high voltage applied to the first common node and to set a voltage level of a second node. A latch circuit is configured to latch an output signal responsive to the voltage level of the second node when the fuse part is in a fused state. A protection circuit is configured to lower a voltage level at the first node when the fuse part is not enabled and the high voltage is applied to the first common node.

Abstract: A precharge circuit of a semiconductor memory apparatus includes a first precharge unit and a second precharge unit. The first precharge unit applies a first core voltage to a pair of local input/output lines, in response to a first precharge signal, to precharge the pair of local input/output lines. The second precharge unit applies a clamp voltage, which is generated using a first supply voltage, to the pair of local input/output lines, in response to the first precharge signal, to precharge the pair of local input/output lines.

Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.

Abstract: Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1iA to flow a current in the memory cell.

Abstract: Provided is a circuit for setting an optimized condition of a semiconductor circuit including a fuse cut signal generator configured to generate a fuse cut signal in response to a first control signal, and a state setting circuit configured to generate an optimization signal in response to a plurality of state control signals and the fuse cut signal.

Abstract: A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.

Abstract: Method and device for providing voltage generation with load-based control are disclosed. The voltage generation can be provided within an electronic device, such as a memory system that provides data storage. In one embodiment, an electrical load imposed on a generated voltage can be monitored and used to dynamically control strength of the generated voltage. For example, for greater electrical loads, the generated voltage can be provided with a greater strength, and for lesser electrical loads, the generated voltage can be provided with a lesser strength. By compensating the generated voltage for the nature of the imposed electrical load, the generated voltage can be provided in a stable manner across a significant range of loads. In the case of a memory system, stability in the generated voltage provides for reduced voltage ripple and thus improved sensing margins. The voltage generation is well suited for use in portable memory products (e.g., memory cards) to generate one or more internal voltages.

Abstract: A memory device and a method of reading the same includes a phase change element having a data state associated therewith that features maintaining the consistency of the data state of the phase change element in the presence of a read current. The memory circuit includes a sense amplifier that defines a sensing node. Circuitry selectively places the bit line in data communication with the sensing node, defining a selected bit line. A current source produces a read current, and a switch selectively applies the read current to the sensing node. Logic is in electrical communication with the sensing node to control the total energy to which the phase change material is subjected in the presence of the read current so that the data state remains consistent.

Abstract: A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.

Abstract: A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that include a MTJ element and a select switching device. A local word line is associated with one row of the plurality of spin-torque MRAM cells and is connected to a gate terminal of the select switching devices of the row of MRAM cells to control activation and deactivation. One gate voltage boosting circuit is placed between an associated global word line and an associated local word line. The gate voltage boosting circuits boost a voltage of a gate of the selected switching device during writing of a logical “1” to the MTJ element of a selected spin-torque MRAM cell.

Abstract: A semiconductor memory device includes a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a bit line control circuit connected to a bit line of the memory cell array to control and detect the bit line voltage in accordance with operation modes, wherein the bit line control circuit comprises a first transistor and a second transistor with a breakdown voltage higher than that of the first transistor, the second transistor being disposed between the first transistor and a bit line in the memory cell array to be serially connected to the first transistor, and wherein a connection node between the first and second transistors is fixed in potential at a data erase time.

Abstract: A voltage regulator with a low noise discharge switch is used in non-volatile memory electronic devices, such as for discharging word lines from negative voltage potentials. The voltage regulator includes a first circuit portion with transistors for transforming a first voltage to a second voltage. The second voltage is applied to a second circuit portion with transistors. The output of the first circuit portion is coupled to ground by a discharge transistor. A third circuit portion with transistors receives a third voltage transformed, starting from the second voltage for biasing at least one word line connected downstream of the third circuit portion. A circuit portion with a discharge switch incorporates the discharge transistor, and further includes a pair of transistors connected in series to each other by an interconnection node. The interconnection node is connected to the body terminal of the discharge transistor.

Abstract: A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.

Abstract: A semiconductor memory device comprises a plurality of memory cells connected to a bit line, and a sense amplifier of the current sense type. The sense amplifier includes an initial charging circuit capable of initially charging the bit line with a suppressed value of current only for a certain starting period during an initial charging period. The sense amplifier detects a value of current flowing in the bit line to decide data read out of each of the memory cells.

Abstract: A memory cell array forms a plurality of control areas in a direction orthogonal to the direction of extension of a bit line. A sense amplifier initially charges a bit line in each control area in the memory cell array with a charging voltage controlled by a respective individual bit-line control signal. Bit-line control signal generator circuits are provided plural in accordance with the control areas in the memory cell array. Each bit-line control signal generator circuit receives the potential on a cell source line in a corresponding control area, individually generates and provides the bit-line control signal in the each control area in accordance with the received voltage on the cell source line in each control area.

Abstract: One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.

Abstract: A phase change memory device includes a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. A plurality of reference bit line and a plurality of clamp bit lines are arranged in the column direction. A cell array block including a phase change resistance cell is arranged where a word line and a bit line intersect. A reference cell array block is formed where a word line and the reference bit line intersect. The reference cell array block is configured to output a reference current. A clamp cell array block is formed where a word line and a clamp bit line intersect. The clamp cell array block is configured to output a clamp current. A sense amplifier is connected to each of the bit lines and is configured to receive a clamp voltage and a reference voltage.

Abstract: A device is fabricated on a flash process semiconductor die. The device includes main memory to store processor information. A cache memory caches a portion of the processor information. A cache controller controls the cache memory. A device interface communicates the processor information to another semiconductor die. Control logic controls the device interface.

Abstract: Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.

Abstract: In general, in one aspect, the disclosure describes an apparatus including a memory cell. Ground biased write control circuitry is used to bias write and writebar bitlines when the memory cell is not performing a write operation. Ground biased read control circuitry is used to bias a read bitline when the memory cell is not performing a read operation.

Abstract: A semiconductor device includes a plurality of memory cells, a temperature budget sensor, and a circuit. The circuit periodically compares a signal from the temperature budget sensor to a reference signal and refreshes the memory cells based on the comparison.

Abstract: A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a control signal which controls enable and disable of the precharging/equalizing unit, wherein the control signal generating unit includes a clamping unit to clamp its source voltage to a voltage level lower than that of its bulk bias.

Abstract: During a stand-by state in which power supply is cut off, a high-voltage power supply control circuit isolates a global negative voltage line transmitting a negative voltage and a local negative voltage line provided corresponding to each respective sub array block from each other and isolates a global ground line and a local ground line transmitting a ground voltage from each other. These local ground line and local negative voltage line are charged to a high voltage level through a high voltage line before cut-off from the corresponding power supply. A leakage current path from a word line to the negative voltage line or the ground line is cut off, so that the word line in a non-selected state can reliably be maintained at a non-selection voltage. Thus, in a low power consumption stand-by mode, data stored in a memory cell can be held in a stable manner.

Abstract: A bitline precharge voltage generator can generate multiple bitline precharge voltages when bitlines are precharged, thereby providing a stable operation regardless of a core voltage used as a high data voltage of a memory cell. In the bitline precharge voltage generator, a core voltage level detecting unit detects a core voltage level, activates a first enable signal when the core voltage level is lower than a specific voltage level, and activates a second enable signal when the core voltage level is higher than the specific voltage level. A bitline precharge voltage generating unit generates a bitline precharge voltage corresponding to half of the core voltage level when the first enable signal is activated. A bitline precharge voltage clamping unit generates a clamped bitline precharge voltage having a constant voltage level when the second enable signal is activated, regardless of the core voltage level.

Abstract: A word line driver is provided for accessing a DRAM cell embedded in a conventional logic process. The DRAM cell includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep n-well. The deep n-well is located in a p-type substrate. A word line couples the drain of the n-channel transistor to the gate of the p-channel access transistor. A negative boosted voltage supply applies a negative boosted voltage to the p-well and the source of the n-channel transistor. The negative boosted voltage is less than ground by an amount equal to or greater than the threshold voltage of the p-channel access transistor. The deep n-well and the p-type substrate are coupled to ground. The various polarities can be reversed in another embodiment.

Abstract: A semiconductor memory device includes an I/O line, a first sense amplifier connected to the first I/O line to amplify a signal applied on the first I/O line in response to a first control signal, a second sense amplifier for amplifying an output signal of the first sense amplifier in response to a second control signal, and a disabling unit for disabling the first control signal in response to an output signal of the second sense amplifier.

Abstract: A method and apparatus for multiple string searching using a ternary content addressable memory. The method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of a stored patterns matching one or more characters of the text string using a state machine, wherein the state machine comprises a ternary content addressable memory (CAM) and wherein the performing comprises comparing a state and one of the plurality of characters with contents of a state field and a character field, respectively, stored in the ternary CAM. In various embodiments, one or more of the following search features may be supported: exact string matching, inexact string matching, single character wildcard matching, multiple character wildcard matching, case insensitive matching, parallel matching and rollback.

Abstract: A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent on gate voltages as opposed to P/N ratios.

Abstract: Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.

Abstract: A device is fabricated on a flash process semiconductor die. The device includes main memory to store processor information. A cache memory caches a portion of the processor information. A cache controller controls the cache memory. A device interface communicates the processor information to another semiconductor die. Control logic controls the device interface.

Abstract: A memory circuit includes a controlled current source coupled to an input to a nonvolatile cell, and a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the controlled current source via the nonvolatile cell.

Abstract: A content-addressable memory circuit includes a first local bit line coupled to a first memory location, a second local bit line coupled to a second memory location, a global bit line coupled to the first and second local bit lines and a global bit line accelerator coupled to the first and second local bit lines and the global bit line. The global bit line accelerator sets the second local bit line to a first logical value depending on a signal from the first local bit line. In this way, the global bit line accelerator accelerates the evaluation phase of operation of the second local bit line.

Abstract: An SRAM device is disclosed, which comprises a plurality of rows of SRAM cells and a line-buffer SRAM cell. Each row of SRAM cells is controlled by a word line. The line-buffer SRAM cell is coupled to the rows of SRAM cells and controlled by a read enable line. The signal on the read enable line is activated after the signal on the word line is activated, and part of the activated signal on the read enable line overlaps with the activated signal on the word line. The power provided to the line-buffer SRAM cell is selectively cut off.