Abstract: A static memory circuit includes memory cells arranged in a matrix of word lines and bit lines, and a reset circuit for resetting each pair of bit lines to have an equivalent potential in response to a change in a row address signal. The reset circuit generates a reset signal at a first time a certain time period after a first change of the row address signal and terminates the reset signal at a second time when a second change of the row address signal is detected. Thus, data destruction during reading is prevented.

Abstract: A digital delay system employs a phase-locked loop to control a recall address generator. The phase-locked loop comprises a subtractor for determining the difference between the store address and the recall address and for producing a phase signal corresponding to this difference. The phase signal is directed to a voltage controlled oscillator for controlling the rate at which the recall address generator recalls data from a memory. A delay length is introduced as a phase error into the phase-locked loop. Input data is stored in a memory at a fixed rate, and recalled from the memory at a rate determined by the phase-locked loop. When the error signal is zero, the recall address rate will equal the store address rate and the respective addresses will be equal.

Abstract: An on-chip apparatus for generation of timing signals for a large scale integrated (LSI) chip or semiconductor memory array is disclosed. This apparatus may be used both during the production testing of the memory and during normal functional operation. In the testing environment it allows use of much less expensive peripheral test equipment, while also providing for much greater accuracy in determination of whether or not the memory array meets its timing specification. Use during normal functional operation (subsequent to use in the test environment) provides for a guarantee of defect free operation.

Abstract: Memory access time, noise and costs are substantially reduced while reliability is increased by replacing fixed delay lines with a dynamic delay. This dynamic delay is placed on the same integrated circuit as the remainder of the memory access circuitry to eliminate tracking problems associated with off-chip delay lines. The dynamic delay element is activated after all of the row address strobe (RAS) bits have been generated. These RAS bits serve to strobe the row column address bits initially present on the address bus into the memory. After the delay time has elapsed an address multiplexor switches column address bits onto the address bus to replace the prior row address bits. As soon as this switch is completed column address strobe (CAS) bits are generated to strobe the column address bits into the memory.

Abstract: A write protection circuit for a control register includes a first logic circuit which provides a write enable signal to the control register in response to simultaneously receiving a register select signal, a write control signal and an enable signal. A second logic circuit provides the enable signal to the first logic circuit only until the first logic circuit first provides the write enable signal. The second logic circuit will also cease to provide the enable signal in response to a time-out signal. In response to either a reset signal or a test signal, the second logic circuit will again provide the enable signal.

Abstract: Disclosed is a semiconductor memory device which is one of three types of semiconductor memory devices, one operable only in page mode, one operable only in nibble and one operable selectively in page mode or nibble mode, being obtained from a partially unconnected semiconductor memory device through alternations in a portions in wiring. The semiconductor memory device includes first and second internal column address strobe signal generator. The second internal column address strobe signal generator has at the first stage thereof a NAND circuit one of inputs to which determines the type of the semiconductor memory device depending on which of three kinds of signals is selected as the input. Selection of such an input is effected by an aluminum wiring process using a mask. Such selection of the input causes variation in the input response characteristics of the output of the second internal column address strobe signal generator, thus providing a desired response appropriate for the selected mode or modes.

Abstract: A signal transmitting circuit which can transmit an input signal with a variable delay time is disclosed. The circuit comprises a series circuit of a transistor and a load element and a variable time constant circuit coupled to a control electrode of the transistor whose time constant value is changed in response to a control signal.

Abstract: A semiconductor device comprises a plurality of data supply circuits, output circuits for producing a plurality of data delivered from the data supply circuit and delay circuit for transferring respective data from each data supply circuit to a different output circuit with a different delay time. Each data supply circuit includes a plurality of row lines, a row decoder for selecting the row line in response to an address signal, a plurality of memory cell arrays including memory cells selectively driven by the row line and storing data, a plurality of column lines to receive data read out from the memory cell array, and a column decoder for selecting said column lines. The delay circuit prevents a plurality of data from being simultaneously outputted.

Abstract: A delay circuit including an even number of memory devices, for example two, reading from one memory device, while writing to the other. Sequences of bit addresses are generated for writing and reading, with an offset between the sequences. For the case of two memory devices, each address sequence is applied alternately to the one and then the other memory device. Importantly, if each memory device has an even number n of storage locations, then, preferably, only (n-1) of these are used in the generated sequences of addresses. This has the result that the circuit can write to and read from all of the memory locations in the memory devices. Thus, the maximum delay possible in the circuit of the invention is nearly the total number of bits in the multiple memory devices, and the circuit is capable of handling data at the maximum operating rate of the memory devices.

Abstract: A drive circuit which includes a plurality of load MOS transistors coupled in series between a positive power source terminal and a node point, a plurality of drive MOS transistors coupled in parallel between a ground terminal and the node point, a static type bootstrap buffer circuit connected at the input terminal to the node point, and a gate control circuit for controlling the conduction states of the load and drive MOS transistors. The gate control circuit renders the load MOS transistors conductive, and then renders the drive MOS transistors nonconductive after the load MOS transistors are rendered fully conductive.

Abstract: A semiconductor memory device including static memory cells connected at intersections of word lines and pairs of bit lines, in which writing is carried out by changing the potentials of the paired bit lines according to writing data of binary digits "1" and "0" and turning on one transistor of a memory cell while turning off the other transistor of the cell. A characteristic feature of the invention is that, according to the write data, one of the paired bit lines is maintained at a low level while the other bit line is simultaneously maintained at a high level, and the period of maintenance of the high level is shorter than the period of maintenance of the low level.

Abstract: There is provided a signal propagating device for receiving an input signal at an input end thereof and supplying the input signal to a plurality of memory cells arranged in one row. The signal propagating device includes a word line connected to transmit the input signal and having a plurality of line segments electrically coupled to the memory cells. A preceding one of the line segments is formed to have a larger average width than a succeeding one of the line segments.

Abstract: A memory device provided with an improved control circuit for enabling effective interface with a CPU. The device comprises a memory circuit, a first terminal for receiving a strobe signal for placing the memory circuit in an accessed state, a second terminal for receiving a chain of clock signals, digital counter for counting the clock signals in response to the strobe signal having a plurality of different value of count, output terminals, a circuit for selectively deriving a count signal from one of the count output terminal according to a programmed state, and a ready signal generating circuit for generating a ready signal for indicating the completion of the access operation of the memory circuit in response to the count signal.

Abstract: A semiconductor memory having an address buffer (10), row decoder (12), word lines (16), bit line (20) and sense amplifier (22) for accessing individual memory cells in an array of memory cells. In order to emulate worst case delays experienced in the word lines in accessing the last cells in the rows in order to prevent the sense amplifiers (22) from reading the bit lines (20) too soon, a tunable delay circuit (30) delays actuation of the sense amplifier. This circuit is divided into a plurality of impedance section with associated parasitic capacitance where groups of sections are bypassed by switching devices such as MOS transistors. The delay of a signal propagating through this tunable delay circuit can be varied by bypassing varying numbers of the sections with the switching devices.

Abstract: A disk mastering preview system utilizes an original audio signal from an audio source for previewing signals to be recorded by a disk lathe. Delayed audio signals corresponding to the original audio signals are produced for recording by the disk lathe a predetermined time delay thereafter. The original audio signals are sampled periodically by a sample and hold circuit to produce analog sample signals indicative of the signals sampled. An analog to digital converter converts the analog sample signals to corresponding digital sample signals. Successive digital sample signals are written into successively addressed memory locations and read out an adjustable predetermined number of memory addresses subsequently. A digital to analog converter converts the digital sample signals read out of memory into analog signals for recording. The predetermined number of addresses is set in a time delay register which produces a signal indicative of the number.

Abstract: An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. In a programming mode of operation, the application of high voltages to the row and column lines is controlled to prevent programming voltage from reaching a selected column until after all transistors in a row are turned on by programming voltage on a row line. This prevents unwanted programming conditions.

Abstract: A memory device utilizing metal oxide semiconductor field effect transistors (MOS FETs) formed in a semiconductor substrate. The memory device is so improved as to be accessed without a delay and as not to behave erroneously, in spite of a potential variation of data line or the semiconductor substrate. It comprises a plurality of row lines for supplying input signals, a plurality of column lines for supplying output signals, decoders for selecting any one of these lines, a plurality of memory cells connected to the row and column lines in a specific manner, a voltage sensing circuit connected to the column lines, a first potential source connected to the column lines, a second potential source for supplying the memory cells with a source voltage, and means for holding the column lines at a potential substantially equal to the voltage supplied from the second potential source when the potential of the column lines or the substrate varies.

Abstract: A bipolar memory circuit is provided with a delay circuit which receives a write enabling signal, a gate circuit which detects the coincidence between an input signal and an output signal of the delay circuit, and a circuit which is started by an output signal of the gate circuit and which provides a pulse signal of a fixed time. The operation of a write driver circuit in the bipolar memory circuit is controlled by the pulse signal. Noise interfering in the write enabling signal are neglected by the use of the delay circuit and the gate circuit. The pulse width of the write enabling signal is permitted to be made smaller than the pulse width of the pulse signal required by the write driver circuit.

Abstract: An electronic memory comprises a plurality of memory cells arranged in an array of rows and column, row address circuitry, column address circuitry, circuitry for sensing the logic states of the cells, and circuitry for delaying addressing of a selected column until after an addressed row has achieved a voltage level suitable for the sensing circuitry to sense. By so delaying the addressing of the selected column, the time required to read information out is reduced substantially--typically by a factor of two for a 1K or 2K.times.8-bit static memory.

Abstract: A memory cell is connected to a word line and a data line. A first pulse is applied from an address decoder to the memory cell, and data read out from the memory cell is detected by a sense amplifier to which a second pulse is supplied. There is provided a pulse supply means for supplying the first and second pulses, which includes a delay line supplied with the first pulse and a pulse generator circuit composed of MOS transistors which receives as an input a delayed pulse from the delay line and delivers the second pulse. If the word line is formed of, for example, a polysilicon layer, then the delay line is also formed of a polysilicon layer so that the delay line may have substantially the same signal delay characteristic as that of the word line. Since the signal delay characteristics of the word and delay lines may vary correspondingly to each other in accordance with changes of device parameters, the phase difference between the first and second pulses can be adjusted for optimum results.

Abstract: An MOS dynamic random access memory (RAM) includes an array of memory cells arranged in rows and columns. The array is divided into two or more sub-arrays. During an operating cycle latching of the sense amplifiers in the sub-arrays is staggered to avoid coincidence of current peaks each arising when the sense amplifiers in one of the sub-arrays are simultaneously latched. Latching takes place first in a sub-array in which a cell is selected. Recovery of the column conductors in the sub-arrays is also staggered to avoid coincidence of current peaks each occurring when one of the sub-arrays is recovered. The sub-array in which a cell is selected is recovered last.

Abstract: A method for storing a binary signal in a high speed flip-flop memory. The apparatus includes a clock signal selecting device connected to control a pair of memory elements in cascade. Data is introduced into the first memory element under the control of a first control signal from the clock signal selecting device and is transferred to the second memory element under the control of a second control signal from the clock signal selecting device. A single output of a clock pulse generator is applied via parallel lines, one of which includes a delay element, to a logic gate to provide spaced time pulses which are applied to the clock signal selecting device. The clock signal selecting device includes a pair of two input AND gates, each of which are connected to receive at one input the spaced time pulses and at the second input a clock signal selecting signal derived from the output of a JK flip-flop having its sync input connected to receive the spaced time pulses.

Abstract: A clocked memory comprising a memory matrix having a plurality of memory cells arranged in rows and columns on a semiconductor substrate; a plurality of word select lines in said memory matrix, a plurality of bit lines crossing said select lines and connecting to said memory cells in each column; a drive circuit for driving said word select lines; a plurality of presence amplifiers connected to said bit lines; and a sense clock line parallel to said word select lines and connected to a gate of a transistor in said presence amplifier; and a presense drive circuit connected to said sense clock line and operated by a clock signal, said presense drive circuit having a transistor with controlled charging capability so as to conduct said transistor responsive to the charge of the memory cell in said each column.

Abstract: An array of parallel FET load circuits on an IC (integrated circuit) chip can have their respective signal delays equalized where their nodal capacitances are different or alternately can have their signal delays set for different durations to meet the needs of a subsequent circuit, by adjusting the current driving capacity of a driver driving each circuit to meet the desired delay requirements thereof.

Abstract: An MOS RAM employing capacitive storage cells where each cell includes a refreshing network which receives an AC signal for refreshing is disclosed. The refreshing signal is applied to the refreshing network through a depletion mode device which acts as a variable capacitor. Lower capacitance is provided when one binary state is stored in the cell, thus preventing undesirable charge from being retained within the cell when the opposite binary state is written into the cell. The refreshing signal is completely asynchronous with memory timing signals; thus, the memory may be accessed at any time.