Signals Patents (Class 365/191)
  • Patent number: 11417377
    Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chieh Chiu, Chia-En Huang, Fu-An Wu, I-Han Huang, Jung-Ping Yang
  • Patent number: 11373692
    Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: June 28, 2022
    Assignee: MediaTek Inc.
    Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Jou-Ling Chen
  • Patent number: 11354064
    Abstract: Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael Dieter Richter, Markus Balb
  • Patent number: 11340786
    Abstract: A shared data transfer clock is used among double data rate memory ranks. A memory controller processes incoming memory access commands destined for at least one of a plurality of double data rate memory ranks and determines when a target DDR memory rank is out of synchronization with respect to the shared data transfer clock and a memory clock. In response to determining that the target DDR memory rank is out of synchronization, the memory controller determines whether the non-target DDR memory rank is out-of-synchronization with respect to the shared data transfer clock and the memory clock, and issues a data transfer clock synchronization command to the target DDR memory rank in response to determining that the non-target DDR memory rank is out-of-synchronization with respect to the shared data transfer clock and the memory clock.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: May 24, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Tahsin Askar
  • Patent number: 11221913
    Abstract: Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Randall J. Rooney, Matthew A. Prather
  • Patent number: 11217301
    Abstract: Embodiments herein include a first line, wherein the first line is complementary to a second line; a voltage generator configured to generate a first supply voltage, a second supply voltage and a third supply voltage, the third supply voltage is lower than the second supply voltage, the voltage generator further comprises a transistor structure with a plurality of transistors electrically connected in parallel from the first supply voltage to a supply output node that provides the second supply voltage; a memory cell electrically coupled to the first and second lines, the memory cell further comprises two cross-coupled transistor strings connected from the first supply voltage to a ground voltage; a pre-charger with a first pre-charger transistor cross-coupled to a second pre-charger transistor, the pre-charger is configured to pre-charge the first and second lines to a level of a source voltage.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hua-Hsin Yu, Hau-Tai Shieh
  • Patent number: 11183239
    Abstract: An operation method of a resistive memory device includes receiving write data and an address; determining whether the write data is in a first state or in a second state; applying a first pulse to a target memory cell corresponding to the address, among a plurality of memory cells, when the write data is in the first state; and selectively applying, when the write data is in the second state, a second pulse to the target memory cell according to a comparison result of the write data and pre-read data which is pre-stored data read from the target memory cell.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Ho-Seok Em
  • Patent number: 11163495
    Abstract: Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Timothy P. Finkbeiner
  • Patent number: 11120868
    Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Yuan Chen, Che-Ju Yeh, Hau-Tai Shieh, Cheng Hung Lee, Hung-Jen Liao, Sahil Preet Singh, Manish Arora, Hemant Patel, Li-Wen Wang
  • Patent number: 11069394
    Abstract: Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Thomas H. Kinsley
  • Patent number: 10991420
    Abstract: A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
  • Patent number: 10964363
    Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 30, 2021
    Assignee: MediaTek Inc.
    Inventors: Bo-Wei Hsieh, Chia-Yu Chan, Jou-Ling Chen
  • Patent number: 10956315
    Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fa-Long Luo, Jaime Cummins, Tamara Schmitz, Jeremy Chritz
  • Patent number: 10943640
    Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, George Vergis, James A. McCall, Ge Chang
  • Patent number: 10930746
    Abstract: A differential type non-volatile memory circuit comprising a differential sensing circuit, a differential data line pair, a memory cell array, and a differential bit line pair is provided. The differential sensing circuit has a differential input terminal pair and a differential output terminal pair. The differential data line pair is electrically connected to the differential input terminal pair of the differential sensing circuit. The memory cell array has at least one differential non-volatile memory cell configured to store data. The differential bit line pair is electrically connected between the memory cell array and the differential data line pair. When logic states of the differential output terminal pair start to be different in a read operation phase of the memory cell array, the differential sensing circuit and the differential data line pair are disconnected.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 23, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Chen-Hao Po, Cheng-Te Yang
  • Patent number: 10896721
    Abstract: The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (?T denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ?T is more than a tDQSS then ?T is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: January 19, 2021
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Nitin Kumar Chhabra
  • Patent number: 10885968
    Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Penney
  • Patent number: 10841879
    Abstract: A user terminal includes a WiFi card and a communications card. The WiFi card includes a first electronic controller, an antenna in communication with the first electronic controller, the antenna of the WiFi card configured to receive a signal from a remote device. The communications card includes a second electronic controller, a connector configured to connect to an external communications device, and a power switch in communication with the second electronic controller and the connector, the second electronic controller configured to control the power switch to enable or disable power through the connector upon receiving instructions from the first electronic controller, based on the signal received by the antenna of the WiFi card.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 17, 2020
    Assignee: HUGHES NETWORK SYSTEMS, LLC
    Inventor: Emanuel Harrington
  • Patent number: 10832744
    Abstract: A read-only memory (ROM) device includes a memory cell that is electrically coupled to a bitline (BL) or to a BL which represents a complement of the BL. The ROM device precharges the BL and the BL to a first logical value. The ROM device activates the memory cell which discharges the BL when the memory cell is coupled to the BL or discharges the BL when the memory cell is coupled to the BL. The ROM device reads the first logical value as being stored within the memory cell when the BL is less than the BL. Otherwise, the ROM device reads the second logical value as being stored within the memory cell when the BL is greater than the BL.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuoyuan Hsu, Jacklyn Chang
  • Patent number: 10832762
    Abstract: A circuit for reducing static power in SRAM and methods for using the same are disclosed. In one embodiment, a circuit for reducing static power in SRAM includes a plurality of memory blocks, where a memory block in the plurality of memory blocks includes a plurality memory banks, where a memory bank in the plurality of memory banks includes a plurality bit cells. The circuit further includes a bias circuit configured to produce a bias voltage to a row of bit cells, where the bias circuit is coupled to a circuit ground terminal of the row of bit cells in the plurality of bit cells, and a controller configured to control the bias circuit to produce a first set of bias settings in an access mode and control the bias circuit to produce a second set of bias settings in a standby mode of the SRAM.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: November 10, 2020
    Assignee: Ambient Scientific, Inc.
    Inventor: Gajendra Prasad Singh
  • Patent number: 10727840
    Abstract: Memory systems can include shifting an ODT information signal prior to passing it through a cloned DLL delay line. The shifted ODT information passes through a cloned DLL delay line to move it into a DLL domain. Meanwhile, a clock gate can use a command indication to select whether to provide a clock signal to a DLL delay line. The clock gate can block the clock signal in the absence of a read or write operation and can pass the clock signal during read or write operations. When the DLL delay line receives the clock signal, it delays the clock signal to be in the DLL domain. By locating the ODT shifter before the cloned DLL delay line, as opposed to after it, the ODT shifter doesn't need a signal passed through the DLL delay line. Preventing the clock signal from passing through the DLL delay line reduces power consumption.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kallol Mazumder
  • Patent number: 10665289
    Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 26, 2020
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Lei Luo, Liji Gopalakrishnan
  • Patent number: 10650869
    Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akio Sugahara, Yoshikazu Harada, Shoichiro Hashimoto
  • Patent number: 10643672
    Abstract: A memory device is provided. The memory device comprises a memory array and circuitry configured to determine one or more settings for the memory array corresponding to a powered-on state of the memory device, to store the one or more settings in a non-volatile memory location, and in response to returning to the powered-on state from a reduced-power state, to read the one or more settings from the non-volatile memory location.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan S. Parry, George B. Raad, James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10572183
    Abstract: A data processing system includes a memory and a data processor. The data processor is connected to the memory and adapted to access the memory in response to scheduled memory access requests. The data processor has power management logic that, in response to detecting a memory power state change, determines whether to retrain or suppress retraining of at least one parameter related to accessing the memory based on an operating state of the memory. The power management logic further determines a retraining interval for retraining the at least one parameter related to accessing the memory, and initiates a retraining operation in response to the memory power state change based on the operating state of the memory being outside of a predetermined threshold.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: February 25, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sonu Arora, Guhan Krishnan, Kevin Brandl
  • Patent number: 10566037
    Abstract: A storage device comprises a controller, such as an ASIC controller, and one or more NAND flash memory devices. The controller comprises a differential receiver and a delay locked loop circuit. During read and write operations, the controller is configured to vary a delay of a data strobe signal by an interval across a width of a data window using the delay locked loop circuit, and to compare a write pattern to a read pattern for each delayed interval to determine the timing margins of the storage device. During read and write operations, the controller is further configured to apply a reference voltage to a host interface or a memory interface, increment and decrement the reference voltage by a set value, and compare a write pattern to a read pattern for each varied reference voltage value to determine the voltage margins of the storage device.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC
    Inventors: Shajith Musaliar Sirajudeen, Taninder Sijher
  • Patent number: 10553272
    Abstract: One controller for controlling operation of a memory device includes an output circuit configured to supply a chip select signal, an address signal, a command signal, and a clock signal to the memory device, and a data processing circuit configured to process read data and write data through a data terminal based on the chip select signal, the address signal, the command signal, and the clock signal supplied by the output circuit. The controller is configured to supply the address signal and the command signal to the memory device a predetermined duration after the output circuit supplies the chip select signal.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 4, 2020
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Chikara Kondo
  • Patent number: 10497405
    Abstract: A memory is described. The memory includes a storage cell. The memory also includes a read bit line coupled to the storage cell. The memory also includes at least one N type pre charge transistor coupled between the read bit line and a power supply node. The at least one N type pre-charge transistor is to pre-charge the read bit line. The memory also includes at least one P type pre charge transistor that is also coupled between the read bit line and the power supply node. The at least one P type pre-charge transistor is to pre-charge the read bit line with the at least one N type transistor.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Rajiv Kumar, Kuan Cheng Tang
  • Patent number: 10460775
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Patent number: 10439740
    Abstract: A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: October 8, 2019
    Assignee: Rambus Inc.
    Inventors: Jun Kim, Wayne S. Richardson, Glenn Chiu
  • Patent number: 10438651
    Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Penney
  • Patent number: 10388395
    Abstract: A storage device includes a nonvolatile memory device that detects loop counts of state pass loops of at least one target state of a plurality of target states, and generates state loop count information (SLCI) indicative of whether a program operation is successful based on the detected loop count of the state pass loops, during a program operation of selected memory cells; and a storage controller that makes a request to the nonvolatile memory device for the state loop count information in response to detection of an operation condition or an external command, and assigns a memory block in which the selected memory cells are included as a bad block based on the state loop count information from the nonvolatile memory device.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungduk Lee, Young-Seop Shim
  • Patent number: 10388348
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell having a first variable resistance element, a second memory cell having a second variable resistance element, and a first circuit which controls writing to the first memory cell and the second memory cell. The first circuit receives a first command instructing writing to the first memory cell, after receiving the first command, receives a second command instructing writing to the second memory cell, and after receiving the second command, performs writing to the second memory cell when performing writing to the first memory cell.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: August 20, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Shimizu
  • Patent number: 10347347
    Abstract: An apparatus is provided which comprises: a buffer to receive first data from a host, and output the first data with configurable delay; and one or more circuitries to: compare the first data from the host with second data that is accessible to the apparatus, wherein the second data is substantially a copy of the first data, and calibrate the delay of the buffer, based at least in part on the comparison of the first data and the second data.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Sriram Balasubrahmanyam
  • Patent number: 10324490
    Abstract: A device with an I/O interface includes a replica clock distribution path matched to a clock distribution path of an unmatched receiver circuit. The device can monitor changes in delay in the replica path, and adjust delay in the real clock distribution path in response to the delay changes detected in the replica path. The receiver circuit includes a data path and a clock distribution network in an unmatched configuration. A ring oscillator circuit includes a replica clock distribution network matched to the real clock distribution network. Thus, delay changes detected for the replica clock distribution network indicates a change in delay in the real clock distribution network, which can be compensated accordingly.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventor: Christopher P. Mozak
  • Patent number: 10297292
    Abstract: A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascade configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: May 21, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Conte, Mario Micciche', Santi Nunzio Antonino Pagano
  • Patent number: 10276232
    Abstract: A sense amplify enable (SAE) signal is generated on a SAE line by receiving a trigger signal at a first circuit portion coupled to a first domain power supply and a second circuit portion coupled to a second domain power supply. The second domain power supply is separate and distinct from the first domain power supply. The first circuit portion and the second circuit portion are each further coupled to the SAE line for carrying the SAE signal. For a first period of time, a first portion of the SAE signal is generated based on the first domain power supply using the first circuit portion. And, for second period of time, a second portion of the SAE signal is generated based on the second domain power supply using a second circuit portion.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hao-I Yang, Tsung-Hsien Huang
  • Patent number: 10268122
    Abstract: Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Silvio E. Bou-Ghazale, Abhik Ghosh, Niti Goel
  • Patent number: 10250659
    Abstract: Client buffer thresholds are dynamically adjusted to provide quick start up and smooth playback in a variety of network conditions. In some examples, multiple buffer configurations are available. An initial buffer configuration may be used in typical circumstances and will yield good behavior in most cases. A modified buffer configuration can be used when limited available network resources prevent smooth playback. In some embodiments, a client buffer configuration is continuously adapted based on network throughput and data transfer rates.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 2, 2019
    Assignee: MobiTV, Inc.
    Inventors: Kent Karlsson, Tommy Isaksson
  • Patent number: 10242723
    Abstract: A method and apparatus for performing a background calibration in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller is coupled to receive data during reads from the memory on a functional data path and a duplicate data path. The memory controller further includes calibration circuitry. During reads of data conducted during normal operation, the calibration circuit calibrates a first delay locked loop (DLL) in the duplicate data path. A second DLL, in the functional data path, may be adjusted based on the calibrations conducted in the duplicate data path.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 26, 2019
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Fabien S. Faure
  • Patent number: 10162003
    Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 25, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10147493
    Abstract: A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Parvinder Kumar Rana, Lava Kumar Pulluru, Manish Chandra Joshi
  • Patent number: 10083725
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: September 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Patent number: 10062421
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: June 17, 2017
    Date of Patent: August 28, 2018
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Patent number: 10002667
    Abstract: A memory device may include N memory areas that are divided into a first group and a second group, and are selected by area selection signals corresponding to the N memory areas among N area selection signals, N*M pipe latches that store output data of memory areas corresponding to the N*M pipe latches among the N memory areas, a first pipe output signal generation circuit that generates 1-1th to 1-Mth pipe output signals of pipe latches, which correspond to memory areas belonging to the first group, in response to an area selection signal corresponding to a predetermined memory area of memory areas, and a second pipe output signal generation circuit that generates 2-1th to 2-Mth pipe output signals of pipe latches, which correspond to memory areas belonging to the second group, in response to an area selection signal corresponding to a predetermined memory area of memory areas.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: June 19, 2018
    Assignee: SK Hynix Inc.
    Inventors: Sang-Oh Lim, Jong-Tai Park
  • Patent number: 9886994
    Abstract: One semiconductor device includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal is activated. The latency control circuit activates a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles. The command receiver is activated based on a first control signal. The first control signal is activated in response to the first internal chip select signal. The first control signal is deactivated in response to the second control signal.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: February 6, 2018
    Assignee: LONGITUDE SEMICONDUCTORS S.A.R.L.
    Inventor: Chikara Kondo
  • Patent number: 9865318
    Abstract: A transmission circuit may be provided. The transmission circuit may include a strobe control circuit and an output driver. The strobe control circuit may generate strobe driving signals based on information and a clock signal. The output driver may generate a strobe signal by driving a signal transmission line. The transmission circuit may drive the signal transmission line to a specified level for a predetermined time after transmission of the strobe signal is completed.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: January 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Kyung Hoon Kim, Sun Ki Cho
  • Patent number: 9865317
    Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: January 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shuichi Ishibashi, Kazutaka Miyano, Hiroki Fujisawa
  • Patent number: 9865335
    Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
    Inventors: Pankaj Aggarwal, Jui-Che Tsai, Cheng Hung Lee, Chien-Yuan Chen, Chiting Cheng, Hau-Tai Shieh, Yi-Tzu Chen
  • Patent number: 9761330
    Abstract: A semiconductor device may include a refresh counter configured to output a plurality of refresh addresses by counting a refresh signal; a check signal generator configured to generate a check signal according to a logic level of any one specific refresh address among the plurality of refresh addresses during a refresh operation, and output the check signal in response to a redundancy check pulse signal; a redundancy checker configured to store information on whether a redundancy cell was used, in response to the check signal, the redundancy check pulse signal and the plurality of refresh addresses, and output a word line control signal according to whether the redundancy cell was used; and a refresh controller configured to control a row address for selectively enabling a word line and a redundancy word line of a cell array in response to the word line control signal.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: September 12, 2017
    Assignee: SK hynix Inc.
    Inventor: Jae Il Kim