Signals Patents (Class 365/191)
  • Patent number: 10347347
    Abstract: An apparatus is provided which comprises: a buffer to receive first data from a host, and output the first data with configurable delay; and one or more circuitries to: compare the first data from the host with second data that is accessible to the apparatus, wherein the second data is substantially a copy of the first data, and calibrate the delay of the buffer, based at least in part on the comparison of the first data and the second data.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Sriram Balasubrahmanyam
  • Patent number: 10324490
    Abstract: A device with an I/O interface includes a replica clock distribution path matched to a clock distribution path of an unmatched receiver circuit. The device can monitor changes in delay in the replica path, and adjust delay in the real clock distribution path in response to the delay changes detected in the replica path. The receiver circuit includes a data path and a clock distribution network in an unmatched configuration. A ring oscillator circuit includes a replica clock distribution network matched to the real clock distribution network. Thus, delay changes detected for the replica clock distribution network indicates a change in delay in the real clock distribution network, which can be compensated accordingly.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventor: Christopher P. Mozak
  • Patent number: 10297292
    Abstract: A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascade configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: May 21, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Conte, Mario Micciche', Santi Nunzio Antonino Pagano
  • Patent number: 10276232
    Abstract: A sense amplify enable (SAE) signal is generated on a SAE line by receiving a trigger signal at a first circuit portion coupled to a first domain power supply and a second circuit portion coupled to a second domain power supply. The second domain power supply is separate and distinct from the first domain power supply. The first circuit portion and the second circuit portion are each further coupled to the SAE line for carrying the SAE signal. For a first period of time, a first portion of the SAE signal is generated based on the first domain power supply using the first circuit portion. And, for second period of time, a second portion of the SAE signal is generated based on the second domain power supply using a second circuit portion.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hao-I Yang, Tsung-Hsien Huang
  • Patent number: 10268122
    Abstract: Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Silvio E. Bou-Ghazale, Abhik Ghosh, Niti Goel
  • Patent number: 10250659
    Abstract: Client buffer thresholds are dynamically adjusted to provide quick start up and smooth playback in a variety of network conditions. In some examples, multiple buffer configurations are available. An initial buffer configuration may be used in typical circumstances and will yield good behavior in most cases. A modified buffer configuration can be used when limited available network resources prevent smooth playback. In some embodiments, a client buffer configuration is continuously adapted based on network throughput and data transfer rates.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 2, 2019
    Assignee: MobiTV, Inc.
    Inventors: Kent Karlsson, Tommy Isaksson
  • Patent number: 10242723
    Abstract: A method and apparatus for performing a background calibration in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller is coupled to receive data during reads from the memory on a functional data path and a duplicate data path. The memory controller further includes calibration circuitry. During reads of data conducted during normal operation, the calibration circuit calibrates a first delay locked loop (DLL) in the duplicate data path. A second DLL, in the functional data path, may be adjusted based on the calibrations conducted in the duplicate data path.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 26, 2019
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Fabien S. Faure
  • Patent number: 10162003
    Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 25, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10147493
    Abstract: A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Parvinder Kumar Rana, Lava Kumar Pulluru, Manish Chandra Joshi
  • Patent number: 10083725
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: September 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Patent number: 10062421
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: June 17, 2017
    Date of Patent: August 28, 2018
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Patent number: 10002667
    Abstract: A memory device may include N memory areas that are divided into a first group and a second group, and are selected by area selection signals corresponding to the N memory areas among N area selection signals, N*M pipe latches that store output data of memory areas corresponding to the N*M pipe latches among the N memory areas, a first pipe output signal generation circuit that generates 1-1th to 1-Mth pipe output signals of pipe latches, which correspond to memory areas belonging to the first group, in response to an area selection signal corresponding to a predetermined memory area of memory areas, and a second pipe output signal generation circuit that generates 2-1th to 2-Mth pipe output signals of pipe latches, which correspond to memory areas belonging to the second group, in response to an area selection signal corresponding to a predetermined memory area of memory areas.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: June 19, 2018
    Assignee: SK Hynix Inc.
    Inventors: Sang-Oh Lim, Jong-Tai Park
  • Patent number: 9886994
    Abstract: One semiconductor device includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal is activated. The latency control circuit activates a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles. The command receiver is activated based on a first control signal. The first control signal is activated in response to the first internal chip select signal. The first control signal is deactivated in response to the second control signal.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: February 6, 2018
    Assignee: LONGITUDE SEMICONDUCTORS S.A.R.L.
    Inventor: Chikara Kondo
  • Patent number: 9865317
    Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: January 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shuichi Ishibashi, Kazutaka Miyano, Hiroki Fujisawa
  • Patent number: 9865318
    Abstract: A transmission circuit may be provided. The transmission circuit may include a strobe control circuit and an output driver. The strobe control circuit may generate strobe driving signals based on information and a clock signal. The output driver may generate a strobe signal by driving a signal transmission line. The transmission circuit may drive the signal transmission line to a specified level for a predetermined time after transmission of the strobe signal is completed.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: January 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Kyung Hoon Kim, Sun Ki Cho
  • Patent number: 9865335
    Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
    Inventors: Pankaj Aggarwal, Jui-Che Tsai, Cheng Hung Lee, Chien-Yuan Chen, Chiting Cheng, Hau-Tai Shieh, Yi-Tzu Chen
  • Patent number: 9761330
    Abstract: A semiconductor device may include a refresh counter configured to output a plurality of refresh addresses by counting a refresh signal; a check signal generator configured to generate a check signal according to a logic level of any one specific refresh address among the plurality of refresh addresses during a refresh operation, and output the check signal in response to a redundancy check pulse signal; a redundancy checker configured to store information on whether a redundancy cell was used, in response to the check signal, the redundancy check pulse signal and the plurality of refresh addresses, and output a word line control signal according to whether the redundancy cell was used; and a refresh controller configured to control a row address for selectively enabling a word line and a redundancy word line of a cell array in response to the word line control signal.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: September 12, 2017
    Assignee: SK hynix Inc.
    Inventor: Jae Il Kim
  • Patent number: 9754656
    Abstract: In some embodiments, disclosed herein are approaches for facilitating voltage controlled slaved (or replica) clock circuits such as voltage controlled delay lines (VCDLs) off of a master clock generator. In such systems, one or more control (or bias) voltages are generated to control a master clock generator such as a master DLL. One or more “slave” circuits may be controlled off of the master's control voltage so that their clocks replicate desired traits of the master clock.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventor: Stephen J. Spinks
  • Patent number: 9740642
    Abstract: Methods and electronic devices for adjusting an operating frequency of a memory are disclosed. The method includes: transmitting to the memory a first command that instructs the memory to hold the data information in the memory; transmitting to the memory controller a second command that adjusts the first frequency of the memory controller to a second frequency; and transmitting to the memory a third command that instructs the memory to exchange the data information according to the second frequency of the memory controller. According to the disclosure, it is possible to dynamically adjust the frequency of the memory during operation, avoiding the need of the user to turn off and then turn on the electronic device to adjust the frequency of the memory.
    Type: Grant
    Filed: September 5, 2011
    Date of Patent: August 22, 2017
    Assignees: LENOVO (BEIJING) LIMITED, BEIJING LENOVO SOFTWARE LTD.
    Inventors: Jingang Peng, Xiaogang Wang, Xiaoyi Feng
  • Patent number: 9728246
    Abstract: Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a plurality of transistors that are brought into a first operation state when at least one of the first and second command signals is activated, and an output gate circuit that receives a first signal output from the internal circuit, the output gate circuit being configured to pass the first signal when the second command signal is deactivated and to block the first signal when the second command signal is activated.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: August 8, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Keisuke Fujishiro
  • Patent number: 9728234
    Abstract: A method for operating a semiconductor memory device includes receiving input/output signals including a command, an address and data, through input/output lines; and receiving a first control signal and a second control signal, wherein, regardless of a state of the second control signal, when the first control signal which is enabled is received, the input/output signals received through the input/output lines are recognized as the command.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: August 8, 2017
    Assignee: SK Hynix Inc.
    Inventors: Do Hyun Kim, Beom Ju Shin
  • Patent number: 9697889
    Abstract: According to one general aspect, an apparatus may include a bit cell configured to store a bit of information. The apparatus may include a first voltage configured to supply the bit cell with power. The apparatus may include a wordline driver configured to cause the bit to be read from the bit cell. The wordline driver may be configured to operate during a read operation at a second voltage that is lower than the first voltage, wherein the second voltage is determined by charge sharing between a plurality of capacitances. The wordline driver may include a switch configured to disconnect the wordline driver from the first voltage before an input word line signal is applied to the wordline driver, and wherein the switch is responsive to a clock signal.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: July 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kevin E. Klein, Prashant U. Kenkare
  • Patent number: 9697885
    Abstract: A semiconductor memory device includes: a weak cell controller for programming weak cell information, outputting the weak cell information in response to an initialization signal or a write end signal, and outputting a read end signal whenever the weak cell information is outputted; a memory cell array region that includes memory cells for storing data in response to a row active signal and a column selection signal, and includes a first cell region for storing the weak cell information; an information transfer control circuit for generating a column address based on a column counting signal generated by using the read end signal, and generating a row address whenever the column counting signal reaches a predetermined value in response to the initialization signal; a row circuit for enabling the row active signal; and a column circuit for outputting the column selection signal by decoding the column address.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: July 4, 2017
    Assignee: SK Hynix Inc.
    Inventor: Youk-Hee Kim
  • Patent number: 9691447
    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: June 27, 2017
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Bret Stott, Benedict C. Lau
  • Patent number: 9679618
    Abstract: A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascode configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: June 13, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Conte, Mario Micciche′, SantiNunzioAntonino Pagano
  • Patent number: 9672882
    Abstract: A method and apparatus for memory subsystem calibration in which periodic calibrations of a data strobe delay and reference voltage are scheduled. After a first calibration, a reference score is determined based on a parameter of an eye opening. On a next scheduled calibration thereafter, the data strobe delay is calibrated at the most recent value of the reference voltage. A score is then determined, and compared to the reference score. If the score is within a specified range of the reference score, then no calibration of the reference voltage is performed on the current cycle. Otherwise, the reference voltage is calibrated as well.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: June 6, 2017
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Rakesh L. Notani
  • Patent number: 9659121
    Abstract: A computer program product for improved modeling of differential circuits is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to represent a configuration of a differential circuit on a defined space with representations of single-ended inputs and outputs disposed as differential input and output pairs along borders of the defined space, respectively, for each differential input and output pair, introduce an internal input or output differential node to feed from or to feed a corresponding differential input or output pair within the borders, respectively, with the internal input and output differential nodes being connectable and perform timing calculations with respect to input and output differential nodes.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: May 23, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemlata Gupta, Jin Hu, Chad A. Marquart, Vasant Rao, Debjit Sinha
  • Patent number: 9640233
    Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: May 2, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyo-min Sohn
  • Patent number: 9627029
    Abstract: A memory controller transmits a control signal to a memory module, where the memory controller continuously transmits a clock signal to the memory module. The memory controller determines adjustments to the control signal with respect to the clock signal, by iteratively analyzing a strobe signal.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: April 18, 2017
    Assignee: INTEL CORPORATION
    Inventors: Tonia G. Morris, Jonathan C. Jasper, John V. Lovelace, Benjamin T. Tyson
  • Patent number: 9612610
    Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: April 4, 2017
    Assignee: Silicon Motion, Inc.
    Inventors: Chin-Pang Chang, Chun-Yi Lo
  • Patent number: 9612982
    Abstract: Methods and electronic devices for adjusting an operating frequency of a memory are disclosed. The method includes: transmitting to the memory a first command that instructs the memory to hold the data information in the memory; transmitting to the memory controller a second command that adjusts the first frequency of the memory controller to a second frequency; and transmitting to the memory a third command that instructs the memory to exchange the data information according to the second frequency of the memory controller. According to the disclosure, it is possible to dynamically adjust the frequency of the memory during operation, avoiding the need of the user to turn off and then turn on the electronic device to adjust the frequency of the memory.
    Type: Grant
    Filed: September 5, 2011
    Date of Patent: April 4, 2017
    Assignees: Beijing Lenovo Software Ltd., Lenovo (Beijing) Limited
    Inventors: Jingang Peng, Xiaogang Wang, Xiaoyi Feng
  • Patent number: 9601170
    Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a command input buffer that receives command signals and further provides buffered command signals; a command decoder coupled to the command input buffer, that decodes the buffered command signals responsive to a first clock signal and further provides a decoded command signal; and a command extension circuit coupled to the command decoder, which receives the decoded command signal, the first clock signal and a second clock signal having a first delay relative to the first clock signal, and further provides a command extension signal having a pulse width longer than the pulse width of the decoded command signal.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: March 21, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Kallol Mazumder
  • Patent number: 9576639
    Abstract: One semiconductor device includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal is activated. The latency control circuit activates a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles. The command receiver is activated based on a first control signal. The first control signal is activated in response to the first internal chip select signal. The first control signal is deactivated in response to the second control signal.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: February 21, 2017
    Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.
    Inventor: Chikara Kondo
  • Patent number: 9576641
    Abstract: Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: February 21, 2017
    Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.
    Inventor: Chikara Kondo
  • Patent number: 9530480
    Abstract: A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: December 27, 2016
    Assignees: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC
    Inventors: Naoki Shimizu, Ji Hyae Bae
  • Patent number: 9484134
    Abstract: A feedthrough signal transmission circuit includes a first permanently on cell and a cell controlling unit. The first permanently on cell is arranged to transmit a first control signal. The cell controlling unit is coupled to the first permanently on cell, and includes a power switch and a plurality o buffers. The power switch is coupled to the first permanently on cell, arranged to receive a switch control signal and the first control signal, and selectively output the first control signal according to the switch control signal. The plurality of buffers is coupled to the power switch. Each of the buffers is arranged to buffer a data input only when powered by the first control signal output from the power switch.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: November 1, 2016
    Assignee: MEDIATEK INC.
    Inventors: Chien-Pang Lu, Yu-Tung Chang
  • Patent number: 9450620
    Abstract: A digital interface and control module and a multi-function digital bus for use in a wireless radio frequency receiver, transmitter, or transceiver that communicates over a millimeter-wave band at multi-gigabit speeds. The control module provides a low power, low cost, small form factor, and low pin-count solution for high-speed control of a multi-gigabit radio frequency circuitry. The control module may be used to steer an antenna array for beamforming including selecting different antennas and different phases in compliance with IEEE 802.11ad/WiGig specifications. The control module may also be used for individually controlling variable gain amplifiers and low noise amplifiers and for phase shift controls, gain settings, and other controls.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 20, 2016
    Assignee: Nitero Pty Ltd.
    Inventors: Sebastian Ahmed, Richard Steven Richmond, II
  • Patent number: 9443571
    Abstract: According to one embodiment, a semiconductor memory includes a memory area; an error detection circuit which detect an error of first data output from the memory area; and a control circuit which control the memory area and the error detection circuit. When the error is detected in the first data, the control circuit starts precharge of a bit line at a timing when a first period has elapsed from a start of a first operation of the memory area for output of the first data. When the error is not detected in the first data, the control circuit starts the precharge at a timing when a second period has elapsed from the start of the first operation, the second period is shorter than the first period.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: September 13, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Naoki Shimizu
  • Patent number: 9437263
    Abstract: Apparatuses and methods for providing strobe signals to memories are described herein. An example apparatus may include a plurality of memories and a memory controller. The memory controller may be coupled to the plurality of memories and configured to receive an input clock signal. The memory controller may further be configured to provide a timing strobe signal having a delay relative to the input clock signal to a memory of the plurality of memories. The memory controller may further be configured to receive a return strobe signal from the plurality of memories. In some examples, the return strobe signal may be based at least in part on the timing strobe signal and the memory controller may be configured to adjust the delay based, at least in part, on a phase difference of the input clock signal and the return strobe signal.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: September 6, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Nathan A. Eckel
  • Patent number: 9430406
    Abstract: An electronic system 100 for generating a cryptographic key, the system comprising a memory 110 used as a physically unclonable function, the memory being writable, volatile and configured such that upon each powering-up of the memory the memory settles into a memory content which depends upon at least partially random physical characteristics of the memory, the memory being accessible through a memory interface, and a key derivation unit 150 configured to derive the cryptographic key from the memory content into which the memory settled, wherein the electronic system for generating a cryptographic key further comprises, a memory read-out unit connected to the memory through the memory interface and to the key derivation unit, the memory read-out unit comprising an address scrambler 140 for retrieving the memory content over the memory interface in a scrambled order.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: August 30, 2016
    Assignee: INTRINSIC ID B.V.
    Inventors: Erik Van Der Sluis, Marten Van Hulst
  • Patent number: 9426916
    Abstract: A multi-rank memory module is operable in a memory system with a memory controller. The memory module according to one embodiment comprises at least one module board, memory devices organized in three ranks, and at least one register device providing control/address signals to the memory devices. Arrangement of the ranks on the at least one module board are made to balance memory device loadings on the C/A signals, and data/strobe signal hubs are designed to provide better alignment of different data bits in a data signal and to reduce reflection from discrete components disposed near an edge of the module board, resulting in improved signal quality and integrity.
    Type: Grant
    Filed: August 11, 2013
    Date of Patent: August 23, 2016
    Assignee: Netlist, Inc.
    Inventors: Jayesh R. Bhakta, Son H. Nguyen
  • Patent number: 9418717
    Abstract: A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuoyuan (Peter) Hsu, Bing Wang, Derek C. Tao, Yukit Tang, Kai Fan
  • Patent number: 9419633
    Abstract: An interface circuit of a semiconductor apparatus may include a pulse generation unit, a data clock synchronization unit and a system clock synchronization unit. The pulse generation unit may be configured to generate a burst end pulse from a burst end signal according to a data clock signal. The data clock synchronization unit may be configured to enable a data clock synchronization signal based on the burst end pulse and the data clock signal, and disable the data clock synchronization signal according to a burst end detection signal. The system clock synchronization unit may be configured to generate the burst end detection signal by synchronizing the data clock synchronization signal with a system clock signal.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 16, 2016
    Assignee: SK HYNIX INC.
    Inventor: In Sik Yoon
  • Patent number: 9406373
    Abstract: A memory array includes an array of memory cells. The memory array further includes at least two read tracking cells in a read tracking column. The memory array further includes a read tracking circuit coupled to the at least two read tracking cells, wherein the read tracking circuit is configured to generate a global tracking result signal based on outputs from the at least two read tracking cells. The memory array further includes memory control circuitry, wherein the memory control circuitry is configured to reset a memory clock based on the global tracking result signal.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Derek C. Tao, Bing Wang, Kuoyuan (Peter) Hsu, Jacklyn Chang, Young Suk Kim
  • Patent number: 9390016
    Abstract: The disclosed embodiments provide a system in which a processor chip accesses an off-chip cache via silicon photonic waveguides. The system includes a processor chip and a cache chip that are both coupled to a communications substrate. The cache chip comprises one or more cache banks that receive cache requests from a structure in the processor chip optically via a silicon photonic waveguide. More specifically, the silicon photonic waveguide is comprised of waveguides in the processor chip, the communications substrate, and the cache chip, and forms an optical channel that routes an optical signal directly from the structure to a cache bank in the cache chip via the communications substrate. Transmitting optical signals from the processor chip directly to cache banks on the cache chip facilitates reducing the wire latency of cache accesses and allowing each cache bank on the cache chip to be accessed with uniform latency.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 12, 2016
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Pranay Koka, Michael O. McCracken, Herbert D. Schwetman, Jr., Ronald Ho
  • Patent number: 9384820
    Abstract: A method and apparatus for aligning calibration segments for increased availability of a memory subsystem is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto via a number of independently operable channels (interfaces). The memory controller may convey on each of the channels at least one corresponding data strobe signal. The data strobe signal in each channel may be periodically calibrated. The memory controller may be configured to align the periodic calibrations in time so that they are performed concurrently instead of in a staggered manner. During the time the calibrations are performed on each channel, the memory may be unavailable for normal accesses.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: July 5, 2016
    Assignee: Apple Inc.
    Inventors: Neeraj Parik, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu
  • Patent number: 9374096
    Abstract: A semiconductor apparatus includes a clock division block suitable for generating a first internal clock and a second internal clock having a first phase difference at which active sections of the first internal clock and the second internal clock overlap with each other by dividing a phase of a source clock at a predetermined rate, and a phase detection block suitable for outputting detection result information generated by combining a result obtained by detecting a phase of the first internal clock at a predetermined edge of a strobe signal and a result obtained by detecting a phase of the second internal clock at the predetermined edge of the strobe signal.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: June 21, 2016
    Assignee: SK Hynix Inc.
    Inventors: Ga-Ram Park, Jae-Il Kim
  • Patent number: 9355718
    Abstract: For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level are orthogonal or otherwise cross with one another. Vertical shunting among levels for routing in different directions employs short paddles that stay within the parallel scheme, and multiple paddles within a region at the same metal level can be co-linear. Parallel lines in the same metal level can be rotated with respect to one another in adjacent regions, for example to better interface with driver circuitry with orthogonal orientations in the different regions.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: May 31, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Everardo Torres Flores, Hernan A. Castro, Jeremy M. Hirst
  • Patent number: 9330749
    Abstract: In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: May 3, 2016
    Assignee: XILINX, INC.
    Inventors: Dhruv Choksey, Terence J. Magee
  • Patent number: 9312031
    Abstract: A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data.
    Type: Grant
    Filed: August 23, 2014
    Date of Patent: April 12, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventor: Naohisa Nishioka