Transmission Patents (Class 365/198)
  • Patent number: 10090052
    Abstract: Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 9881674
    Abstract: Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 9666305
    Abstract: A circuit for testing a memory includes a complementary charge trap memory cell, which includes a first transistor and a second transistor. A logical value of the cell corresponds to respective states of the first transistor and the second transistor. The circuit further includes a first bitline coupled to the first transistor, where the first transistor is configured to apply a first voltage to the first bitline. The circuit includes a second bitline coupled to the second transistor, where the second transistor is configured to apply a second voltage to the second bitline. The circuit also includes a sense circuit configured to output, prior to programming of the complementary charge trap memory cell, a logical high signal or a logical low signal in response to the first voltage on the first bitline and the second voltage on the second bitline.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Patent number: 9654105
    Abstract: A semiconductor apparatus may include an on-die termination (ODT) enable signal generator configured to enable an ODT enable signal in response to a data strobe signal, or enable the ODT enable signal in response to a command latch enable signal and an address latch enable signal. The semiconductor apparatus may include an ODT circuit configured to perform an ODT operation in response to the ODT enable signal.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: May 16, 2017
    Assignee: SK hynix Inc.
    Inventor: Kwang Hyun Kim
  • Patent number: 9135981
    Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eunsung Seo, Chul-Sung Park, Chi-Sung Oh
  • Patent number: 9136250
    Abstract: A through silicon via (TSV) repair circuit is provided. The TSV repair circuit includes at least two transmission control switches and at least two transmission path modules. Two transmission control switches transmit an input signal of a first chip or a second chip to one of two terminals in each of the transmission path modules according to a switch signal. Each transmission path module includes at least two data path circuits and corresponding TSVs. Each data path circuit includes an input driving circuit, a short-circuit detection circuit and a leakage current cancellation circuit. The short-circuit detection circuit detects whether to detect whether short-circuit on the TSV and a silicon substrate is present and generate a short-circuit detection output signal. The leakage current cancellation circuit to avoid a leakage current generated by a first level voltage to flow into the silicon substrate according to the short-circuit detection output signal.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: September 15, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Pei-Ling Tseng, Keng-Li Su
  • Patent number: 9129669
    Abstract: Semiconductor systems are provided. The semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device generates an input calibration signal during a mode register write operation and receives an output data and an output calibration signal to control a recognition point of a logic level of the output data according to a delay time of the output calibration signal during a read operation. The second semiconductor device stores the input calibration signal therein during the mode register write operation and outputs the output calibration signal and the output data during the read operation.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: September 8, 2015
    Assignee: SK Hynix Inc.
    Inventor: Keun Soo Song
  • Patent number: 9070572
    Abstract: A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 30, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Hyung Song, Kyoungsun Kim, Yong-jin Kim, Jaejun Lee, Sangseok Kang, Jungjoon Lee
  • Patent number: 9047929
    Abstract: A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: June 2, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eunsung Seo, Chul-Sung Park, Chi-Sung Oh
  • Patent number: 9036420
    Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 19, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventors: Benjamin Vigoda, Jeffrey Bernstein, Jeffrey Venuti, Alexander Alexeyev, Eric Nestler, David Reynolds, William Bradley, Vladimir Zlatkovic
  • Publication number: 20150124541
    Abstract: According to one embodiment, there are provided a memory which is provided on a circuit board, a controller which is provided on the circuit board and controls the memory, and a signal line which is formed on the circuit board and configured to perform data transmission between the controller and the memory, in which a width of the signal line in the place where the signal line is led out from the memory is large compared with a place disposed under the memory.
    Type: Application
    Filed: January 12, 2015
    Publication date: May 7, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi OKADA, Atsuko Seki
  • Patent number: 9019778
    Abstract: A semiconductor apparatus includes a memory chip which includes: a memory area; a data input/output block configured to communicate with the memory area; and a data transmission/reception block configured to connect one of a plurality of channels and a pad to the data input/output block, wherein the plurality of channels are configured to input and output normal data to and from another chip, and the pad is configured to input and output test data.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Young Ju Kim, Sang Hoon Shin
  • Publication number: 20150103609
    Abstract: A semiconductor device including a control signal generator and an internal refresh signal generator is provided. The control signal generator generates first and second control signals, one of which is selectively enabled in response to temperature code signals and mode set signals after a pulse of an internal refresh signal is outputted by the internal refresh signal generator. The temperature code signals are obtained from temperature signals. The internal refresh signal generator outputs a refresh command signal as the internal refresh signal when the first control signal is enabled. Further, the internal refresh signal generator outputs the refresh command signal as the internal refresh signal at a moment that the refresh command signal is inputted thereto by a predetermined number of times when the second control signal is enabled.
    Type: Application
    Filed: February 10, 2014
    Publication date: April 16, 2015
    Applicant: SK hynix Inc.
    Inventors: Choung Ki SONG, Yo Sep LEE, Chan Gi GIL, Chang Hyun KIM
  • Publication number: 20150098285
    Abstract: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Brian W. Huber, Vijay Vankayala, Brian Gross, Gary Howe, Roy E. Greeff
  • Patent number: 9001605
    Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics, Inc.
    Inventor: David V. Carlson
  • Patent number: 8988102
    Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: March 24, 2015
    Assignee: Rambus Inc.
    Inventor: Ian Shaeffer
  • Patent number: 8976601
    Abstract: A semiconductor memory apparatus includes a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple the low voltage page buffer and the high voltage page buffer. The boundary circuit unit includes: a first boundary circuit unit having first and second transistors configured to receive data of a corresponding memory cell area through a signal transmission line selected from a plurality of signal transmission lines extended and arranged along a first direction for each column; a second boundary circuit unit disposed adjacent in the first direction from the first boundary circuit unit and having the plurality of signal transmission lines extended and arranged thereon; and an active region where the first transistor is formed and an active region where the second transistor is formed are isolated from each other.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Sung Lae Oh, Byung Sub Nam, Go Hyun Lee
  • Patent number: 8971139
    Abstract: A semiconductor device comprises transmission lines, inverting circuits, first, second and third switches, global sense amplifiers, and a control circuit. The first switch switches between the transmission line and the input of the inverting circuit, the second switch switches between the transmission line and the output of the transmission line, and the third switch switches between the adjacent transmission lines. The control circuit turns off the first and second switches so that the transmission lines are brought into a floating state in a state where signals of the transmission lines are held in the inverting circuits by the global sense amplifiers. After charge sharing of the transmission lines occurs by turning on the third switches within a predetermined period, the control circuit turns off the second switches so that the transmission lines are inverted and driven via the inverting circuits and the second switches.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: March 3, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 8953409
    Abstract: A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a predetermined number.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: February 10, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toru Ishikawa
  • Patent number: 8947960
    Abstract: A storage medium including a plurality of memory cells, a plurality of transmission lines, a driving module and a floating detection module is disclosed. The memory cells store data. The transmission lines are coupled to the memory cells. The driving module accesses the memory cells via the transmission lines. The floating detection module includes a reset unit, a plurality of connectors and a detector. The reset unit is coupled to a detection line. Each of the connectors is coupled between one of the transmission lines and the detection line. The detector determines whether a state of at least one of the transmission lines is a floating state according to a level of the detection line.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: February 3, 2015
    Assignee: Winbond Electronics Corp.
    Inventor: Chih-Jing Lai
  • Patent number: 8917565
    Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: December 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Ryul Ryu
  • Patent number: 8902684
    Abstract: A system includes a first chip configured to supply a training command and a second chip configured to transfer to the first chip a measured time for performing an operation in response to the training command.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: December 2, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ki-Chang Kwean
  • Patent number: 8897082
    Abstract: The data transmission circuit includes: a plurality of local bit line pairs through which data is read simultaneously; a plurality of voltage change detection circuits provided for the plurality of local bit line pairs; a global bit line pair; a plurality of column selection circuits configured to select one of the local bit line pairs and connect the selected local bit line pair to the global bit line pair; and a sense amplifier connected to the global bit line pair. The sense amplifier is controlled by a sense amplifier activation signal to which the outputs of the plurality of voltage change detection circuits are connected, whereby the voltage of a selected read data line pair is amplified using discharge of a non-selected read data line pair, to achieve high-speed read.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: November 25, 2014
    Assignee: Panasonic Corporation
    Inventor: Tsuyoshi Koike
  • Patent number: 8896340
    Abstract: Semiconductor modules are provided. The semiconductor module includes semiconductor chips with one or more ranks. The semiconductor module includes a mode register configured for storing a first information signal whose logic level is set or determined according to a number of the ranks and an on-die termination (ODT) controller configured for generating an internal control signal for activating an ODT circuit in response to the first information signal. The internal control signal is enabled during a read operation or disabled during a write operation.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: November 25, 2014
    Assignee: SK Hynix Inc.
    Inventor: Tae Jin Kang
  • Patent number: 8897080
    Abstract: A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N×m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: November 25, 2014
    Assignee: SanDisk Technologies Inc.
    Inventor: Wanfang Tsai
  • Patent number: 8891318
    Abstract: A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: November 18, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Takenori Sato, Yoji Idei, Hiromasa Noda
  • Patent number: 8867287
    Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jin Youp Cha, Jae Il Kim
  • Publication number: 20140301134
    Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a cache memory, and a package. The first processing unit comprises a first ground-referenced single-ended signaling (GRS) interface circuit and the second processing unit comprises a second GRS interface circuit. The cache memory comprises a third and a fourth GRS interface circuit. The package comprises one or more electrical traces that couple the first GRS interface to the third GRS interface and couple the second GRS interface to the fourth GRS interface, where the first GRS interface circuit, the second GRS interface, the third GRS interface, and the fourth GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.
    Type: Application
    Filed: April 4, 2013
    Publication date: October 9, 2014
    Applicant: NVIDIA Corporation
    Inventors: William J. Dally, John W. Poulton, Thomas Hastings Greer, III, Brucek Kurdo Khailany, Carl Thomas Gray
  • Patent number: 8837230
    Abstract: A memory circuit device having at least one test element interconnecting memory sections can include at least one first switch coupled to a first memory section between a first node within a tested section and an intermediate node, a test switch coupled between the intermediate node and a forced voltage node, and a second switch coupled between the intermediate node and a second node; wherein the forced voltage node is selectively coupled to receive a forced voltage substantially the same as a voltage applied to the second node, and the second node is coupled to at least a second memory section.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: September 16, 2014
    Assignee: Suvolta, Inc.
    Inventors: Lawrence T. Clark, Richard S. Roy
  • Patent number: 8837191
    Abstract: A semiconductor apparatus includes a multi-chip module which multi-chip module comprises a first and a second chips. The semiconductor apparatus comprises a first data line in the first chip to carry first read data; a first controller, in the first chip, configured to generate first output data on a first output data line in the first chip based on the first read data transmitted from the first data line; a first data transmitter configured to electrically connect the first output data line to the second chip.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 16, 2014
    Assignee: SK Hynix Inc.
    Inventors: Heat Bit Park, Kang Seol Lee
  • Publication number: 20140204692
    Abstract: A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.
    Type: Application
    Filed: March 20, 2014
    Publication date: July 24, 2014
    Applicant: Elpida Memory, Inc.
    Inventors: Shetti Shanmukheshwara Rao, Ankur GOEl
  • Publication number: 20140185384
    Abstract: An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence accompanies an impedance calibration operation; and if the input command sequence accompanies the impedance calibration operation, simultaneously performing an operation corresponding to the input command sequence and the impedance calibration operation.
    Type: Application
    Filed: December 31, 2013
    Publication date: July 3, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong KIM, Soonbok Jang
  • Patent number: 8760952
    Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: June 24, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: David V. Carlson
  • Publication number: 20140169112
    Abstract: A semiconductor memory system configured to exchange signals through channels may include a memory control device configured to have a plurality of channels, a plurality of memory devices configured to be connected to each of the plurality of channels, wherein the plurality of channels share at least one of the plurality of memory devices.
    Type: Application
    Filed: March 14, 2013
    Publication date: June 19, 2014
    Applicant: SK HYNIX INC.
    Inventors: Chun-Seok JEONG, Jae-Jin LEE
  • Publication number: 20140140152
    Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.
    Type: Application
    Filed: September 10, 2013
    Publication date: May 22, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshikazu TAKEYAMA, Masaru KOYANAGI, Akio SUGAHARA
  • Patent number: 8687449
    Abstract: A semiconductor device according to the present invention includes plural core chips CC0 to CC7 to which mutually different pieces of chip identification information LID are allocated, and an interface chip IF that controls the core chips CC0 to CC7. The interface chip IF receives address information ADD for specifying a memory cell, and supplies in common a part of the address information to the core chips CC0 to CC7 as chip selection information SEL to be compared with the chip identification information LID. With this configuration, it appears from a controller that an address space is simply enlarged. Therefore, an interface that is same as that for a conventional semiconductor memory device can be used.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: April 1, 2014
    Assignee: Elpida Memory, Inc.
    Inventor: Hideyuki Yoko
  • Patent number: 8687442
    Abstract: A data signal is sampled by generating a read enable signal at a first semiconductor device which is intended for a second semiconductor device. A read enable signal with at least some I/O pad delay included is obtained, including by passing the read enable signal intended for the second semiconductor device at least partially through an input/output (I/O) pad on the first semiconductor device. At the first semiconductor device, a data signal from the second semiconductor is sampled using the read enable signal with at least some I/O pad delay included.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: April 1, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Priyanka Thakore, Meng-Kun Lee
  • Patent number: 8675429
    Abstract: A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: March 18, 2014
    Assignee: Google Inc.
    Inventors: Min Wang, Philip Arnold Ferolito, Suresh Natarajan Rajan, Michael John Sebastian Smith
  • Patent number: 8664972
    Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: March 4, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kohei Murayama, Takeshi Suzuki
  • Patent number: 8644085
    Abstract: Correction of duty cycle distortion of DQ and DQS signals between a memory controller and a memory is corrected by determining a duty cycle correction factor. The duty cycle distortion is corrected by applying the duty cycle correction factor to the plurality of differential DQS signals. The duty cycle distortion is corrected across a plurality of differential DQS signals between the memory controller and the bursting memory.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kyu-hyoun Kim, Paul Rudrud, Jacob D. Sloat
  • Patent number: 8638619
    Abstract: A memory chip includes a plurality of storage elements. A method of controlling the memory chip includes receiving a plurality of target values from a memory controller. Each target value of the plurality of target values received from the memory controller corresponds to a respective one of the plurality of storage elements. The method further includes, for each storage element of the plurality of storage elements, adjusting a measurable parameter of the storage element until the measurable parameter of the storage element reaches the target value corresponding to the storage element received from the memory controller.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: January 28, 2014
    Assignee: Marvell World Trade Ltd.
    Inventor: Pantas Sutardja
  • Patent number: 8619492
    Abstract: An on-die termination (ODT) circuit of a memory device comprising: a memory device having a memory core having a memory cell array; a data input/output pin connected to the memory core through a data buffer; and an on-die termination (ODT) circuit, comprising: a termination circuit configured to provide a termination impedance at the input/output data pin, the termination circuit having a switching device that selectively connects a termination impedance to the input/output data pin based on the presence of an asynchronous control signal (ACS), wherein the ACS is generated based on the presence of a memory WRITE command.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: December 31, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Jin Jeon
  • Patent number: 8599623
    Abstract: An integrated circuit device can include a plurality of test elements, each comprising at least one first switch coupled between a node within a tested section and an intermediate node, a test switch coupled between the intermediate node and a forced voltage node, and a second switch coupled between the intermediate node and an output node; wherein the forced voltage node is coupled to receive a forced voltage substantially the same as a test voltage applied to the output node in a test mode.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: December 3, 2013
    Assignee: Suvolta, Inc.
    Inventors: Lawrence T Clark, Richard S Roy
  • Patent number: 8581755
    Abstract: A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: November 12, 2013
    Assignee: Rambus Inc.
    Inventors: Aliazam Abbasfar, John Wilson
  • Patent number: 8576650
    Abstract: A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: November 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Young Oh, Seung-Jun Bae, Kwnag-Il Park
  • Patent number: 8553471
    Abstract: A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Si-Hong Kim, Seung-Jun Bae, Jin-Il Lee, Kwang-Il Park
  • Patent number: 8547775
    Abstract: The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip selection information for comparison with the chip identification information to the plural core chips. As a result, since the controller recognizes that an address space is simply enlarged, the same interface as that in the semiconductor memory device according to the related art can be used.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: October 1, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hideyuki Yoko
  • Patent number: 8547761
    Abstract: A memory module comprises a plurality of semiconductor memory devices each having a termination circuit for a command/address bus. The semiconductor memory devices are formed in a substrate of the memory module, and they operate in response to a command/address signal, a data signal, and a termination resistance control signal.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Il Kim, You-Keun Han, Jung-Joon Lee
  • Patent number: 8542543
    Abstract: A memory device including variable resistance elements comprises a plurality of memory cells configured to store data; a first signal transmission/reception unit and a second signal transmission/reception unit configured to transmit a signal to the memory cells or receive a signal from the memory cells; a first transmission line arranged to couple first ends of the memory cells to the first signal transmission/reception unit; and a second transmission line configured to couple second ends of the memory cells to the second signal transmission/reception unit, wherein a first resistance of a first signal path coupled between the first and second signal transmission/reception units through a first memory cell of the memory cells is substantially equal to a second electrical resistance of a second signal path coupled between a second memory cell and the first and second signal transmission/reception units through a second memory cell of the memory cells.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: September 24, 2013
    Assignee: SK hynix Inc.
    Inventor: Sang-Min Hwang
  • Publication number: 20130242680
    Abstract: A memory module includes a command/address (CA) register, memory devices, and a module resistor unit mounted on a circuit board. The centrally disposed CA register drive the memory devices one or more internal CA signal(s) to arrangements of memory devices using multiple CA transmission lines, wherein the multiple internal CA transmission lines are commonly terminated in the module resistor unit.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 19, 2013
    Inventors: JAE-JUN LEE, Do-Hyung Kim, Yong-Jin Kim, Bo-Ra Kim, Jeong-Hoon Baek, Kwang-Seop Kim, Da-Ae Heo