Abstract: A method of communicating between a memory and circuitry on an integrated circuit is disclosed. The method comprises converting a first input signal from the memory to a first differential output signal dependent upon the first input signal. The first input signal is a full swing signal. The first differential output signal is propagated to the circuitry using a pair of first signal lines. Finally, at the circuitry, the first differential output signal is converted into a first received signal, which is a full swing signal.

Abstract: A semiconductor device includes a switching element (ex. a Schottky barrier diode) which control transmission/cutoff of a signal transmitted between two portions of a transmission line. An anode electrode of the switching element is interposed between the two portions of the transmission line while the longitudinal direction of the anode electrode accords with the longitudinal direction of the transmission line. A cathode electrode of the switching element is disposed on at least one of the widthwise sides of the anode electrode, and is connected to the ground.

Abstract: A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transistors connected to function as diodes. The n-channel and p-channel devices may be connected to a large variety of devices and circuits, such as phase locked loops, delay locked loops, clock circuits, or any circuit which requires two balanced paths, one through n-channel devices and one through p-channel devices, to compensate for process variations. Methods for balancing a circuit path and compensating for process variations are also disclosed.

Abstract: Data of 2-bits prefetched from a memory array and transmitted to an amplifying circuit via a data bus is ordered in accordance with the least significant bit of a column address which is a start address supplied from the outside. The first data is output to read data buses and is directly transmitted to an output data latch. The second data is held once by a second data latch and, after that, transmitted to the output data latch. Since the first data is transmitted from the amplifying circuit directly to the output data latch, the time from a read command is received until data is started to be output can be shortened.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: A memory array is divided into a plurality of memory blocks each having a plurality of bit line pairs. In the memory block selected for a data write operation, first and second selection gates are turned ON so as to couple first and second nodes to the power supply voltage and the ground voltage, respectively. In the data write operation, complementary bit lines of the same bit line pair are electrically coupled to each other through a bit-line coupling transistor. A bit-line current switching portion connects a plurality of bit line pairs in series between the first and second nodes so that the directions of reciprocating-current paths respectively formed in the plurality of bit line pairs correspond to the respective data levels of a plurality of bits.

Abstract: A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths is provided. The data communication system includes a central data path including at least one junction circuit configured for exchanging data signals between the central data path and the plurality of data paths of the at least one data path. A respective one junction circuit of the at least one junction circuit includes circuitry for controlling resetting the respective one junction circuit for preparation of a subsequent data transfer through the respective one junction circuit in accordance with receipt of an input junction monitor signal indicating that data has been transferred to the respective one junction circuit. The data communication system further includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths.

Abstract: A technique to encode a precharge command on a flag signal used to execute data transfer to and from a DRAM.

Abstract: Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The present invention offers an improved signal to noise ration. The present invention provides for the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. Embodiments of a method for forming transmission lines in an integrated circuit include forming a first layer of electrically conductive material on a substrate. The method includes forming a first layer of insulating material on the first layer of the electrically conductive material. The first layer has a thickness of less than 1.0 micrometers (&mgr;m). A transmission line is formed on the first layer of insulating material. The transmission line has a thickness and a width of approximately 1.0 micrometers. A second layer of insulating material is formed on the transmission line.

Abstract: An MRAM device (400) having write paths with substantially uniform length and resistance for all memory cells within the memory array (411). CVC circuits are positioned with respect to the memory array (411) such that the write path length along conductive lines of the MRAM device (401) is substantially the same for all memory cells in the array (411), ensuring that the resistance along the write path is substantially uniform, and therefore, the amount of write current provided by the CVC circuits to write the cells of the memory array (411) is substantially the same.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: A large difference in the lengths of the passages or a large difference in the load capacitances inclusive of parasitic elements of parallel data wirings can cause differences in the propagation time of data on the parallel data wirings. The invention provides a simultaneous arrival judging circuit for comparing phases of part or whole bits of data received from the parallel data wirings, and a timing adjusting mechanism for adjusting phases among parallel bits of the received data based on the judged results of the simultaneous arrival judging circuit, so that the data bits arrive simultaneously at a receiver.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: A semiconductor device comprises a memory cell block and a sense amplifier zone. A selection gate included in the sense amplifier zone is turned on for selectively coupling the memory cell block with the sense amplifier zone. Local drivers are dispersively arranged on a BLI wire transmitting a gate control signal, and a driver is arranged on an end of the BLI wire. The driver pulls down the potential of the BLI wire at a high speed.

Abstract: A high speed data path includes a first plurality of inverters skewed toward one logic level alternating with a second plurality of inverters skewed toward a second logic level. As a result, the inverters in the first plurality accelerate one transition of a digital signal and the inverters in the second plurality accelerate the opposite transition of the digital signal. Prior to applying the digital signal to the inverters, the inverters are preset to a logic level from which they will transition in an accelerated manner. As a result, a transition of the digital signal is coupled through the inverters in an accelerated manner.

Abstract: A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.

Abstract: The data transmission device including: a data bus sense amp controlled according to a control signal which is a pulse signal, for detecting and amplifying a data applied to a data bus; a plurality of driving units for buffering and outputting an output from the data bus sense amp; a read data line for receiving a pulse data transmitted by the plurality of driving units; a plurality of pull-down units controlled according to an output signal from the plurality of driving units, for performing a pull-down operation on the read data line; a plurality of multi-delay units controlled according to a detection signal detecting a period of an externally-inputted clock signal, for delaying the pulse data applied to the read data line for a different delay time; and a pull-up unit controlled according to an output signal from the plurality of multi-delay units, for resetting the data line.

Abstract: A method and apparatus for data transmission and reception is disclosed. A data transmission/reception apparatus (300) may allow data to be transferred between a data bus (IOT and ION) and a bit line pair (Di and DBi). The data transmission/reception apparatus (300) may include a column select transfer gate circuit (12) that may receive column select signals (YU and YLi) from a column address decode circuit (14). Column select transfer circuit (12) may include a transfer gate circuit (12i) that may provide a data transmission/reception path between a data bus (IOT and ION) and a bit line pair (Di and DBi). Transfer gate circuit (12i) may include connection nodes that may have parasitic capacitors (Ci and CBi). A precharge circuit (16) may allow previous data signals stored on parasitic capacitors (Ci and CBi) to be removed during a precharge operation before a subsequent data transfer operation is executed.

Abstract: In the SDRAM, a selector selects one of four global IO line pairs according to a column block select signal and a word configuration selecting signal, and connects the selected global IO line pair to an input/output node pair of a preamplifier in a pulsed manner for a prescribed period of time. Since the equalization of the global IO line pair can be started immediately after the global IO line pair is connected in a pulsed manner to the input/output node pair of the preamplifier, longer equalization period for the global IO line can be set aside so that the read operation can be stabilized.

Abstract: Each global data bus is selectively connected via a connection circuit to any of local data buses associated with subarrays arranged on either side of the global data bus. Between row blocks is arranged a connection controlling circuit outputting a control signal which controls connection of the connection circuit. In each connection controlling circuit, a fuse corresponding to a location of a subarray including a defective memory cell is cut to provide column substitution without changing an order of global data buses.

Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Abstract: A method and apparatus for data transmission and reception is disclosed. A data transmission/reception apparatus (300) may allow data to be transferred between a data bus (IOT and ION) and a bit line pair (Di and DBi). The data transmission/reception apparatus (300) may include a column select transfer gate circuit (12) that may receive column select signals (YU and YLi) from a column address decode circuit (14). Column select transfer circuit (12) may include a transfer gate circuit (12i) that may provide a data transmission/reception path between a data bus (IOT and ION) and a bit line pair (Di and DBi). Transfer gate circuit (12i) may include connection nodes that may have parasitic capacitors (Ci and CBi). A precharge circuit (16) may allow previous data signals stored on parasitic capacitors (Ci and CBi) to be removed during a precharge operation before a subsequent data transfer operation is executed.

Abstract: A driver circuit transmits a signal to a receiver circuit through a signal transmission line. The driver circuit has an output driver, a front driver, and a level adjuster. The front driver drives the output driver, and the level adjuster adjusts the output level of the front driver. The output driver generates a signal whose level is variable in response to an output level of the front driver.

Abstract: An open drain driver circuit generates four switching signals to switch respective sets of current driving transistors on and off. The switching signals have slightly different transition times, and the rate at which the magnitude of each switching signal changes during each transition is controlled throughout each transition to maximize the switching times while slowing the rate of change during certain portions of each transition to prevent excessive changes in the rate at which the current changes. As a result, voltage transients generated in power supply lines coupled to the driver circuit have relatively small peak amplitude.

Abstract: When there is a difference in the lengths of the passages among the parallel data wirings or a difference in the load capacitances inclusive of parasitic elements, a difference in the propagation time among the data becomes no longer negligible. At the time of transmitting data at high speeds in a short period, in particular, the setup time for receiving the data and the holding time are no longer maintained, and the data are not normally transmitted. In a data transmitter provided to address this problem, the receiver for receiving parallel data is provided with a simultaneous arrival judging circuit for comparing phases of part or whole bits of the received data, and with a timing adjusting mechanism for adjusting phases among the parallel bits at a point of receiving data in the receiver based on the judged results of the simultaneous arrival judging circuit, so that the data bits arrive simultaneously at the receiver.

Abstract: A large difference in the lengths of the passages or a large difference in the load capacitances inclusive of parasitic elements of parallel data wirings can cause differences in the propagation time of data on the parallel data wirings. The invention provides a simultaneous arrival judging circuit for comparing phases of part or whole bits of data received from the parallel data wirings, and a timing adjusting mechanism for adjusting phases among parallel bits of the received data based on the judged results of the simultaneous arrival judging circuit, so that the data bits arrive simultaneously at a receiver.

Abstract: A semiconductor memory device having an operation delay function of a CAS command, and a buffer and a signal transmission circuit which are applied to the semiconductor memory device, are provided. The signal transmission circuit includes a plurality of transmission units each for delaying an input signal by a different number of delay clock cycles. The transmission unit includes a transmission switch and a clock delay unit. The semiconductor memory device can delay a received signal for different numbers of delay clocks in response to first through third control signals. Therefore, a predetermined delay time between when a row-type command is received and when a column-type command is received can be shortened.

Abstract: A transmission circuit for transmitting a data signal between circuit units through a signal wire. The data signal is transmitted for precharging the signal wire to high potential during a precharge period and discharging it to low potential according to data transmitted during an evaluation period or keeping the signal wire as it is. Latch type Source-Coupled-Logic as configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to high potential during the precharge period. The second node is discharged according to potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire. Thus, the operation of discharging the signal wire by the driver circuit can be sped up.

Abstract: A semiconductor memory device of present invention has a memory cell, a sense amplifier which amplifies data of the memory cell, first IO line connected to the sense amplifier, and second IO line which is connected to first IO line through a switch, wherein the second IO line is arranged on the memory cell.

Abstract: A bus made up of a plurality of lines is interposed between a driver circuit on the transmitting end and a receiver circuit on the receiving end. An equalizer circuit includes multiple CMOS switches, each of which is connected between two adjacent ones of the bus lines. In changing data to be transmitted through the bus lines, first, the outputs of tristate buffers on the transmitting end should have high impedance and input buffers on the receiving end should be deactivated. Then, an equalize (EQ) signal is asserted, thereby activating the equalizer circuit. While the potential levels on the bus lines are being equalized, these bus lines are all electrically disconnected from a power supply. After the potential levels on the bus lines have been equalized in this manner, the EQ signal is negated and then normal signal transmission is carried out.

Abstract: A computer includes a storage device having a plurality of memory cells, being operable to output data stored in the memory cell corresponding to an address signal, and being operable to output a data output fixing signal attaining a predetermined level in response to output of the data, and a processing device operable to apply the address signal to the storage device, take in the data from the storage device in response to the fact that the data output fixing signal attains the predetermined level, and perform processing in accordance with the data. The storage device and the processing device may be formed on a single chip. The processing device can take in and process the data whenever the data output fixing signal is output. When the storage device operates under conditions better than the worst conditions, data processing can be performed before elapse of a maximum access time determined in a specification prescribed taking the worst conditions into consideration.

Abstract: An energy-saving device for a memory circuit. The energy-saving device is capable of immediately terminating a local sense amplifier enable signal to a sense amplifier. The energy-saving device employs a plurality of Schmitt triggering circuits with each Schmitt triggering circuit capable of receiving an operational signal and an inverse operational signal and capable of issuing a Schmitt triggering signal to a data-transmission tester. The data-transmission tester will issue a response signal when change in the Schmitt triggering signal is detected. A data-transition-detected pulse is sent from a data-transmission-testing pulse generation circuit to a power shut down signaling circuit to terminate the local sense amplifier enable signal when the data-transmission-testing pulse-generation circuit receives a response signal.

Abstract: A system for testing semiconductor devices on device test boards has a single tester channel connected to multiple DUTs in a loop. Outputs from DUTs are received at a comparator and latch after a period of Round Trip Delay (RTD). The comparator is connected in a parallel configuration with the return path of the loop, where the point of connection is in greater proximity to DUT output pins than the test channel and is a path different from the tester I/O driver path, thus preventing input signals from test drivers from interfering with output signals from DUTs that will serve as inputs to test circuitry. The time it takes a new input cycle state to reach the output comparator is long after the output from a prior cycle has been tested. A diode clamp and resistor are connected in a series with the comparator at the input stage near the comparator in order to reduce ringing at the input of the comparator, which limits tester speed.

Abstract: A semiconductor memory device having an operation delay function of a CAS command, and a buffer and a signal transmission circuit which are applied to the semiconductor memory device, are provided. The signal transmission circuit includes a plurality of transmission units each for delaying an input signal by a different number of delay clock cycles. The transmission unit includes a transmission switch and a clock delay unit. The semiconductor memory device can delay a received signal for different numbers of delay clocks in response to first through third control signals. Therefore, a predetermined delay time between when a row-type command is received and when a column-type command is received can be shortened.

Abstract: A driver circuit transmits a signal to a receiver circuit through a signal transmission line. The driver circuit has an output driver, a front driver, and a level adjuster. The front driver drives the output driver, and the level adjuster adjusts the output level of the front driver. The output driver generates a signal whose level is variable in response to an output level of the front driver.

Abstract: A semiconductor memory device includes a transmission line, connected to a driving unit, for transmitting a signal from the driving unit, a delaying unit for delaying a level of the transmission line to output the delayed signal, a precharging unit for receiving the delayed signal to precharge the transmission line, and a stabilization unit for accelerating the level transition of the transmission line, wherein the stabilization unit includes a detecting unit for detecting the level of the transmission line transmitted from the driving unit to generate a detected signal, and a switching unit for performing a switching operation in response to the detected level to swiftly achieve a level transition of the transmission line.

Abstract: A semiconductor device connected to a bus consisting of a plurality of signal lines, comprises a first pad connected with a discrete resistor corresponding to the impedance of the signal lines, a plurality of second pads respectively connected with the signal lines, a reference voltage generator for generating a reference voltage, a comparator for comparing the voltage on the first pad with the reference voltage to generate a control signal, a code generator for generating a code signal according to the control signal, a current source for supplying the first pad with variable current according to the code signal, and a data driver for driving data signals to the signal lines connected with the second pads according to the code signal. The code signal is used to match the impedance of the data driver with the impedance of the signal lines.

Abstract: Address buffers of a semiconductor memory device have a switching section for switching into each other transmission routes of first and second address signals input from outside in response to predetermined control signals. The signals allow input of the address signals and set the operating mode of the semiconductor memory device.

Abstract: A method of storing data comprises the steps of: storing at least a set of coded real-time data having packets respectively having variable coding data rates per a predetermined interval in a data memory; detecting a maximum among the variable coding data rates; storing data of the maximum in a control data memory; selectively reading at least the see of coded real-time data in response to a demand; adding dummy data to read at least the set of coded real-time data such that the resultant data has a fixed data rate equal to or more than the data of maximum from the control data memory per the predetermined interval; and outputting the resultant data. A data storing apparatus embodying the method mentioned above is also disclosed. The data storing apparatus may further comprise a receiving circuit for receiving coded data output demanding data including a desired data rate and for supplying the desired data rate to the adding circuit.

Abstract: A low power semiconductor memory device for minimizing power consumption is disclosed. The low power semiconductor memory device includes a memory cell array with a plurality of memory cells connected to a pair of bit lines, and having first and second pairs of data lines each having a normal data line and a complementary data line. The device further includes a first switching circuit for switch-connecting the pair of bit lines to the first pair of data lines in response to column select information and a sense amplifier connected to the pair of bit lines within the memory cell array. A driving circuit transfers external data to one of the normal data line and the complementary data line of the second pair of data lines in response to a write master signal.

Abstract: A semiconductor memory device has the skew between the individual transmission lines of a parallel transmission bus minimized by the addition of respective load transmission lines to each of the individual transmission lines in the parallel bus. A first circuit unit including a first parallel bank of internal circuits for generating internal control signals is formed adjacent to a predetermined region within a chip. A second circuit unit includes a second parallel bank of internal circuits for performing a predetermined operation in response to an output of the first circuit unit. The second circuit transmits signals to the first circuit over a parallel bus comprised of a plurality of transmission lines connected respectively between the individual internal circuits of the first and second circuit units. A plurality of load transmission lines are connected respectively to predetermined portions of the individual transmission lines to thereby equalize the loads of the transmission lines.

Abstract: A redundancy circuit for a semiconductor memory device utilizes a fuse ladder comprising alternating programmable resistive fuses and signal restorers connected to one another in series. The signal restorers coupled between the fuses prevent the formation of a high impedance resistive line with a floating node when one of the fuses in the ladder is blown.

Abstract: A serial differential cell includes complementary positive and negative pass gate networks coupled to a differential amplifier, which produces a valid logic output. The complementary pass gate networks can include one or more pass gate stages coupled in series. In a serial differential multiplexer, a stage includes first and second inputs, and a select input for controlling which input is passed to an output of the stage. For multiple stages, the output of a first stage is coupled to one of the inputs of a next stage. A number of stages can be coupled together in series to form networks, with a differential amplifier coupled between positive and negative networks where necessary to provide a valid logic output.

Abstract: A single chip integrated circuit 200 is disclosed which includes logic circuitry 202, memory circuitry 204, and a bus 300. First bus control circuitry 302 controls the exchange of signals between logic circuitry 202 and bus 300. Second bus control circuitry 303 controls the exchange of signals between memory circuitry 204 and bus 300. Third bus control circuitry 306 is included which controls the exchange of signals between bus 300 and at least one test pin 206. Mode control circuitry 205 is operable as control circuitry 302, 303, and 306. In the operating mode, mode control circuitry 205 activates first bus control circuitry 302 and second bus control circuitry 303. In a memory test mode, mode control circuitry 205 activates second bus control circuitry 303 and third bus control circuitry 306 and deactivates first bus control circuitry 302.

Abstract: A redundancy circuit for a semiconductor memory device utilizes a fuse ladder comprising alternating programmable resistive fuses and signal restorers connected to one another in series. The signal restorers coupled between the fuses prevent the formation of a high impedance resistive line with a floating node when one of the fuses in the ladder is blown.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and also bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: An internal power voltage generating circuit of a semiconductor memory device may be constructed with a voltage sensing circuit (100) and a reference voltage controller (300) providing an internal power voltage int. V.sub.CC of a given reference voltage amplitude V.sub.ref and an external power voltage amplitude ext. V.sub.CC. Thus, when a high voltage over an operating voltage of a chip is applied to a pad (10) of the chip, the internal power voltage is raised to the level of the external power voltage. Therefore, when stress is added to the chip during a "burn-in-test", the defective chip is easily detected. Consequently, the reliability of those semiconductor memory devices subjected to post-manufacturing testing can be improved.

Abstract: The solid state memory device consists of a circuit board based system which is mounted in a 3480 type magnetic tape cartridge form factor housing to make this media physically compatible with the 3480 type magnetic tape cartridges. The interconnection of the solid state memory device with the read/write device is by an optical connections which transfer data between the solid state memory device and the associated read/write device. A plurality of batteries in the solid state memory device provide power for the memory retention capability required of the volatile solid state memory devices. The batteries are recharged by the use of a pair of power rails that are incorporated into the exterior housing of the 3480 form factor cartridge. Thus, the associated read/write device applies power to the solid state memory via these power rails when the 3480 form factor cartridge is placed in the associated read/write device.

Abstract: The invention provides an activator unit which is suitable for use in an identification system and which embodies a memory for the storage of a code therein and means for introducing a selected code into the memory by way of a programming units external to the activator unit.