Bad Bit Patents (Class 365/200)
  • Patent number: 11446564
    Abstract: A first sensor detects a movement of a first apparatus attached to a lower body of a user, and a second sensor detects a movement of a second apparatus attached to an upper body of the user or held by a hand of the user. Then, a virtual object is caused to continue a first action in a virtual space while received outputs from the first sensor and the second sensor both satisfy a condition.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: September 20, 2022
    Assignee: Nintendo Co., Ltd.
    Inventors: Shinji Kitahara, Atsushi Yamazaki
  • Patent number: 11442631
    Abstract: As described herein, an apparatus may include a memory that includes a first portion, a second portion, and a third portion. The apparatus may also include a memory controller that includes a first logical-to-physical table stored in a buffer memory. The memory controller may determine that the first portion is accessed sequential to the second portion and may adjust the first logical-to-physical table to cause a memory transaction performed by the memory controller to access the third portion as opposed to the first portion.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Rajesh N. Gupta
  • Patent number: 11437387
    Abstract: The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: September 6, 2022
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Zhi Tian, Juanjuan Li, Hua Shao, Haoyu Chen
  • Patent number: 11436090
    Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: September 6, 2022
    Assignee: Texas Instmments Incorporated
    Inventors: Devanathan Varadarajan, Ramakrishnan Venkatasubramanian, Varun Singh
  • Patent number: 11430539
    Abstract: Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Troy D. Larsen, Jonathan D. Harms, Glen E. Hush, Timothy P. Finkbeiner
  • Patent number: 11430535
    Abstract: A semiconductor device includes an internal power supply generation circuit that generates an internal power supply voltage from an external power supply voltage and a non-volatile memory circuit. The semiconductor device sets the internal power supply voltage generated by the internal power supply generation circuit based on data stored in the non-volatile memory circuit. A mode signal that switches the internal power supply voltage is set in the non-volatile memory circuit. The mode signal is set to a burn-in mode before a burn-in test and is set to a normal mode after the burn-in test. In the burn-in test, when a VCC burn-in voltage is applied to a VCC terminal to start the semiconductor device, the internal power supply generation circuit generates a VDD burn-in voltage upon receiving the mode signal set in the burn-in mode.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: August 30, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tetsuya Kawashima
  • Patent number: 11429291
    Abstract: Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 11423999
    Abstract: A memory device and its addressing method are disclosed. The memory device includes: an input module for receiving an input signal including an access address, a command, and a decoding selection instruction; a memory array including memory blocks, each having memory units arranged in an array; and a control module including memory block local control units, which respectively connected to one of the memory blocks in one-to-one correspondence. The memory block local control unit includes: at least one decoding unit, which performs redundant decoding or normal decoding to the input signal. The input of the decoding unit is coupled to the input module and the output is coupled to one of the memory units. The device further includes a selection module; the input of the selection module is coupled to the input module, and the output is coupled to the decoding unit. The addressing efficiency of the memory device is improved.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 23, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: WeiBing Shang, Liang Zhang, Jia Wang
  • Patent number: 11417407
    Abstract: The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: August 16, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Balaji Jayaraman, Toshiaki Kirihata, Amit K. Mishra
  • Patent number: 11398272
    Abstract: Along with the miniaturization of the semiconductor memory device, the resistor and parasitic capacitance of the wires become large, which prevents the semiconductor memory device from being speeded up. In a semiconductor memory device having a semiconductor substrate having a main surface, a first memory cell row having a plurality of first memory cells arranged in parallel to a first direction in plan view on the main surface, a first word line connected to the plurality of first memory cells, a first word line driver for changing a potential of the first word line, and a control circuit for outputting a first predecode signal to the first word line driver via the first predecode line in response to a clock signal and an address signal, a repeater is inserted between the control circuit and the first word line driver.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: July 26, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 11393831
    Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ping-Wei Wang, Lien Jung Hung, Kuo-Hsiu Hsu, Kian-Long Lim, Yu-Kuan Lin, Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Choh Fei Yeap
  • Patent number: 11385959
    Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: July 12, 2022
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern
  • Patent number: 11379363
    Abstract: A controller, a memory system, and operating methods thereof are disclosed. A memory system includes at least one nonvolatile memory device and a controller configured to control the nonvolatile memory device. The at least one nonvolatile memory device includes a super block including a plurality of way interleaving memory blocks and each of memory cells included in the plurality of way interleaving memory blocks operates in a first mode which stores N-bit (wherein N is a natural number of 2 or more) data. The controller generates a reproduction super block by replacing at least one bad block among the plurality of way interleaving memory blocks included in the super block with a non-way interleaving spare block and sets each of memory cells included in the non-way interleaving spare block to operate in a second mode which stores M-bit (wherein M is a natural number smaller than N) data.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: July 5, 2022
    Assignee: SK hynix Inc.
    Inventors: Jeen Park, Hyeong Ju Na
  • Patent number: 11373724
    Abstract: The present disclosure includes systems, apparatuses, and methods for improving safety and correctness of data reading in flash memory devices associated with System-on-Chips. An example may include a plurality of sub-arrays, a plurality of memory blocks in each sub-array of the plurality of sub-arrays, a plurality of memory rows in each memory block of the plurality of memory blocks, and a plurality of extended pages in each memory row of the plurality of memory rows, wherein each extended page of the plurality of extended pages includes a group of data, an address, and an error correction code (ECC).
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: June 28, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Alberto Troia, Antonino Mondello
  • Patent number: 11373729
    Abstract: A replacement block pool for a memory device is established. The replacement block pool comprises one or more valid blocks from a set of valid blocks in the memory device determined based on a constraint defining a minimum number of valid blocks for the memory device. A grown bad block is detected in the memory device. The grown bad block is replaced with a replacement block from the replacement block pool in response to detecting the grown bad block.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: June 28, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Tao Liu, Chun Sum Yeung, Xiangang Luo
  • Patent number: 11361814
    Abstract: A memory mat architecture is presented where a column decoder is disposed within the memory array. The location of the column decoder reduces a distance between the column decoder and a target memory cell and thus reduces a distance that a column select signal travels from the column decoder to the target memory cell. A single predecoder is disposed in a bank controller for the memory array. The column decoder may be disposed in the middle of the memory array or offset from the middle near the far edge of the memory array opposite the bank controller. The location of the column decoder enables a reduced array access time to obtain data from the target memory cell.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Hiroshi Akamatsu
  • Patent number: 11348660
    Abstract: Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yoshihito Morishita, Hiroshi Ichikawa
  • Patent number: 11348504
    Abstract: A display apparatus includes a display panel; and a display driver integrated circuit (DDI) chip coupled to the display panel, the DDI chip being configured to generate a display driving signal for driving the display panel based on image data. The DDI chip may include: a first embedded memory device embedded in the DDI chip and configured to store compensation data for compensating for electrical and optical characteristics of a plurality of pixels included in the display panel; a timing controller configured to control signals for driving the display panel, and to generate a data control signal based on the image data and the compensation data; and a data driver configured to provide a data voltage to the display panel according to the data control signal. The first embedded memory device may not include static random access memory (SRAM).
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: May 31, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngmok Kim, Kyunglyong Kang, Jungu Kang, Boyoung Seo, Yongsang Jeong
  • Patent number: 11340802
    Abstract: A memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a plurality of planes and performs a protection operation and a general operation on the plurality of planes. The controller controls an operation of the semiconductor memory device by transferring a Sudden Power Off (SPO) process command, which is generated in response to a Sudden Power Off (SPO) that occurs in the memory system, to the semiconductor memory device. The semiconductor memory device is configured to interrupt the general operations among operations performed on the plurality of planes in response to the SPO process command.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: May 24, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyo Jae Lee
  • Patent number: 11342014
    Abstract: Embodiments herein relate to column select circuitry of a memory device. Specifically, the column select circuitry includes a pre-header circuit coupled to a pre-driver circuit. The pre-header circuit is configured to couple a gate of a transistor of a main column select driver circuit of the column select circuitry to a first voltage supply during operation and a second voltage supply when in a standby state. A voltage of the second voltage supply is greater than a voltage of the first voltage supply. The voltage of the second power supply applied to the gate of the transistor of the main column select driver circuit reduces current leakage through the transistor and enables a reduction in a size of the column select circuitry.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Charles L. Ingalls
  • Patent number: 11341011
    Abstract: A repair circuit includes a plurality of storage circuits suitable for storing repair addresses according to a priority order, each of the storage circuits, among the plurality of storage circuits, storing valid information representing whether the corresponding storage circuit is valid or not and failure information representing whether the corresponding storage circuit is defective or not, and a plurality of enable signal generation circuits respectively corresponding to the plurality of storage circuits and each suitable for generating an enable signal representing whether a corresponding storage circuit is operable or not based on the valid information and the failure information of the corresponding storage circuit and a storage circuit having a preceding priority prior to the corresponding storage.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: May 24, 2022
    Assignee: SK hynix Inc.
    Inventor: Woo Hyun Paik
  • Patent number: 11334458
    Abstract: Methods, systems, and devices for completing memory repair operations interrupted by power loss are described. A command to perform a memory repair of a memory device may be received. A memory repair process of the memory device may be initiated, based on the command. The memory repair process may include programming fuse elements of the memory device. Information associated with the initiated memory repair process may be stored in a non-volatile memory. The memory repair process may be interrupted by a power interruption. During powerup of the memory device, it may be determined that the memory repair process was initiated and not completed before the powerup, based on the stored information. The memory repair process of the memory device may be continued, based on the determination. Upon completion of the memory repair process, the stored information may be cleared.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Alan J. Wilson, Donald Martin Morgan
  • Patent number: 11335422
    Abstract: A semiconductor memory device includes: a first memory cell and switching element coupled in series between a first and second interconnect; a second memory cell and switching element coupled in series between the first and a third interconnect; a third memory cell and switching element coupled in series between the first and a fourth interconnect; and a control circuit. The control circuit is configured to: in a first operation on the first memory cell, upon receipt of a first command, apply a third voltage between the first and second voltage to the third and fourth interconnect; and upon receipt of a second command, apply the first and third voltage to the fourth and third interconnect, respectively.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 17, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Hisanori Aikawa, Eiji Kitagawa
  • Patent number: 11335430
    Abstract: Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: May 17, 2022
    Assignee: Rambus Inc.
    Inventor: Christopher Haywood
  • Patent number: 11335427
    Abstract: A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: May 17, 2022
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Yu-Tao Lin, Tse-Hua Yao, Yi-Fan Chen
  • Patent number: 11335853
    Abstract: A method of manufacturing an OTS device of the invention is a method of manufacturing OTS device including a first conductor, an OTS portion made of chalcogenide, and a second conductor which are layered in order and disposed on an insulating substrate. The manufacturing method includes: a step D of forming a resist so as to coat part of an upper surface of the second conductor; a step E of dry etching a region which is not coated with the resist; and a step F of ashing the resist. In the step E, the second conductor, all of the OTS portion, and an upper portion of the first conductor are removed by an etching treatment once in a depth direction of the region.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: May 17, 2022
    Assignee: ULVAC, INC.
    Inventors: Hyung-Woo Ahn, Kazumasa Horita, Takahiko Sawada, Tadashi Yamamoto
  • Patent number: 11314590
    Abstract: A memory device includes a plurality of memory chips storing and outputting data in response to a control command and an address command, at least one ECC memory chip providing an error check and correction (ECC) function on the data stored and output by the plurality of the memory chips, and a controller, marking a memory chip in which a defective memory cell is detected among the plurality of memory chips, as a defective memory chip, storing data of the defective memory chip in the ECC memory chip, and controlling the defective memory chip to execute a post package repair (PPR).
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: April 26, 2022
    Inventors: Hui Chung Byun, Yoen Hwa Lee, Seung Hun Lee
  • Patent number: 11315621
    Abstract: A device includes an operation control circuit and a drive control signal generation circuit. The operation control circuit generates an internal refresh signal that is activated to perform an active operation for a cell array, the cell array being coupled to a word line that is selected by a row address based on a refresh signal that is activated to perform a refresh operation. In addition, the operation control circuit generates a pre-refresh pulse based on the refresh signal and generates a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit generates a drive control signal to control a drive of an active voltage that is supplied to the word line that is selected by the row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Kyung Mook Kim, Woongrae Kim, Sang Il Park, Seung Hun Lee
  • Patent number: 11309057
    Abstract: Apparatuses and methods for post-package repair (PPR) protection. A device may enter a PPR mode to repair one or more memory addresses by blowing fuses. However, fuses may be incorrectly blown if the device receives row activation (ACT) signals while in the PPR mode. A PPR mask circuit may provide a PPR mask signal if an ACT signal is received while the memory is in the PPR mode. The PPR mask signal may suppress further ACT signals from being provided. In some embodiments, the memory may also include a PPR function circuit, which may monitor one or more signals used as part of PPR operations. If these signals are in an illegal state, the PPR function circuit may suppress PPR operations to prevent damage to the fuse array.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Takaaki Nakamura
  • Patent number: 11308987
    Abstract: Long term optical memory includes a storage medium composed from an array of silicon nanoridges positioned onto the fused silica glass. The array has first and second polarization contrast corresponding to different phase of silicon. The first polarization contrast results from amorphous phase of silicon and the second polarization contrast results from crystalline phase of silicon. The first and second polarization states are spatially distributed over plurality of localized data areas of the storage medium.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: April 19, 2022
    Assignee: Wostec, Inc.
    Inventors: Valery Konstantinovich Smirnov, Dmitry Stanislavovich Kibalov
  • Patent number: 11301145
    Abstract: A storage device configured for connection with a host includes; an output unit configured to provide at least one storage device operating state indication to a user, an input unit configured to accept at least one user input, a main memory configured to temporarily store data received from the host, a storage configured to store the data in non-volatile memory space, and a controller configured to execute a backup operation in response to a user input accepted by the input unit, transfer data from the main memory to the storage during the backup operation, and provide a storage device operating state indication through the output unit during execution of the backup operation.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong Wook Jeong
  • Patent number: 11295832
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Patent number: 11294577
    Abstract: A non-volatile memory includes a plurality of data storage units arranged in an array, a plurality of redundant data storage units arranged in at least one row and a plurality of redundant address storage units arranged in at least one row. A storage size of each of the data storage units is word. Each of the data storage units is addressable by a row address and a column address. One of the redundant data storage units in a first column is configured to substitute for one of the data storage units in a second column. One of the redundant address storage units in a third column is configured to record the row address representative of the substituted one of the data storage units.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 5, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Hua Lu, Hsin-Pang Lu
  • Patent number: 11294590
    Abstract: The present disclosure relates to an electronic device. A storage device having improved memory block use efficiency includes a plurality of memory blocks each including a plurality of pages storing data, an erase page storage configured to store erase page information about erase pages in a victim block among the plurality of memory blocks and a bad block controller configured to replace a fail page in which a program fail occurred with one of the erase pages, based on the erase page information, the fail page being one of the plurality of pages in one of the plurality of memory blocks other than the victim block.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: April 5, 2022
    Assignee: SK hynix Inc.
    Inventor: Chi Eun Kim
  • Patent number: 11282564
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including identifying, among a first plurality of wordlines of a set of pages of the memory device, at least one wordline having a current value of a data state metric satisfying a first condition; determining new values of the data state metric of a second plurality of wordlines of the set of pages, wherein the at least one wordline is excluded from the second plurality of wordlines; and responsive to determining that the new values of the data state metric of one or more wordlines of the second plurality of wordlines satisfy a second condition, performing a media management operation with respect to the one or more wordlines.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
  • Patent number: 11282558
    Abstract: Embodiments of the present disclosure relate to an architecture for random access memory (RAM) circuit configurations. For example, certain embodiments relate to a ferroelectric RAM (FRAM) read only memory (ROM) wordline architecture. A method for power-on reset of a memory can include powering on the memory. The method can also include reading a first flag in a first bit of a first configuration wordline of the memory, wherein the first configuration wordline is one of a plurality of redundant configuration wordlines. The method can further include reading, when the first flag indicates the first configuration wordline is valid, a predetermined number of bytes of the wordline. The method can additionally include configuring operations of the memory based on the predetermined number of bytes, when the first flag indicates the first configuration wordline is valid.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: March 22, 2022
    Assignee: WUXI PETABYTE TECHNOLOGIES CO., LTD.
    Inventor: Feng Pan
  • Patent number: 11276466
    Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: March 15, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Mai Shimizu, Koji Kato, Yoshihiko Kamata, Mario Sako
  • Patent number: 11276452
    Abstract: A memory system includes a memory device including a first area being refreshed according to a first refresh period and a second area begin refreshed according to a second refresh period longer than the first refresh period. The memory system also includes a memory controller configured to generate a write command and a write data corresponding to a first write request and a first data.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: March 15, 2022
    Assignees: SK hynix Inc., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Won Woo Ro, Hyunwuk Lee, Gun Ko, Ipoom Jeong, Min Seong Kim, Yong Tag Song, Sung Jae Lee
  • Patent number: 11270764
    Abstract: The invention relates to a two-bit memory cell structure, and an array architecture and a circuit structure thereof in an in-memory computing chip. The double-bit storage unit comprises three transistors which are connected in series, a selection transistor in the middle is used as a switch, and two charge storage transistors are symmetrically arranged on the two sides of the double-bit storage unit. A storage array formed by the double-bit storage unit is used for storing the weight of the neural network, and multiplication and accumulation operation of the neural network is carried out in a two-step current detection mode. According to the invention, leakage current can be effectively controlled, higher weight storage density and higher reliability are realized, and neural network operation with more practical significance is further realized.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: March 8, 2022
    Assignee: NANJING UCUN TECHNOLOGY INC
    Inventors: Wei Cong, Seow Fong Lim
  • Patent number: 11270769
    Abstract: A non-volatile programmable circuit configurable to perform logic functions, is provided. The programmable circuit can employ two-terminal non-volatile memory devices to store information, thereby mitigating or avoiding disturbance of programmed data in the absence of external power. Two-terminal resistive switching memory devices having high current on/off ratios and fast switching times can also be employed for high performance, and facilitating a high density array. For look-up table applications, input/output response times can be several nanoseconds or less, facilitating much faster response times than a memory array access for retrieving stored data.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 8, 2022
    Assignee: CROSSBAR, INC.
    Inventors: Mehdi Asnaashari, Hagop Nazarian
  • Patent number: 11264066
    Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Chi Wu, Cheng Hung Lee, Chien-Kuo Su, Chiting Cheng, Yu-Hao Hsu, Yangsyu Lin
  • Patent number: 11257561
    Abstract: A semiconductor system includes: a first semiconductor device suitable for outputting a command; and a second semiconductor device suitable for activating a test enable signal based on the command, generating a counting signal representing a toggling number of a row active signal for an activation period of the test enable signal, increasing and outputting an address when the counting signal reaches a target activation number, and deactivating the test enable signal when the counting signal reaches the target activation number and the address has a maximum value.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventor: Sang-Ah Hyun
  • Patent number: 11257565
    Abstract: Filter information including a first temperature level and a second temperature level associated with a test process to be executed on one or more memory components is determined. Information associated with the test process is distributed to a first test component including a first set of memory components and a first temperature control component and a second test component including a second set of memory components and a second temperature control component. First feedback information associated with execution of the test process by the first test component at the first temperature level established by the first temperature control component is received. Second feedback information associated with execution of the test process by the second test component at the second temperature level established by the second temperature control component is received.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Sivagnanam Parthasarathy, Daniel Scobee, Frederick Jensen
  • Patent number: 11257566
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for storing an enable state of an address. The address may be broadcast from a fuse array to a fuse latch, and may be associated with enable information. The fuse latch may include a plurality of enable latch circuits, each of which may receive the enable information in common, and each of which may store the enable information as an enable bit. Each of the enable latch circuits may provide a respective enable signal based on a state of the stored enable bit. An enable logic circuit may provide an overall enable signal with a state determined by the states of all of the enable signals from the plurality of enable latch circuits.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Dennis G. Montierth
  • Patent number: 11244716
    Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a wordline driving circuit including a plurality of sub-wordline decoders respectively connected to the plurality of wordlines, wherein each of the sub-wordline decoders is configured to input a first driving signal to the respectively connected wordline when the wordline is selected, and wherein each sub-wordline decoder is configured to input a predetermined power supply voltage to the respectively connected wordline when the wordline is unselected, The memory device may include a sense amplifier circuit including sense amplifiers connected to the bitlines, and a logic circuit configured to determine a failure of at least one of the memory cell array and the wordline driving circuit.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: February 8, 2022
    Inventors: Jinseok Jeong, Eunju Gi
  • Patent number: 11244741
    Abstract: Memory devices are disclosed. A memory device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, and electronic systems are also disclosed.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, James S. Rehmeyer, Seth A. Eichmeyer
  • Patent number: 11240951
    Abstract: Provided is a method for allocating assemblies to placement lines for placing components on the assemblies, wherein an expected production time is determined for each assembly type of the assemblies to be provided with components and for each placement line, taking into consideration each cycle time for the assembly type on the placement line and the expected number of pieces to be produced for each assembly type. The actual number of pieces to be produced arises according to a predeterminable probability distribution, wherein the possible allocations of assemblies to the placement lines are restricted by the existing infrastructure and/or by user defined specifications, and the allocation of the assemblies to the placement lines is calculated by means of an optimization method.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: February 1, 2022
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Alexander Pfaffinger, Christian Royer
  • Patent number: 11232827
    Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 25, 2022
    Assignee: Highlands, LLC
    Inventors: Craig E. Hampel, Richard E. Perego, Stefanos Sidiropoulos, Ely K. Tsern, Frederick A. Ware
  • Patent number: 11226894
    Abstract: Devices and techniques are disclosed herein for allowing host-based maintenance of a flash memory device. In certain examples, memory write information can be encrypted at the memory device and provided to the host for updating and maintaining memory device maintenance statistics.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: David Aaron Palmer, Christian M. Gyllenskog, Jonathan Scott Parry, Stephen Hanna
  • Patent number: 11222670
    Abstract: Various implementations described herein are directed to an implementation of a higher order multiplexer using lower order multiplexers. In an embodiment, the implementation requires a slight modification to the existing circuitry design of the lower multiplexers. A plurality of multiplexers may be coupled with each other such that a common input port and output port is formed. Using an enable signal, only one of the coupled multiplexers may be enabled at a time while the remaining multiplexers are switched off. Therefore, upon receiving a select signal indicating an address of a memory cell, the lower multiplexers coupled together function as a higher order multiplexer in selecting the appropriate column corresponding to the memory cell.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 11, 2022
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Nicolaas Klarinus Johannes Van Winkelhoff, El Mehdi Boujamaa, Bo Zheng, Fakhruddin Ali Bohra, Cyrille Nicolas Dray, Ashish Bhardwaj, Durgesh Kumar Dubey