Abstract: Methods, systems, and devices for memory traffic monitoring are described. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a characteristic related to an operational bias of circuits of the memory device. The memory device may use the characteristic (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

Abstract: A semiconductor memory device includes a refresh counter generating a counting address that is sequentially increasing according to a refresh command; an active latch generating an active address corresponding to an input address according to an active command; and a refresh control circuit repeatedly performing a first refresh period and a second refresh period according to the refresh command, and controlling selective refresh of one or more word lines corresponding to the counting address selected based on one or more high bits of the active address during the first refresh period and controlling sequential refresh of the word lines corresponding to the counting address during the second refresh period.

Abstract: Systems and methods described herein may enable a memory system to selectively provide a signal boost to a word line to precharge the word line. A memory device may include voltage shaping circuitry and a memory controller. The memory controller may cause the voltage shaping circuitry to adjust a characteristic of a word line select control signal transmitted via the word line prior to the word line select control signal being transmitted to a memory cell.

Abstract: A first sensor detects a movement of a first apparatus attached to a lower body of a user, and a second sensor detects a movement of a second apparatus attached to an upper body of the user or held by a hand of the user. Then, a virtual object is caused to continue a first action in a virtual space while received outputs from the first sensor and the second sensor both satisfy a condition.

Abstract: A storage device may include storage for data. A host interface may receive a write request from a host at the storage device. The write request may include a data chunk and a data identifier (ID). A class ID determiner circuitry may determine a class ID for the data chunk. A mapping table may map the data ID to the class ID.

Abstract: An integrated circuit device having a mechanism to check calibration of memory cells configured to perform operations of multiplication and accumulation. The integrated circuit device programs, in a first mode, threshold voltages of first memory cells in a memory cell array to store weight data, and programs, in a second mode, threshold voltages of second memory cells in the memory cell array to store a first result of applying an operation of multiplication and accumulation to a sample input and the weight data. During a calibration check, the integrated circuit device performs the operation using the first memory cells to obtain a second result, and compares the first result, retrieved from the second memory cells, and the second result to determine whether calibration of output current characteristics of the first memory cells programmed in the first mode is corrupted.

Abstract: A magnetic memory device includes a first magnetic memory cell extending in a first direction and including a first magnetic domain and a second magnetic domain arranged in the first direction, and a second magnetic memory cell extending in the first direction and including a third magnetic domain and a fourth magnetic domain arranged in the first direction. A magnetization direction of the first magnetic domain and a magnetization direction of the second magnetic domain are anti-parallel to each other. A magnetization direction of the third magnetic domain and a magnetization direction of the fourth magnetic domain are anti-parallel to each other. The third magnetic domain of the second magnetic memory cell is spaced apart from the second magnetic domain of the first magnetic memory cell in a second direction intersecting the first direction.

Abstract: An MRAM-based vector multiplication device, such as can be used for inferencing in a neural network, is presented that is ultralow power, low cost, and does not require special on-chip programming. A crosspoint array has an MRAM cell at each crosspoint junction and periphery array circuitry capable of supplying independent input voltages to each word line and reading current on each bit line. Vector multiplication is performed as an in-array multiplication of a vector of input voltages with matrix weight values encoded by the MRAM cell states. The MRAM cells can be individually programmed using a combination of input voltages and an external magnetic field. The external magnetic field is chosen so that a write voltage of one polarity reduces the anisotropy sufficiently to align the cell state with the external field, but is insufficient to align the cell if only half of the write voltage is applied.

Abstract: Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.

Abstract: According to one implementation of the present disclosure, a circuit comprises: a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array. According to one implementation of the present disclosure, a method includes: providing an excitation stress on one or more canary circuits corresponding to a grouping of bitcells in a memory array; detecting at least a partial breakdown of the one or more canary circuits; and generating a flag.

Abstract: A storage system performing an overwrite, a host system controlling the storage system, and an operating method of the storage system, wherein the storage system includes a memory device; and a controller that receives new data and an overwrite request from the host system, wherein the overwrite request includes a first logical address for old data and a second logical address for the new data, and performs an overwrite operation by writing the new data corresponding to the second logical address to the memory device and invalidating the old data corresponding to the first logical address according to the overwrite request.

Abstract: Apparatuses, systems, and methods are disclosed for battery charging and power output. A system may include a plurality of hot-swappable, stackable slices for battery charging and power output. A slice may include communication circuitry for communication among the slices. A slice may include power input conversion circuitry, power storage circuitry, and/or power output conversion circuitry. A slice may include at least one electrical connector for connecting to a second slice. The at least one electrical connector may include connections for power and communications. A slice may include at least one mechanical connector for connecting to the second slice.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to program and verify the memory cells during a program operation. The memory cells associated with predetermined ones of the data states are not verified until the memory cells associated with specific prior ones of the data states finish programming to define verify windows ranging between each one of the specific prior ones of the data states and each one of the predetermined ones. The control means adjusts the verify windows in response to the memory cells associated with one of the specific prior ones of the data states not finishing programming before the one of the predetermined ones of the at least one of the verify windows is verified.

Abstract: A method for repairing a memory device includes: performing error detection on memory units of the memory device; temporarily storing each of unit addresses of detected error units in registers until the number of the detected error units reaches a first preset number, where the detected error units are damaged memory units, and each of the detected error unit occupies a respective one of the registers, and each of the unit addresses comprises a row address; successively selecting one of the registers as a target register; determining whether a row addresses in the target register exists in a reference storage module, where a repaired row address or an unrepaired row address is stored in the reference storage module; and repairing error units that are not repaired through the row addresses according to a result of the determination.

Abstract: A lamp may include a display device including a first region and a second region having mutually different references for the number of a failed pixel, and a controller to control the display device.

Abstract: Methods, systems, and devices for resuming write operation after suspension are described. A memory system may be configured to determine an upper limit of a threshold voltage of a page of a block at which a performance of a write operation was suspended based at least in part on an indication to resume the performance of the write operation that was previously suspended at a memory system; determine a difference between a first quantity of a first logic state stored in the page and a second quantity of the first logic state associated with an unsuspended write operation based at least in part on determining the upper limit of the threshold voltage; and resume the performance of the write operation based at least in part on determining the difference between the first quantity of the first logic state and the second quantity of the first logic state.

Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

Abstract: A repair system and a repair method for a semiconductor structure, a storage medium, and an electronic device are provided. The semiconductor structure includes a main memory area and a redundant memory area. The repair system of the present disclosure includes a test circuit, a control circuit, and a repair circuit. The test circuit is configured to perform defect detection on the main memory area to determine a failed cell of the main memory area and position information of the failed cell. The control circuit is connected to the test circuit, and is configured to store the position information of the failed cell and generate a repair signal according to the position information. The repair circuit is connected to the control circuit, and is configured to receive the repair signal and perform a repair operation on the failed cell through the redundant memory area.

Abstract: The present disclosure provides an improved device that can be used to sense and characterize a variety of materials. The device may be used for a variety of applications, including genome sequencing, protein sequencing, biomolecular sequencing, and detection of ions, molecules, chemicals, biomolecules, metal atoms, polymers, nanoparticles and the like.

Abstract: An example method may be used to perform concurrent compensation in a memory array. The example method may include decoding a prime row address corresponding to a respective prime memory cell row of a first row section of a memory array mat to provide a prime section signal, and in response to a determination that the prime row address matches a defective prime row address, providing a redundant section signal corresponding to a respective redundant memory cell row of a second row section of the memory array mat. In response to the prime section signal, initiating a first threshold voltage compensation operation on first sensing circuitry coupled to the first row section; and in response to the redundant section signal indicating a defective prime row, initiating a second threshold voltage compensation operation on second sensing circuitry coupled to the second row section concurrent with the first threshold voltage compensation operation.

Abstract: The present invention discloses a memory test circuit having repair information maintaining mechanism. A repairing control circuit controls a MBISR circuit to perform a self-repair procedure on a memory circuit and includes a remapping storage circuit and a latch storage circuit. The remapping storage circuit receives and stores repairing information generated by the MBISR circuit after the self-repair procedure finishes. The latch storage circuit is electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit to receive and store the repairing information from the remapping storage circuit such that the remapping circuit accesses the repairing information therefrom when a scan test is performed on the remapping storage circuit based on a scan chain to perform remapping and repairing on the memory circuit based on the repairing information and a redundant structure of the memory circuit.

Abstract: A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state. The evaluation unit is configured for evaluating the plurality of memory cells in the first state to obtain a first evaluation result, and for evaluating the plurality of memory cells in the second state to obtain a second evaluation result.

Abstract: An apparatus includes memory cells. A first memory cell of the memory cells includes a first write port laid out in a first doping region and a first read port laid out in a second doping region. The first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.

Abstract: Embodiments of the invention relate to the processing of a safety-related user program for a safety control system. The generation of the machine code for the safety-related control takes place on a cloud computer. The data required for generating the machine code such as the source code data of the user program, are secured with a unique signature and transmitted to the cloud computer. The machine code is generated on the cloud computer from the transmitted data. A new signature is generated via the resultant data and the signature from the preceding step. The entire safety life cycle is also covered, since each step in the life cycle is automatically documented and may be clearly tracked at any time, and corruptions of a step may be detected.

Abstract: A semiconductor device includes a plurality of built-in memories, and each of the built-in memories includes a plurality of memory cells. Each built-in memory includes a selector circuit that connects a selected memory cell among the memory cells to an outside, a memory cell relief circuit that, when a fault has occurred in one of the memory cells, transmits, to the selector circuit, a relief signal configured to connect a normal memory cell to the outside without connecting the one of the memory cells in which the fault has occurred, to the outside, and switches selection in the selector circuit, and an abnormality detection circuit that performs abnormality detection for the memory cell relief circuit, based on a temporal change in the relief signal output from the memory cell relief circuit.

Abstract: An electronic device includes an internal mode control circuit suitable for generating a burst control signal, a blocking control signal and an internal voltage control signal based on a refresh cycle when an internal mode is performed in a self-refresh operation, a refresh control circuit suitable for generating a refresh signal for performing a refresh operation every refresh cycle when the self-refresh operation is performed, generating the refresh signal every set cycle based on the burst control signal when the internal mode is performed, and blocking the generation of the refresh signal based on the blocking control signal, and an internal voltage generation circuit suitable for adjusting a level of an internal voltage for the refresh operation based on the internal voltage control signal.

Abstract: Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

Abstract: A read and write method includes: applying a read command to a memory device, the read command indicating address information; reading data to be read from a storage unit corresponding to the address information indicated by the read command; and if an error occurs in the data to be read, associating the address information indicated by the read command with a spare storage unit, and backing up the address information indicated by the read command and association information between the address information and the spare storage unit in a non-volatile storage unit based on a preset rule.

Abstract: Systems and methods are provided for a memory device. A memory device includes a memory array, a column selection circuit coupled to the memory array, where the column selection circuit is configured to generate a column selection signal, and a sense amplifier configured to receive data signals from the memory array. An enable signal generating circuit is configured to generate a first enable signal and a second enable signal. The column selection circuit generates the column selection signal based on the first enable signal, and the sense amplifier is configured to receive a data signal from the memory array in response to the second enable signal.

Abstract: A storage device includes a storage circuit, a reading circuit, a first check circuit, and a second check circuit. The storage circuit includes a plurality of sense amplifier arrays and a plurality of storage unit arrays which are arranged alternately. A first data wire is electrically connected to each of the sense amplifier arrays. The reading circuit is configured to read data on the first data wire. Both the first check circuit and the second check circuit are electrically connected to the reading circuit. The reading circuit is configured to transmit a part of the read data to the first check circuit for error checking and/or correcting, and transmit another part of the read data to the second check circuit for error checking and/or correcting. The data transmitted to the first check circuit and the data transmitted to the second check circuit are respectively from adjacent sense amplifier arrays.

Abstract: In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and control logic coupled to the I/O circuit. The array of memory cells includes a plurality of banks including a plurality of main banks and a redundant bank. The I/O circuit is coupled to each pair of adjacent banks of the plurality of banks and configured to direct a piece of data to or from either bank of each pair of adjacent banks. The control circuit is configured to select one bank of each pair of adjacent banks based on bank fail information indicative of a failed main bank of the plurality of main banks. The control circuit is further configured to control the I/O circuit to direct the piece of data to or from the selected bank of each pair of adjacent banks.

Abstract: A method for determining a repaired line and a repairing line in a memory includes the following: writing first preset data sets into respective lines in a normal region, and writing second preset data sets into respective lines in a redundancy region; repairing the lines in the normal region by using the lines in the redundancy region; reading data from the lines in the normal region after repairing; and determining a repaired line in the normal region and a repairing line in the redundancy region according to the data of the lines in the normal region, the data of the lines in the normal region after repairing, or the data of the lines in the redundancy region.

Abstract: A method and an apparatus for determining a repair location for a redundancy circuit, and a method for repairing an integrated circuit are provided. At least one fail bit of a chip to be repaired is determined. At least one initial repair location for the redundancy circuit is initially assigned according to the at least one fail bit. At least one potential fail line is determined according to the at least one initial repair location. At least one predicted repair location is determined according to the at least one potential fail line. Each of the at least one predicted repair location is a location with a higher probability that a new fail bit appears. At least one final repair location for the redundancy circuit is determined according to the at least one fail bit and the at least one predicted repair location.

Abstract: Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures are provided. In some embodiments methods may include contacting a substrate with a first reactant comprising a transition metal precursor, contacting the substrate with a second reactant comprising a niobium precursor and contacting the substrate with a third reactant comprising a nitrogen precursor. In some embodiments related semiconductor device structures may include a semiconductor body and an electrode comprising a transition metal niobium nitride disposed over the semiconductor body.

Abstract: A semiconductor memory device includes a resistive change memory device including a control circuit block and a plurality of memory decks electrically connected with the control circuit block. The semiconductor memory device includes a pattern generation block, a position correction block and a position decision block. The pattern generation block receives a row address, a column address and a deck selection signal to generate a plurality of pattern generation signals to select a plurality of memory cells in the memory deck in various patterns. The position correction block receives a temporary code for classifying the memory cells into a temporary near cell region and a temporary far cell region and for reflecting a position of the memory deck in the temporary code to output a correction code.

Abstract: Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system. In one embodiment, a hierarchical ROM encoding system comprises two levels of ROM encoders that are used to detect an address fault. In another embodiment, a hierarchical ROM encoding system comprises three levels of ROM encoders that are used to detect an address fault.

Abstract: Methods, systems, and devices for self-repair verification are described. A memory system may receive, at a memory device, a command to initiate a repair operation. The memory system may perform the repair operation by replacing a first row of memory cells of the memory device with a second row of memory cells of the memory device. The memory system may write first data to the second row of memory cells, and read second data from the second row of memory cells, based on a stored indication associated with the replacement of rows. The memory device may output an error flag with a first value based at least in part on reading the second data, and the first value of the error flag may indicate that the repair operation was successfully performed based at least in part on the second data matching the first data.

Abstract: A memory device includes a memory bank that includes a first set of memory rows in a first section of the memory bank, a first set of redundant rows in a first section of the memory bank, a second set of memory rows in a second section of the memory bank, and a second set of redundant rows in the second section of the memory bank. The memory bank also includes a repeater blocker circuit that when in operation selectively blocks a signal from transmission to the second section of the memory bank and blocker control circuitry that when in operation transmits a control signal to control the selective blocking of the signal by the repeater blocker circuit.

Abstract: According to a certain embodiment, the semiconductor integrated circuit includes a multi-chip package comprising a plurality of memory chips, and a controller configured to control the multi-chip package. Each of the plurality of memory chips includes a logic control unit including a logic unit circuit configured to detect a potential from a wiring pad. The logic unit circuit determines a master chip or a slave chip on the basis of the potential detected from the wiring pad, the master chip transmits a pulse count and a status response command to the slave chip, so that the slave chip sets a logical unit number of its own memory chip, and the master chip sets a total number of chips loaded on the basis of status information from the slave chip.

Abstract: Methods, systems, and devices for memory wear management are described. A device may include an interface controller and a non-volatile memory. The interface controller may manage wear-leveling procedures for memory banks in the non-volatile memory. For example, the interface controller may select a row in a memory bank for the wear-leveling procedure. The interface controller may store data from the row in a buffer in the interface controller. The interface controller may then transfer the data to the non-volatile memory so that the non-volatile memory can write the data to a second row of the memory bank.

Abstract: An apparatus with a memory array having a plurality of memory cells. The apparatus also including a memory built-in self-test circuit to test the memory array. The memory built-in self-test circuit includes one or more processing devices to write a data pattern to one or more memory cells to be tested in the memory array, pause for a time period corresponding to a predetermined pause time setting, and read the written data pattern from the one or more memory cells after the time period has elapsed. The predetermined pause time setting is automatically adjusted based on memory device conditions, which can include the temperature of the apparatus.

Abstract: An imaging device according to the present disclosure has a stacked chip structure in which at least two semiconductor chips, that are a first semiconductor chip provided with a pixel circuit and a second semiconductor chip including an analog-to-digital (AD) conversion circuit which is provided so as to correspond to the pixel circuit, are stacked. The AD conversion circuit includes a latch circuit that retains a digital code after AD conversion and a transfer circuit that transfers the digital code after AD conversion. Further, a failure detection circuit for detecting a failure of the AD conversion circuit is provided. The failure detection circuit performs failure detection by writing a test pattern for failure detection into the latch circuit via the transfer circuit, then reading the test pattern from the latch circuit via the transfer circuit, and comparing the read test pattern with an expected value.

Abstract: A method of operating a controller includes randomly transmitting a first command to a non-volatile memory device upon a read request from a host; receiving first read data corresponding to the first command from the non-volatile memory device; determining whether the number of first error bits of the first read data is greater than a first reference value; determining whether the number of first error bits is greater than a second reference value, when the number of first error bits is not greater than the first reference value; storing a target wordline in a health buffer, when the number of first error bits is greater than the second reference value; periodically transmitting a second command to the non-volatile memory device; and receiving second read data corresponding to the second command from the non-volatile memory device.

Abstract: A repair circuit includes: a plurality of redundant memory cells, each redundant memory cell being configured with a state signal; and a repair module connected to the plurality of redundant memory cells and configured to determine target memory cells from the redundant memory cells based on the state signals and repair defective memory cells through the target memory cells. The target memory cells are in one-to-one correspondence to the defective memory cells. The repair module can repair, at each of multiple repair stages, different defective memory cells, the plurality of redundant memory cells being shared at the multiple repair stages.

Abstract: A storage apparatus includes a control chip, a storage chip, a power interface configured to receive a first voltage, a first variable-voltage circuit. An input end of the first variable-voltage circuit is coupled to the power interface. The first variable-voltage circuit is configured to convert the first voltage into a second voltage, and provide the second voltage to the control chip and a second variable-voltage circuit, where an input end of the second variable-voltage circuit is coupled to the power interface. The second variable-voltage circuit is configured to convert the first voltage into a third voltage and provide the third voltage to the control chip and the storage chip.

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.

Abstract: Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

Abstract: Provided are a data transmission circuit and a memory. The data transmission circuit includes: a normal reading module, which is connected to a normal storage array and configured to read and output data from the normal storage array; a redundant reading module, which is connected to a redundant storage array, and configured to read and output data from the redundant storage array; and an error detection operation module, which is connected to the normal reading module and the redundant reading module respectively, and configured to synchronously receive the read data output from the normal reading module and the redundant reading module, and perform error detection operation on the read data.

Abstract: A method for rebuilding data when changing erase block sizes in a storage system is provided. The method includes determining one or more erase blocks to be rebuilt and allocating one or more replacement erase blocks, wherein the one or more erase blocks and the one or more replacement erase blocks have differing erase block sizes. The method includes mapping logical addresses, for the one or more erase blocks, to the one or more replacement erase blocks and rebuilding the one or more erase blocks into the one or more replacement erase blocks, in accordance with the mapping.

Abstract: An apparatus is provided which comprises: a magnetic junction having a magnet with a first magnetization (e.g., perpendicular magnetization); a first structure adjacent to the magnetic junction, wherein the first structure comprises metal (e.g., Hf, Ta, W, Ir, Pt, Bi, Cu, Mo, Gf, Ge, Ga, or Au); an interconnect adjacent to the first structure; and a second structure adjacent to the interconnect such that the first structure and the second structure are on opposite surfaces of the interconnect, wherein the second structure comprises a magnet with a second magnetization (e.g., in-plane magnetization) substantially different from the first magnetization.