Bad Bit Patents (Class 365/200)
  • Patent number: 10692567
    Abstract: A method for assisting a memory cell in an access operation is provided. The method includes: setting a supply voltage to a first supply voltage level to determine a reference probability value of the memory cell applied by the first supply voltage level; applying an assist voltage to an access line coupled to the memory cell, and setting the supply voltage to a second supply voltage level to determine a relationship between the assist voltage and the access failure probability of the memory cell applied by the second supply voltage level; determining, from the relationship, a target assist voltage level of the assist voltage corresponding to the reference probability value; and providing an assist circuit configured to apply the target assist voltage level to the access line during the access operation, wherein the memory cell is applied by the second supply voltage level during the access operation.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: June 23, 2020
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventors: Zhi-Xian Chou, Wei-Chiang Shih
  • Patent number: 10692582
    Abstract: A semiconductor memory device a memory cell array and a repair control circuit. The memory cell array including a normal cell region and a redundancy cell region, the normal cell region including a plurality of normal region groups, and redundancy cell region configured to replace failed memory cells of the normal cell region. The repair control circuit configured to, determine a target normal region group from among the plurality of normal region groups based on an input address, extract target fail addresses from among a plurality of fail addresses based on the target normal region group, and control a repair operation based on the target fail addresses and the input address.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: June 23, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung-Ryun Kim
  • Patent number: 10678688
    Abstract: A semiconductor device includes a decoder configured to receive an extended mode register set (EMRS) code including specific information, and decode the received EMRS code to acquire the specific information; a peripheral controller configured to generate a control signal based on the specific information; and a peripheral region including a plurality of buffers, the plurality of buffers being configured to be controlled by the control signal, wherein the specific information includes information indicating an expected bandwidth of input data that is to be input to one of the plurality of buffers.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 9, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: SukYong Kang, Han-Gi Jung
  • Patent number: 10681136
    Abstract: Apparatus and systems may include a first node group include a first network node coupled to a memory, the first network node including a first port, a second port, a processor port, and a hop port. Network node group may include a second network node coupled to a memory, the second network node including a first port, a second port, a processor port, and a hop port, the hop port of the second network node coupled to the hop port of the first network node and configured to communicate between the first network node and the second network node. Network node group may include a processor coupled to the processor port of the first network node and coupled to the processor port of the second network node, the processor configured to access the first memory through the first network node and the second memory through the second network node. Other apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventor: David R. Resnick
  • Patent number: 10679715
    Abstract: A nonvolatile memory apparatus may include a first memory cell array, a second memory cell array, and a data sensing circuit. The first memory cell array may include a plurality of first memory cells coupled between a plurality of first word lines and a bit line. The second memory cell array may include a plurality of second memory cells coupled between a plurality of second word lines and the bit line. The data sensing circuit may define a sensing period and a latch period based on a power-up signal, may precharge a sensing node coupled to the bit line, may sense and amplify a voltage level of the sensing node, during the sensing period, and may generate an output signal by latching the sensed and amplified signal during the latch period.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventor: Keun Sik Ko
  • Patent number: 10675881
    Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 9, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista, Victorien Brecte
  • Patent number: 10671523
    Abstract: A memory system include: a plurality of first memory devices each coupled to a first channel and including a plurality of first memory blocks; a plurality of second memory devices each coupled to a second channel and including a plurality of second memory blocks; a first access controller suitable for controlling an access to the first memory blocks; a second access controller suitable for controlling an access to the second memory blocks; and a bad block controller suitable for: selecting one between the first and second access controllers by comparing bad physical addresses corresponding to bad blocks included in each of the first and second memory devices with first and second physical addresses respectively corresponding to the first and second memory blocks, and transferring one of the first and second physical addresses and substitute physical address that replace the bad physical addresses.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventor: Byung-Soo Jung
  • Patent number: 10672427
    Abstract: Long term optical memory includes a storage medium composed from an array of silicon nanoridges positioned onto the fused silica glass. The array has first and second polarization contrast corresponding to different phase of silicon. The first polarization contrast results from amorphous phase of silicon and the second polarization contrast results from crystalline phase of silicon. The first and second polarization states are spatially distributed over plurality of localized data areas of the storage medium.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: June 2, 2020
    Assignee: Wostec, Inc.
    Inventors: Valery Konstantinovich Smirnov, Dmitry Stanislavovich Kibalov
  • Patent number: 10666517
    Abstract: The application is directed to a cloud computing platform. The cloud computing platform includes a memory having instructions stored thereon for managing updates the cloud computing platform. The cloud computing platform also includes a controller, operably coupled to the memory. The controller is configured to execute an instruction of identifying an update for an existing cloud computing service operating on the cloud computing platform. The controller is also configured to download the update for the existing service. The controller is also configured to merge the differences between the downloaded update and the existing service to create a new image. The controller is also configured to test the new image offline. Further, the controller is configured to validate the new image online.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: May 26, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Rahim Maknojia, Cheng Wei, Shawn Lucas, Robert S. T. Gibson
  • Patent number: 10665316
    Abstract: A memory device is provided, including a built-in self-test circuit and a redundancy address replacement circuit. The built-in self-test circuit coupled to a main memory cell array is configured to performing a built-in self-test process on the main memory cell array so as to provide a built-in self-test signal. The redundancy address replacement circuit includes a first redundancy circuit and a second redundancy circuit. The first redundancy circuit replaces portion of word line addresses of the main memory cell array with that of a redundancy memory block according to first redundancy data signals generated by a first test process. The second redundancy circuit, coupled to the first redundancy circuit, replaces the failure word line addresses detected in the main memory cell array with another portion of word line addresses of the redundancy memory block according to the built-in self-test signal.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 26, 2020
    Assignee: Winbound Electronics Corp.
    Inventor: Yuji Nakaoka
  • Patent number: 10665321
    Abstract: The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wang, Ching-Huang Wang, Chun-Jung Lin, Tien-Wei Chiang, Meng-Chun Shih, Kuei-Hung Shen
  • Patent number: 10659048
    Abstract: A mixed signal system includes a digital domain and an analog domain. The analog domain includes a plurality of BARs. Each BAR includes addressable registers. The digital domain includes an interface configured to communicate with the analog domain, e.g., write data to an addressable register within a BAR by transmitting a first select signal to select a first BAR of the plurality of BARs. The interface transmits an address of the addressable register of the first BAR and broadcasts the write data to the first BAR and at least one BAR other than the first BAR. The analog domain transmits data from a second BAR of the plurality of BARs to the digital domain by gating a select BAR signal associated with each BAR with its corresponding content stored therein to form respective BAR output and further by gating the respective BAR outputs with one another.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: May 19, 2020
    Assignee: InvenSense, Inc.
    Inventors: Amr Zaky, Hou-Yi Wang, Sarvesh Shrivastava
  • Patent number: 10649028
    Abstract: Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Satya R. S. Bhamidipati, Raghu G. Gopalakrishnasetty, Mary P. Kusko, Cedric Lichtenau
  • Patent number: 10651376
    Abstract: The present invention relates to a memory device comprising a first electrode (27), a second electrode (28) and an active portion that can change conductive state, positioned between a first face of the first electrode (27) and a first face of the second electrode (28). The first electrode (27) comprises an upper portion forming the first face of the first electrode (27). At least one out of the upper portion and the active portion that can change conductive state comprises a porous layer (15).
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 12, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sophie Bernasconi, Christelle Charpin-Nicolle, Aomar Halimaoui
  • Patent number: 10635331
    Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jameer Mulani, Kapil Sundrani, Anindya Rai
  • Patent number: 10636508
    Abstract: A semiconductor system includes: a first semiconductor device suitable for outputting a command; and a second semiconductor device suitable for activating a test enable signal based on the command, generating a counting signal representing a toggling number of a row active signal for an activation period of the test enable signal, increasing and outputting an address when the counting signal reaches a target activation number, and deactivating the test enable signal when the counting signal reaches the target activation number and the address has a maximum value.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventor: Sang-Ah Hyun
  • Patent number: 10636841
    Abstract: A semiconductor device includes: a first metal-oxide semiconductor (MOS) transistor and a second MOS transistor on a substrate; a magnetic tunneling junction (MTJ) between the first MOS transistor and the second MOS transistor; a first interlayer dielectric (ILD) layer on one side of the MTJ and above the first MOS transistor; and a second ILD layer on another side of the MTJ and above the second MOS transistor.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: April 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-I Chou, Hung-Yueh Chen
  • Patent number: 10636824
    Abstract: A method for forming a high dielectric constant (high-?) dielectric layer on a substrate including performing a pre-clean process on a surface of the substrate. A chloride precursor is introduced on the surface. An oxidant is introduced to the surface to form the high-? dielectric layer on the substrate. A chlorine concentration of the high-? dielectric layer is lower than about 8 atoms/cm3.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Tsai, Horng-Huei Tseng, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng, Hsin-Chieh Huang
  • Patent number: 10629249
    Abstract: A semiconductor system includes a first semiconductor device and a first semiconductor device. The first semiconductor device outputs a clock, a chip selection signal and addresses. The second semiconductor device generates a masking signal from the addresses inputted in synchronization with a first pulse of the clock in response to the chip selection signal and decodes internal addresses generated from the addresses inputted in synchronization with a second pulse of the clock to select a word line. The second semiconductor device controls a connection between an address decoder and a fuse circuit in response to the masking signal. The address decoder selects the word line.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: April 21, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang Hyun Ku, HongJung Kim
  • Patent number: 10622091
    Abstract: A nonvolatile memory device includes a memory cell array and a bad block remapping circuit. The memory cell array includes a first mat and a second mat that are paired with each other. The first mat includes a plurality of first memory blocks. The second mat includes a plurality of second memory blocks. A first selection memory block among the plurality of first memory blocks and a second selection memory block among the plurality of second memory blocks are accessed based on a first address. The bad block remapping circuit generates a first remapping address based on the first address when it is determined that the first selection memory block is defective. A first remapping memory block among the plurality of first memory blocks and the second selection memory block are accessed based on the first remapping address.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jun Lee, Bong-Soon Lim, Sang-Won Park
  • Patent number: 10614901
    Abstract: A memory controller includes a memory that stores therein data corresponding to a distribution of write durations measured from a nonvolatile memory device of a specific model, and a processor that measures a write duration taken to write data to a memory cell in a nonvolatile memory device of a same model as the specific model and that determines whether or not the memory cell is defective by evaluating, based on the data corresponding to the distribution, a displacement of the measured write duration from a center portion of the distribution.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: April 7, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Masazumi Maeda
  • Patent number: 10613924
    Abstract: A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: April 7, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Liji Gopalakrishnan
  • Patent number: 10615167
    Abstract: A memory device includes a main one-time programmable (OTP) memory cell connected to a main word line and a main bit line; a redundant OTP memory cell connected to a redundant word line and a redundant bit line; and an input/output circuit configured to, during a program operation to program the main OTP memory cell and the redundant OTP memory cell, electrically separate the main bit line and the redundant bit line and form a first program current path to the main bit line and a second program current path to redundant bit line, wherein the first program current path and the second program current path are independent from each other.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang-Seok Lee
  • Patent number: 10613931
    Abstract: A memory device includes memory banks that each include a bank array having memory cells, a row decoder, and a column decoder. Each memory cell includes a capacitor and a transistor, a write circuit to store input data received at the memory device from a test device in the bank array, a read circuit to generate output data based on reading data stored in the bank array, a parity data management circuit to generate first parity data smaller than the input data using the input data, generate second parity data smaller than the output data using the output data, and generate third parity data using the first and second parity data, and an output circuit to output at least one of the first, second, and third parity data as verification data, in response to receipt of a request from the test device at the memory device.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong Yun Cha, June Hyun Park
  • Patent number: 10607659
    Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: March 31, 2020
    Assignee: Arm Limited
    Inventors: Mudit Bhargava, Shidhartha Das, George McNeil Lattimore, Brian Tracy Cline
  • Patent number: 10600498
    Abstract: A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array including a plurality of fuse banks. A fuse bank of the plurality of fuse banks includes a fuse circuit, which includes a fuse latch having first input circuitry. The fuse latch is implemented to store a first bit of a first memory address received at the first input circuitry. The fuse circuit also includes a matching circuit coupled to the first input circuitry. The matching circuit is implemented to receive a first bit of a second memory address at the first input circuitry and to output, at output circuitry, a comparison result based at least in part on the first bit of the first memory address and the first bit of the second memory address.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Patent number: 10600465
    Abstract: A magnetic storage device includes a first wire extending along a first direction and a plurality of spin orbit torque magnetic random access memory (SOT-MRAM) devices. Each of the plurality of SOT-MRAM devices is disposed at a respective position along the first wire. The magnetic storage device further includes write circuitry, including: a first transistor coupled to the first wire to apply a first write current along the first wire in the first direction; and a second transistor to select an individual SOT-MRAM device and apply a second write current to the individual SOT-MRAM device concurrently with the application of the first write current. The second write current is along an axis of the individual SOT-MRAM device. The magnetic storage device further includes readout circuitry to read a data value stored by the individual SOT-MRAM device.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 24, 2020
    Assignee: SPIN MEMORY, INC.
    Inventor: Satoru Araki
  • Patent number: 10599583
    Abstract: A pre-match method includes: receiving an initial address; gradually increasing a current address according to the initial address; adding an offset value to the current address for generating a match address; generating a hit parameter by comparing the match address with at least one defect address stored in the mapping table; generating a redundancy address corresponding to the match address; and setting a Y-direction address as either the redundancy address or the current address according to the hit parameter.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: March 24, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yi-Ting Lai, Chih-He Chiang
  • Patent number: 10594302
    Abstract: A voltage detection system includes a first voltage detector and a second voltage detector. The first voltage detector is configured for detecting whether an input voltage reaches a first voltage level. The second voltage detector, coupled to the first voltage detector, is configured for detecting whether the input voltage reaches a second voltage level. The first voltage detector outputs a control signal to control a status of the second voltage detector according to a detection result of the first voltage detector.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: March 17, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Weirong Chen
  • Patent number: 10592141
    Abstract: Apparatuses, systems, and methods are disclosed for error characterization for control of non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to acquire an error characterization for a region of memory. Also, an error characterization may comprise information about one or more types of errors to which a region of memory is susceptible. A controller may be configured to assign a region of memory into a logical group based on an error characterization. Further, a logical group may comprise a plurality of regions of memory. Additionally, a controller may be configured to service a write request by striping data across multiple regions assigned to a logical group.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: March 17, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Vinay Vijendra Kumar Lakshmi, Raghavendra Gopalakrishnan
  • Patent number: 10591544
    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: March 17, 2020
    Assignee: Altera Corporation
    Inventors: Dana How, Dinesh Patil, Arifur Rahman, Jeffrey Erik Schulz
  • Patent number: 10586875
    Abstract: A method for fabricating a semiconductor device including a gate-all-around based non-volatile memory device includes forming gate-all-around field effect transistor (GAA FET) channels, depositing tunnel dielectric material around the GAA FET channels to isolate the GAA FET channels, forming a floating gate, including depositing first gate material over the isolated GAA FET channels, and forming at least one control gate, including depositing second gate material over the isolated GAA FET channels.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Zheng Xu, Zhenxing Bi, Dexin Kong, Qianwen Chen
  • Patent number: 10585763
    Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include detecting a loss of communication with a given storage node among multiple storage nodes in a distributed computing system. Upon detecting the loss of communication, a log including updates to the data stored in the given storage node is recorded and, the recorded updates can be applied to the given storage node upon communication with the given storage node being reestablished. In some embodiments, the distributed storage system may be configured as a software defined storage system where the storage nodes can be implemented as either virtual machines or software containers. In additional embodiments, upon detecting the loss of communication, a redistribution of the mirrored data among remaining storage nodes is initiated upon detecting the loss of communication, and the redistribution is rolled back upon reestablishing the communication.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ram Elron, Michael Keller, Rivka M. Matosevich, Osnat Shasha
  • Patent number: 10586909
    Abstract: A cryogenic electronic package includes a circuitized substrate, an interposer, a superconducting multichip module (SMCM) and at least one superconducting semiconductor structure. The at least one superconducting semiconductor structure is disposed over and coupled to the SMCM, and the interposer is disposed between the SMCM and the substrate. The SMCM and the at least one superconducting semiconductor structure are electrically coupled to the substrate through the interposer. A cryogenic electronic assembly including a plurality of cryogenic electronic packages is also provided.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 10, 2020
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Rabindra N. Das, Eric A. Dauler
  • Patent number: 10586584
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
  • Patent number: 10573363
    Abstract: A method of reading information stored in a magnetic memory. In a magnetic memory comprising a magnetic tunnel junction including a first reference layer and a free layer, and a spin orbit active (SO) line adjacent to the first reference layer of the magnetic tunnel junction, first and second currents are passed through the SO line so as to achieve two different directions of a magnetic moment of the first reference layer. Two electrical characteristics of the magnetic tunnel junction are determined, the two electrical characteristics corresponding to the two different directions of the magnetic moment of the first reference layer. These two electrical characteristics are then compared to determine the value of the stored information.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Alexey Vasilyevich Khvalkovskiy, Vladimir Nikitin, Dmytro Apalkov
  • Patent number: 10565055
    Abstract: A semiconductor memory device may be disclosed. The semiconductor memory device may include a first memory cell array region and a second memory cell array region, each of which includes memory cells. The semiconductor memory device may include a column driving (Y-HOLE) region disposed between the first memory cell array region and the second memory cell array region. The Y-HOLE region may include an error correction code (ECC) block configured for performing error correction.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Duk Su Chun
  • Patent number: 10559335
    Abstract: In a method of training for a memory device, an initialization operation is performed on the memory device when the memory device is powered on. A training operation is performed on a plurality of operating frequencies of the memory device such that at least one of a plurality of operating parameters of the memory device is obtained as a configurable operating parameter for each of the plurality of operating frequencies. The configurable operating parameter for each of the plurality of operating frequencies is stored as training data. An optimized operating parameter for the memory device is used based on the training data, a current operation mode of the memory device, and a current operating frequency of the memory device.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Seob Kim, Jung-Il Lee
  • Patent number: 10557726
    Abstract: A magnetic field angle sensor is provided having two or more bridge structures of magnetoresistance elements, with each bridge structure configured to measure a projection of a magnetic field along a different axis such that an angle of direction of the magnetic field can be measured with greater accuracy. The angle sensor includes a first bridge structure configured to generate a first sinusoidal signal indicative of the magnetic field along a first axis and a first cosinusoidal signal indicative of the magnetic field along a second axis that is orthogonal with respect to the first axis and a second bridge structure configured to generate a second sinusoidal signal indicative of the magnetic field along a third axis and a second cosinusoidal signal indicative of the magnetic field along a fourth axis that is orthogonal with respect to the third axis, wherein an angle between the first axis and the third axis is a factor of 90°.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: February 11, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventor: Rémy Lassalle-Balier
  • Patent number: 10559363
    Abstract: The semiconductor memory device may include a memory cell array and a peripheral circuit. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a multi-page read operation on a selected memory block among the plurality of memory blocks. The peripheral circuit may select a first word line and a second word line, which are coupled to the selected memory block, and perform the multi-page read operation on the first and second word lines.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Jae Jung, Sung Won Bae, Min Kyu Lee
  • Patent number: 10559374
    Abstract: A memory chip architecture includes a plurality of test pads, a plurality of interface pads, a function block and an embedded test block. The function block is coupled to the interface pads. The embedded test block is coupled to the test pads. The embedded test block is connected to an access port physical layer (PHY) through the interface pads. The interface pads are disposed between the function block and the embedded test block. The embedded test block is arranged for generating at least one test pattern as a test signal, and outputting the test signal to the function block through the interface pads to test the function block.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: February 11, 2020
    Assignee: Piecemakers Technology, Inc.
    Inventors: Gyh-Bin Wang, Chun-Kai Wang
  • Patent number: 10552085
    Abstract: A host stores “context” metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: February 4, 2020
    Assignee: Radian Memory Systems, Inc.
    Inventors: Alan Chen, Craig Robertson, Robert Lercari, Andrey V. Kuzmin
  • Patent number: 10553303
    Abstract: A semiconductor device includes: a fuse set unit including a plurality of fuse sets, each fuse set including one or more address fuses and an enable fuse; a rupture control unit suitable for controlling the enable fuse of a selected fuse set to be programmed after the address fuses of the selected fuse set is programmed, during a program operation; a cell data verify unit suitable for repeatedly performing a verify and rupture operation on the selected fuse set during the program operation, determining whether read data from the selected fuse set is identical to target data corresponding to a rupture address through a final verify operation, and outputting fail information; and a fuse set control unit suitable for controlling the program operation to be performed on a different fuse set after the program operation on the selected fuse set is terminated, in response to the fail information.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Young-Kyu Noh
  • Patent number: 10552214
    Abstract: A media balancer obtains a master schedule to be used as a basis for generating target schedules, user input specifying one or more target stations for which the one or more target schedules are to be generated, and a duration delta indicating a maximum difference between runtimes of the replacement media items and the one or more scheduled media items. The media balancer selects a media scheduler to identify replacement media items to be substituted for one or more scheduled media items identified in the master schedule and transmits information associated with the duration delta to the media scheduler. The media balancer receives a list of identified replacement media items selected by the media scheduler, and generates the target schedules by replacing scheduled media items with particular replacement media items taken from the list of identified replacement media items.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: February 4, 2020
    Assignee: iHeartMedia Management Services, Inc.
    Inventors: Christopher John Voce, Jonathan David Earley, David C. Jellison, Jr., Darren Grant Davis, Jeffrey Lee Littlejohn
  • Patent number: 10553256
    Abstract: A semiconductor device may include a first column decoder arranged at a first side of a bank, wherein the first column decoder is enabled by a first column decoder select signal. The semiconductor device may include a second column decoder arranged at a second side of the bank, wherein the second column decoder is enabled by a second column decoder select signal; and wherein the bank is arranged between the first column decoder and the second column decoder. The semiconductor device may further include a column decoder selection circuit suitable for activating any one of the first and second column decoder select signals based on a row address.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Yoon Ka
  • Patent number: 10545878
    Abstract: Provided is a search memory capable of suppressing an increase in the area of a chip and an increase in the amount of current consumption. The search memory includes an input control section, N search units, and N first selectors. The input control section receives N (N: two or more) search data that are parallelly inputted. The N first selectors are respectively disposed in association with the N search units to select two search data from the N search data. The search units each include multiple search blocks and M second selectors. The M second selectors select one of two search data selected by the first selectors. For at least one of the N search units, allocation is performed so that two types out of N types of entry data respectively associated with the N search data are respectively stored in the search blocks.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: January 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideto Matsuoka
  • Patent number: 10546649
    Abstract: In one example in accordance with the present disclosure, a method includes mapping, using post-package repair, an address associated with a first memory row of a computing device to a spare memory row of the computing device, wherein the spare memory row has a memory failure pattern, and reading data from the spare memory row.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: January 28, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Eric L Pope, Scott P Faasse
  • Patent number: 10546864
    Abstract: An integrated circuit structure includes a Static Random Access Memory (SRAM) cell, which includes a read port and a write port. The write port includes a first pull-up Metal-Oxide Semiconductor (MOS) device and a second pull-up MOS device, and a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. The integrated circuit structure further includes a first metal layer, with a bit-line, a CVdd line, and a first CVss line in the first metal layer, a second metal layer over the first metal layer, and a third metal layer over the second metal layer. A write word-line is in the second metal layer. A read word-line is in the third metal layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10541008
    Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit line, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christopher Kawamura, Tae H. Kim
  • Patent number: 10535418
    Abstract: A memory device including a memory cell region having a normal cell array and a redundant cell array, a fuse unit having a plurality of fuse sets corresponding to the redundant cell array and which is used for programming an address of a repair target memory cell of the normal cell array and a deciding unit which determines fuse sets that are used in a first operation mode according to a control signal.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: January 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Jung-Taek You