Bad Bit Patents (Class 365/200)
  • Patent number: 11032507
    Abstract: Techniques to set a frame rate and associated device manufacturing are disclosed. In one example, an imaging device includes a detector array configured to detect electromagnetic radiation associated with a scene and provide image data frames according to a first frame rate. The imaging device further includes a readout circuit configured to provide the image data frames according to a frame rate for the readout circuit. The imaging device further includes a fuse configured to set the frame rate for the readout circuit. Related methods and systems are also provided.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: June 8, 2021
    Assignee: FLIR Commercial Systems, Inc.
    Inventors: Robert F. Cannata, Brian B. Simolon, Nicholas Högasten, Christopher Chan, Eric A. Kurth
  • Patent number: 11031083
    Abstract: Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Gary L. Howe, Scott E. Smith
  • Patent number: 11023173
    Abstract: An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Ming-Bo Liu
  • Patent number: 11023132
    Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tetsuya Sunata, Daisuke Iwai, Kenichiro Yoshii
  • Patent number: 11024402
    Abstract: A memory system may include: an error correction code (ECC) generation circuit suitable for generating an M-bit error correction code using N-bit data, where N and M are positive integers; a memory core suitable for storing the N-bit data and the M-bit error correction code; and an ECC circuit suitable for correcting an error of the N-bit data read from the memory core, using the M-bit error correction code read from the memory core, wherein the ECC generation circuit generates the M-bit error correction code using an M×(N+M) check matrix, wherein one column vector among M column vectors corresponding to the M-bit error correction code in the M×(N+M) check matrix has an odd weight, and the other M column vectors have even weights.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: June 1, 2021
    Assignee: SK hynix Inc.
    Inventor: Hoiju Chung
  • Patent number: 11024364
    Abstract: There are provided a sense amplifier for sensing a multilevel cell and a memory device including the same. The sense amplifier is configured to sense the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data a cell voltage stored in a memory cell as the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data. The sense amplifier senses the MSB of the 2-bit data in a state in which a bit line is electrically disconnected from a holding bit line of the sense amplifier and senses the LSB of the 2-bit data in a state in which the cell bit line is electrically connected to the holding bit line. The sense amplifier is configured to equalize a pair of bit lines of the sense amplifier before sensing the MSB and the LSB of the 2-bit data. The sense amplifier is configured to restore to the memory cell the cell voltage corresponding to the sensed MSB and LSB of the 2-bit data.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 1, 2021
    Inventors: Young-Hun Seo, Dong-Il Lee, Hye-Jung Kwon
  • Patent number: 11024633
    Abstract: A device is disclosed that includes a memory bit cell coupled to a bit line, a word line, a pair of metal islands and a pair of connection metal lines. The word line is electrically coupled to the memory bit cell and is elongated in a first direction. The pair of metal islands are disposed at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are elongated in a second direction, and are configured to electrically couple the pair of metal islands to the memory bit cell, respectively. The pair of connection metal lines are separated from the bit line in a layout view. A method of fabricating the device is also provided.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hidehiro Fujiwara, Wei-Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 11015547
    Abstract: Apparatuses and methods for storing redundancy repair information for memories are disclosed. An example apparatus includes a fuse array, a repair plane, and a decode logic and control circuit. The fuse array stores repair information that includes repair commands and load repair addresses. The load repair addresses include a respective repair address. The repair plane includes a block of memory and repair logic. The block of memory includes a plurality of redundant memory and the repair logic includes a plurality of repair blocks. Each repair block is associated with a respective one of the plurality of redundant memory and each repair block of the plurality of repair blocks stores a repair address. The decode logic and control circuit reads the repair information and decodes the repair commands, and loads repair addresses into the plurality of repair blocks based at least in part on the decoded repair commands.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Christopher Morzano
  • Patent number: 11016589
    Abstract: Methods and devices for communicating or interacting by a pen or a stylus with a digitizer are disclosed. An example method describes determining whether the device is to transmit a first information to the digitizer via the electrode or receive a second information from the digitizer via the electrode. An example device for use with the method includes a transmitter circuit, a receiver circuit, and an electrode. The method further includes isolating the electrode from the transmitter circuit in response to determining that the device is to receive the second information from the digitizer via the electrode.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 25, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ori Laslo, Vadim Mishalov, Ron Kaplan
  • Patent number: 11010325
    Abstract: An adapter includes a first coupling component and a second coupling component to establish bidirectional communications between two processing devices by passing data signals through a memory card slot on one of the devices. The adapter includes a first coupling interface configured to couple with the memory card slot on a first one of the two processing devices and further includes a second coupling interface configured to couple with a second processing device. The second coupling interface is of a different form factor than the first coupling interface.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 18, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Adam Nelson Swett, Vlad Radu Calugaru
  • Patent number: 11009852
    Abstract: A numerical controller which uses a simulation screen displayed on a touch panel so as to edit operation data of an industrial machine includes: a touch operation reception unit that receives a touch operation by an operator on the simulation screen; an operation identifying unit that identifies an operation target and an operation type on the simulation screen by the touch operation received; a setting screen data extraction unit that references the editing data storage unit for associating the operation target and the operation type and setting screen data including an editing item so as to store them so as to extract the setting screen data corresponding to the operation target and the operation type identified; an editing processing unit that edits the setting screen data extracted; and a setting screen output unit that outputs, to the touch panel 40, the setting screen data after being edited.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 18, 2021
    Assignee: FANUC CORPORATION
    Inventor: Zhaojia Liu
  • Patent number: 11005518
    Abstract: A transceiver circuit may include: a first NMOS transistor suitable for puffing up a transmission line in response to a TX signal in a TX mode and for being turned on or off according to a voltage level of the transmission line in an RX mode; and a first PMOS transistor suitable for pulling down the transmission line in response to the TX signal in the TX mode and for being turned on or off according to the voltage level of the transmission line in the RX mode.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: May 11, 2021
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Deog-Kyoon Jeong, Han-Gon Ko
  • Patent number: 10997084
    Abstract: A memory system and method for storing data in one or more storage chips is disclosed. The memory system includes one or more storage dies included in each storage chip and a controller. Each of the plurality of storage dies further comprises one or more media replacement unit (MRU) groups. The controller includes a translation module, the translation module further comprising: a chip select table (CST) configured to identify one or more valid storage chips during translation for performing a read/write operation, and a media repair table (MRT) corresponding to each of storage chips, each MRT configured to identify one or more storage dies during translation for performing a read/write operation.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robert Edward Galbraith, Damir Anthony Jamsek, Andrew Kenneth Martin, Daniel Frank Moertl, Mussie T. Negussie, Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis, Milos Stanisavljevic
  • Patent number: 10998077
    Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Rohit Bhasin, Shishir Kumar, Tanmoy Roy, Deepak Kumar Bihani
  • Patent number: 10997020
    Abstract: A memory device, a memory system, and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells and a write command determination unit (WCDU) that determines whether a write command input to the memory device is (to be) accompanied a masking signal. The WCDU produces a first control signal if the input write command is (to be) accompanied by a masking signal. A data masking unit combines a portion of read data read from the memory cell array with a corresponding portion of input write data corresponding to the write command and generates modulation data in response to the first control signal. An error correction code (ECC) engine generates parity of the modulation data.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong-Wook Park
  • Patent number: 10998082
    Abstract: A memory system includes a memory device and a controller. The memory device includes a memory cell array including a normal memory cell area and a redundancy memory cell area, the redundancy memory cell area having a replacement memory cell region and a reserved memory cell region; a register suitable for generating a first signal indicating existence of the reserved memory cell region; and a fuse unit suitable for activating the reserved memory cell region based on the first signal. The controller assigns an address for accessing a reserved memory cell of the reserved memory cell region based on the first signal. A replacement memory cell in the replacement memory cell region replaces a failed memory cell in the normal memory cell region, and the reserved memory cell in the reserved memory cell region remains without replacing any failed memory cell in the normal memory cell region.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyung-Sik Won, Hyungsup Kim
  • Patent number: 10991426
    Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Tien-Yen Wang
  • Patent number: 10987572
    Abstract: A first sensor detects a movement of a first apparatus attached to a lower body of a user, and a second sensor detects a movement of a second apparatus attached to an upper body of the user or held by a hand of the user. Then, a virtual object is caused to continue a first action in a virtual space while received outputs from the first sensor and the second sensor both satisfy a condition.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 27, 2021
    Assignee: Nintendo Co., Ltd.
    Inventors: Shinji Kitahara, Atsushi Yamazaki
  • Patent number: 10992458
    Abstract: One example method includes creating a backup of data, creating metadata associated with the backup, hashing the backup to create a backup hash, obtaining a key from a blockchain, generating an aggregate hash of a combination that includes the key and the backup hash, and transmitting the aggregate hash to a blockchain network. Because the aggregate hash is not modifiable when stored in a blockchain, an immutable record exists that establishes when a particular backup was created.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: April 27, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Assaf Natanzon, David Zlotnick
  • Patent number: 10991413
    Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dale H. Hiscock, Michael Kaminski, Joshua E. Alzheimer, John H. Gentry
  • Patent number: 10990449
    Abstract: Application relationships may be categorized and managed at a service layer, such as creating application relationship, updating application relationship, retrieving application relationship, deleting application relationship, or discovering application relationship. Services may be based on application relationship awareness.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: April 27, 2021
    Assignee: Convida Wireless, LLC
    Inventors: Chonggang Wang, Qing Li, Hongkun Li, Zhuo Chen, Tao Han, Paul L. Russell, Jr.
  • Patent number: 10990317
    Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells at intersections of memory rows and memory columns. The memory device further includes sense amplifiers corresponding to the memory rows. When the memory device powers on, the memory device writes one or more memory cells of the plurality of memory cells to a random data state before executing an access command received from a user, a memory controller, or a host device of the memory device. In some embodiments, to write the one or more memory cells, the memory device fires multiple memory rows at the same time without powering corresponding sense amplifiers such that data stored on memory cells of the multiple memory rows is overwritten and corrupted.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anthony D. Veches, Debra M. Bell, James S. Rehmeyer, Robert Bunnell, Nathaniel J. Meier
  • Patent number: 10984845
    Abstract: In an embodiment, a method for protecting an electronic circuit includes: detecting a malfunction of the electronic circuit; executing a plurality of waves of countermeasures without interrupting an operation of the electronic circuit; and triggering a reset of the electronic circuit after executing the plurality of waves of countermeasures. An interval between two waves of countermeasures of the plurality of waves of countermeasures is variable.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: April 20, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SAS
    Inventors: Diana Moisuc, Christophe Laurencin
  • Patent number: 10984868
    Abstract: Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Toru Ishikawa, Minari Arai
  • Patent number: 10984886
    Abstract: A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array including a plurality of fuse banks. A fuse bank of the plurality of fuse banks includes a fuse circuit, which includes a fuse latch having first input circuitry. The fuse latch is implemented to store a first bit of a first memory address received at the first input circuitry. The fuse circuit also includes a matching circuit coupled to the first input circuitry. The matching circuit is implemented to receive a first bit of a second memory address at the first input circuitry and to output, at output circuitry, a comparison result based at least in part on the first bit of the first memory address and the first bit of the second memory address.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet Ayyapureddi
  • Patent number: 10984843
    Abstract: A memory cell arrangement for Random Access Memory (RAM) including one or more RAM cell groups. The RAM cell groups having two or more local bit-lines sharing a Global Bit-Line (GBL), a pre-charging circuit connected to the GBL, a multiplexer connected to multiple GBLs and configured to shift an output of a first GBL from a first bit to a second bit at least in part according to a value of a fuse bit register associated with a second GBL, and at least one pre-charge enabling circuit controlled by a combination of a pre-charge input value applied to all GBLs of the memory cell arrangement and a pre-charge enable signal for the GBL.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Martin Bernhard Schmidt, Harry Barowski, Simon Brandl, Wolfgang Penth
  • Patent number: 10978155
    Abstract: Apparatus and methods are disclosed, including an apparatus having first and second units of vertically arranged strings of memory cells, each unit including multiple tiers of a semiconductor material, including multiple tiers of memory cells, each tier of memory cells including an access line of at least one memory cell. The access line of a first tier of the first unit can be selectively coupled to a first drive transistor through a first decoder transistor, the access line of a first tier of the second unit can be selectively coupled to the first drive transistor through a second decoder transistor, and the access line of the first tier of the first unit can be selectively coupled to the access line of the first tier of the second unit through the first and second decoder transistors.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 10976944
    Abstract: A method for performing configuration management, an associated data storage device and the controller thereof are provided. The method may include: reading a read-only memory (ROM) code from a ROM to execute the ROM code; during executing the ROM code, detecting a first set of states of a general-purpose input/output (GPIO) circuit to perform a first portion of system configuration settings of the ROM code according to the first set of states; during executing the ROM code, detecting a second set of states of an electronic fuse (eFuse) circuit to perform a second portion of system configuration settings of the ROM code according to the second set of states; and executing at least one program code to make the data storage device be ready for being accessed by a host device.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: April 13, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Chien-Chung Chung, Da-Ru Yu, Wei-Chia Su
  • Patent number: 10978141
    Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry, two or more memory instances coupled to the first and second word-line decoder circuitry; and a control block circuitry coupled to the first and second word-line decoder circuitry and the two or more memory instances. Also, a pin bus enabled in the control block circuitry may be configured to at least partially control selection of one or more of the two or more memory instances.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 13, 2021
    Assignee: Arm Limited
    Inventors: Yew Keong Chong, Sriram Thyagarajan, Andy Wangkun Chen, Vivek Asthana, Munish Kumar
  • Patent number: 10957395
    Abstract: A nonvolatile memory device includes a memory cell array including a main memory area and a dummy memory area, a row decoder, a bit line selection circuit, a data input/output circuit, a control circuit, and a voltage generator. The bit line selection circuit is configured to select a first main bit line during a program time and is configured to select a dummy bit line during a column address switch time. During the column address switch time, a second main bit line is selected. The voltage generator is configured to output, to the row decoder, a source line voltage to be applied to a selected source line during the program time and during the column address switch time, wherein the source line voltage is maintained at a voltage level during the program time and during the column address switch time.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 23, 2021
    Inventors: Hoyoung Shin, Ji-Sung Kim, Hyun-Jin Shin
  • Patent number: 10957413
    Abstract: Systems and methods related to memory devices that may perform error check and correct (ECC) functionality. The systems and methods may employ ECC logic that may be shared between two or more banks. The ECC logic may be used to perform memory operations such as read, write, and masked-write operations, and may increase reliability of storage data.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Susumu Takahashi, Hiroki Fujisawa
  • Patent number: 10942799
    Abstract: Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Ali Khakifirooz, Pranav Kalavade, Ravi H. Motwani, Chang Wan Ha
  • Patent number: 10944829
    Abstract: Aspects of the subject disclosure may include, for example, embodiments a service multiplexer identifying a service associated with each of a group of sensors resulting in a group of services. Further embodiments include the service multiplexer creating a service portfolio according to the group of services. Additional embodiments include service multiplexer communicatively coupling to nodes over a 5th Generation (5G) network according to the service portfolio. The 5G network includes a control plane and user plane. Also, embodiments include service multiplexer continuously connecting to the control plane. Further embodiments include receiving data from the sensors. Additional embodiments include service multiplexer determining that the received data is associated with the service portfolio. Also, embodiments include service multiplexer identifying one or more of the nodes according to the service portfolio and sending the received data to the one or more of the nodes over the user plane.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: March 9, 2021
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Venson Shaw, Sangar Dowlatkhah
  • Patent number: 10936453
    Abstract: A system utilizing elastic spares includes nodes and devices to store one or more data objects having information. The data object includes data object units each assigned to a storage location on a different node than the other units. The data object includes one or more spare units to store reconstructed information of a failed unit. When one of the data objects has a failed unit and no spare units available to store reconstructed information, a controller of the system assigns an elastic spare unit to an available storage location of one of the nodes. Reconstructed information of the failed unit is stored in the elastic spare unit.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: March 2, 2021
    Assignee: Seagate Technology LLC
    Inventors: Nathaniel Rutman, Nikita Danilov
  • Patent number: 10922019
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data from a host system, and writing the data into a plurality of first physical programming units; performing a multi-frame encoding according to the plurality of data to generate encoded data, and writing the encoded data into a second physical programming unit; and writing a plurality of first concatenated information related to the encoded data into the plurality of first programming units, respectively.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: February 16, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chia-Hung Chien, Hsiao-Hsuan Yen
  • Patent number: 10922136
    Abstract: A subscription server generates, at a clock generation module, a clock template including a plurality of slots, each slot associated with at least one content type, and wherein the clock template includes information indicating timing relationships of the plurality of slots relative to one another. The subscription server determines that a media log is to be generated from the clock template for one or more subscribers, and obtains, from a subscription verification module implemented by the processor and associated memory, trust parameters associated with the one or more subscribers. A log generation module implemented by the processor and associated memory, generates a media log including at least one slot assigned a restriction level determined based on the trust parameters. The media log, including information indicating the restriction level, is transmitted to at least one of the one or more subscribers.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: February 16, 2021
    Assignee: iHeartMedia Management Services, Inc.
    Inventors: Christopher John Voce, Jonathan David Earley, David C. Jellison, Jr., Darren Grant Davis, Jeffrey Lee Littlejohn
  • Patent number: 10916276
    Abstract: According to one embodiment, a nonvolatile memory includes a memory cell array including a first storage region and a second storage region, an input/output circuit configured to communicate with a memory controller, and a control circuit. The control circuit is configured to, upon receiving a first command from the memory controller, execute a first training operation related to the input/output circuit, and upon receiving a second command from the memory controller, store a first result of the first training operation in the first storage region.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: February 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kensuke Yamamoto, Kosuke Yanagidaira, Fumiya Watanabe, Shouichi Ozaki
  • Patent number: 10909011
    Abstract: Techniques are provided for storing a row address of a defective row of memory cells to a bank of non-volatile storage elements (e.g., fuses or anti-fuses). After a memory device has been packaged, one or more rows of memory cells may become defective. In order to repair (e.g., replace) the rows, a post-package repair (PPR) operation may occur to replace the defective row with a redundant row of the memory array. To replace the defective row with a redundant row, an address of the defective row may be stored (e.g., mapped) to an available bank of non-volatile storage elements that is associated with a redundant row. Based on the bank of non-volatile storage elements the address of the defective row, subsequent access operations may utilize the redundant row and not the defective row.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Alan J. Wilson
  • Patent number: 10910081
    Abstract: Filter information associated with a test to be performed with one or more memory components is determined. A set of memory components matching the filter information may be reserved for use in the testing. Test execution information defining a set of test processes of the test is determined. A connection with a first test process may be established and used to receive feedback information associated with execution of the test process. Based on the feedback information, a failure of the first test process may be identified.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: February 2, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Aswin Thiruvengadam, Sivagnanam Parthasarathy, Daniel Scobee, Frederick Jensen
  • Patent number: 10909059
    Abstract: A transmission terminal includes at least one processor configured to transmit a terminal information request to request the number of transmission terminals under transmission to a transmission management apparatus connected via a network; and display image data received from one or more of the transmission terminals under transmission on a display device, and display the number of the transmission terminals under transmission received from the transmission management apparatus in response to the terminal information request on the display device.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: February 2, 2021
    Assignee: Ricoh Company, Ltd.
    Inventor: Yoshinaga Kato
  • Patent number: 10902811
    Abstract: The present disclosure provides a shift register, a GOA circuit, a display device, and a driving method. A shift register is provided which comprises: at least one input sub-circuit for charging a pull-up node; at least one output sub-circuit for outputting a respective clock signal; first reset sub-circuit(s) for pulling the potential of the respective signal output terminal down to a reference potential; a first noise reduction sub-circuit for performing noise reduction on the pull-up node through a signal input from the reference potential terminal; a second noise reduction sub-circuit for performing noise reduction on the pull-down node through a signal input from the reference potential terminal; and a second reset sub-circuit for controlling the potential of the pull-down node under control of a signal input from the reset clock signal input terminal.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: January 26, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventor: Jiguo Wang
  • Patent number: 10902898
    Abstract: A semiconductor memory device includes a memory cell array, a buffer unit, control logic, and a decoding circuit. The memory cell array includes a plurality of memory cells. The buffer coupled to the memory cell array, and includes a first memory area, a second memory area, and a conversion memory area. The control logic outputs a mode control signal representing an operating mode of the buffer. The decoding circuit controls the operating mode of the buffer such that the conversion memory area operates as any one of a main memory area and a repair memory area, based on the mode control signal.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: January 26, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang Hwan Kim
  • Patent number: 10901634
    Abstract: A storage system may include a plurality of logical storage units that each include a plurality of storage devices. One or more logical unit numbers may be stored across one or more of the plurality of logical storage units, and the logical unit numbers may be accessible by one or more host devices. A logical storage unit may include a plurality of storage devices. Upon detection of failure of a storage device of a logical storage unit, data of the logical storage unit is drained to one or more fault tolerant logical storage unit. The logical storage unit with the defective device is converted to a fault-tolerant logical storage unit using the available and non-defective devices. Data is rebalanced across the fault-tolerant logical storage units.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 26, 2021
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Chetan Bendakaluru Lingarajappa
  • Patent number: 10891185
    Abstract: Example implementations relate to tracking memory unit errors on a memory device. In example implementations, a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: January 12, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Lidia Warnes, Melvin K. Benedict, Andrew C. Walton
  • Patent number: 10891988
    Abstract: A memory module includes a circuit board, a plurality of memory devices, and a power management integrated circuit (PMIC). The circuit board includes first connectors, a second connector, and a third connector connected to an external device. The plurality of memory devices are mounted on the circuit board, and connected to the first connectors. The PMIC receives a first voltage through the second connector, generates a second voltage using the first voltage, and provides the second voltage to the plurality of memory devices The PMIC adjusts the second voltage based on a signal received through the third connector such that a voltage difference of the first voltage and the second voltage is reduced in a training mode of the memory module.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: January 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwan-Wook Park, Yong-Jin Kim, Jin-Seong Yun, Kyu-Dong Lee
  • Patent number: 10884861
    Abstract: According to one embodiment, a computer-implemented method includes determining a write speed for each of a plurality of systems in a cluster, determining a ratio of the write speeds for each of the plurality of systems in the cluster, and updating parity assignments to each of the plurality of systems in the cluster, based on the ratio of the write speeds.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventor: Steven R. Hetzler
  • Patent number: 10878934
    Abstract: A memory device and an electronic device are provided. Different embodiments of local redundancy decoder circuits that can be used in the memory device and the electronic device are disclosed.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: December 29, 2020
    Inventors: Chien-Yu Huang, Chia-En Huang, Cheng Hung Lee, Hau-Tai Shieh
  • Patent number: 10878881
    Abstract: The memory apparatus includes a plurality of memory chips and a plurality of temperature sensors. The memory chips are coupled to each other. The temperature sensors are respectively disposed on the memory chips. One of the memory chips is configured to be a master memory chip, and a first temperature sensor of the master memory chip is enabled to sense an ambient temperature. The master memory chip generates a refresh rate control signal according to the ambient temperature and controls refresh rates of all of the memory chips.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 29, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Wei Shen
  • Patent number: 10872678
    Abstract: Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Richard E. Fackenthal, Jahanshir Javanifard, Duane R. Mills
  • Patent number: 10868526
    Abstract: Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 15, 2020
    Assignee: NXP USA, INC.
    Inventors: Mikhail Yurievich Semenov, Victor Mikhailovich Mikhailov, Sergei Victorovich Somov, Denis Borisovich Malashevich, Viacheslav Sergeyevich Kalashnikov