Bad Bit Patents (Class 365/200)
  • Patent number: 10294563
    Abstract: Atomic layer deposition (ALD) type processes for producing metal containing thin films comprise feeding into a reaction space vapor phase pulses of metal containing cyclopentadienyl precursors as a metal source material. In preferred embodiments the metal containing cyclopentadienyl reactant comprises a metal atom that is not directly bonded to an oxygen or halide atom. In other embodiments the metal atom is bonded to a cyclopentadienyl compound and separately bonded to at least one ligand via a nitrogen atom. In still other embodiments the metal containing cyclopentadienyl compound comprises a nitrogen-bridged ligand.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: May 21, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Sean T. Barry, Yamile A. M. Wasslen, Antti H. Rahtu
  • Patent number: 10297340
    Abstract: Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Joe M. Jeddeloh, Paul A. LaBerge
  • Patent number: 10290353
    Abstract: NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a processor and a memory device comprising NAND flash memory. The processor is configured to detect an error condition associated with a first page of the NAND flash memory, and determine whether the error condition is associated with a read disturbance or with a retention error. The processor is configured to initiate, if the error condition is associated with the read disturbance, a refresh operation with respect to the page to write data stored at the first page to a second page of the NAND flash memory, and initiate, if the error condition is associated with the retention error, a reprogramming operation with respect to the page to rewrite the data stored at the first page to the first page of the NAND flash memory.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: May 14, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Seung-Hwan Song, Viacheslav Anatolyevich Dubeyko, Zvonimir Z. Bandic
  • Patent number: 10290364
    Abstract: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: May 14, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shuo-Nan Hung, Chi Lo, Chun-Hsiung Hung
  • Patent number: 10290641
    Abstract: A semiconductor device has a 6T SRAM cell formed on a substrate. The SRAM cell includes a first and a second PMOS transistors formed over an N-well line in a substrate. A first and a second NMOS transistors are formed over a first P-well line in the substrate at a first side of the N-well line. A third and a fourth NMOS transistors are formed over a second P-well line in the substrate at a second side of the N-well line. A first gate line connects gates of the first PMOS transistor and the first NMOS transistor. A second gate line connects a gate of the second NMOS transistor. A third gate line connects gates of the second PMOS transistor and the third NMOS transistor. A fourth gate line connects a gate of the fourth NMOS transistor. The first gate line and the third gate line are in L-shape.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: May 14, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Wan-Xun He, Su Xing
  • Patent number: 10288677
    Abstract: A semiconductor device may be provided. The semiconductor device may include a latch comparison circuit configured for generating a latched address by latching a pattern signal inputted through an address, and generate a comparison signal by comparing a pattern signal inputted through the address and the latched address. The semiconductor device may include a failure flag generation circuit configured for generating a failure flag signal based on the comparison signal.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: May 14, 2019
    Assignee: SK hynix Inc.
    Inventors: Tae Kyun Shin, Young Bo Shim
  • Patent number: 10283209
    Abstract: A method for detecting problem cells of a SATA SSD and a SATA SSD having self-detecting function looking for problem cells are disclosed. The method includes the steps of: providing a detecting program used to detect aged and died cells in a SATA SSD; writing the detecting program to a MCU (Micro Control Unit) in the SATA SSD; pulling high electric potential of a communicating pin of a SATA connector of the SATA SSD to initiate the detecting program; collecting location data of aged and died cells in the SATA SSD by the detecting program; and storing the location data in a storage area in the SSD. The present invention utilizes the DAS/DSS pin as a channel to initiate detecting program. It has advantages of using current interface of SSD, no effort on taking apart hardware and automatically running the detecting program without human control.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: May 7, 2019
    Assignee: Storart Technology (Shenzhen) Co. Ltd
    Inventor: Chun Hsien Lin
  • Patent number: 10275228
    Abstract: A method is provided for relaxing register constraints in a computer program. The method includes identifying, by a processor enabled compiler, unrequired register constraints imposed by a user on the computer program. The unrequired register constraints are unrequired for a proper operation of the computer program. The method further includes automatically relaxing, by the processor enabled compiler, the identified unrequired register constraints to optimize register allocation for the computer program.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Toshio Suganuma
  • Patent number: 10277432
    Abstract: The present invention provides a data processing method and device. A data processing device receives a first data stream, where the first data stream includes a first data unit; obtains a boundary of the first data unit; obtains a first skew according to a first data amount and the boundary of the first data unit; and adjusts the first data stream according to the first skew, so that a difference between the boundary of the first data unit and a boundary of the first data amount is a length of an integral quantity of first data units, so that a relatively small amount of data is needed in such an adjustment, that is, one data stream is adjusted, and an adjusted data stream can meet a basic condition for multiplexing, which reduces operation complexity and costs and is beneficial to deploy and implement bit width conversion.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: April 30, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Wenbin Yang, Xinyuan Wang, Tongtong Wang
  • Patent number: 10269422
    Abstract: A storage system includes: a control processor unit, configured to: initiate a read of a raw data page, having correctable errors, calculate a raw bit error rate (RBER) (EQ1) by correcting the correctable errors to become corrected data and comparing raw data with the corrected data, and calculate a correction model characterization based on the RBER (EQ1); and a non-volatile storage array, coupled to the control processor unit, configured to store a processed data page in a physical block with the raw data page; and wherein the control processor unit is further configured to apply the correction model characterization to the raw data page in the physical block.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 23, 2019
    Assignee: CNEX LABS, Inc.
    Inventor: Xiaojie Zhang
  • Patent number: 10269444
    Abstract: Techniques and memory devices are provided in which bit line short circuits are detected and groups of bit lines are masked off. A process tests groups of bit lines which are connected to a sense circuit. A masking latch is provided to store test results for each group of bit lines. Once the testing of a group is completed, the test result is communicated to a controller. Moreover, the same masking latch can store and communicate test results for multiple groups of bit lines which are connected to a sense circuit. In a user mode, a masking latch stores masking data for each group of bit lines. In response to a power on reset, the masking data is loaded into the masking latches and remains there over multiple write and read operation, until a next power on reset occurs.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: April 23, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Anurag Nigam, Yukeun Sim, Jingwen Ouyang, Yingchang Chen
  • Patent number: 10261856
    Abstract: An aspect includes providing communication links from a memory controller to contents of a plurality of bit locations in a plurality of memory devices. A failing bit location in the plurality of bit locations is detected by the memory controller. A replacement bit location for the failing bit location is selected and a replacement communication link to the replacement bit location is provided by the memory controller. A request to access contents of the failing bit location received after the selecting and providing the replacement communication link is performed by accessing contents of the replacement bit location via the replacement communication link.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen P. Glancy, Frank LaPietra, Kevin M. Mcilvain, Jeremy R Neaton, Richard D. Wheeler
  • Patent number: 10256400
    Abstract: A semiconductor device comprises a semiconductor substrate; a multilevel wiring layer structure on the semiconductor substrate; and a variable resistance element in the multilevel wiring layer structure, wherein the variable resistance element comprises a variable resistance element film whose resistance changes between a top electrode and a bottom electrode, wherein the multilevel wiring layer structure comprises at least a wiring electrically connected to the bottom electrode and a plug electrically connected to the top electrode, and wherein the wiring also serves as the bottom electrode.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: April 9, 2019
    Assignee: NEC CORPORATION
    Inventors: Munehiro Tada, Toshitsugu Sakamoto, Hiromitsu Hada, Naoki Banno
  • Patent number: 10255987
    Abstract: The present disclosure relates to a structure which includes a current-mirror control node which is configured to adjust a current margin and provide the adjusted current margin to at least one one-time programmable memory (OTPM) cell.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: April 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: John A. Fifield
  • Patent number: 10249597
    Abstract: Systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems are described. A stacked semiconductor package includes a processor functional silicon die at a first layer of the stacked semiconductor package; one or more memory dies forming a corresponding one or more memory layers of the stacked semiconductor package; a plurality of Through Silicon Vias (TSV s) formed through the one or more memory dies; a plurality of physical memory interfaces electrically interfacing the one or more memory dies to the processor functional silicon die at the first layer through the memory layers via the plurality of TSVs; and a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the processor functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Kalyan C. Kolluru, Pete D. Vogt, Christopher J. Nelson, Amande B. Trang, Uddalak Bhattacharya
  • Patent number: 10249680
    Abstract: A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack—including a memory element, a selector, and a spacer—disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: April 2, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mac D. Apodaca, Kurt Allan Rubin
  • Patent number: 10241689
    Abstract: Techniques for treating surfaces of a multi-platter disk as independent units are described herein. Each surface of a plurality of surfaces of a multi-platter disk is identified and a set of storage layout data describing the storage format of the surface is received. A logical address is calculated based on the surface layout data and at least a portion of the storage layout data is stored on the surface. The logical address of the surface is then provided for use by other services.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: March 26, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: James Christopher Sorenson, III
  • Patent number: 10241207
    Abstract: A LIDAR system for use in a vehicle may include at least one processor configured to control at least one light source in a manner enabling light flux of at least one light source to vary over scans of a field of view. The processor may also be configured to control at least one light deflector to deflect light from the at least one light source in order to scan the field of view. The processor may also be configured to receive input indicative of a current driving environment of the vehicle, and based on the current driving environment, coordinate the control of the at least one light source with the control of the at least one light deflector to dynamically adjust an instantaneous detection distance by varying an amount of light projected and a spatial light distribution of light across the scan of the field of view.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: March 26, 2019
    Assignee: Innoviz Technologies Ltd.
    Inventors: Oren Rosenzweig, Amit Steinberg, Guy Zohar, Nir Osiroff, Omer David Keilaf, Oren Buskila
  • Patent number: 10235258
    Abstract: The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: March 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-pil Son, Chul-woo Park, Su-a Kim
  • Patent number: 10235397
    Abstract: Systems and methods for managing content in a flash memory. Data structures such as trees and graphs are implemented in a flash memory. Nodes or field nodes such as pointers or invalidation bits are updated using an overwrite operation where possible or by invalidating certain fields and temporarily storing changes in an in-memory table.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 19, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Philip N. Shilane, Grant R. Wallace
  • Patent number: 10224114
    Abstract: A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.
    Type: Grant
    Filed: May 20, 2017
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-min Ryu, Hak-soo Yu, Reum Oh, Seong-young Seo, Soo-jung Rho
  • Patent number: 10217525
    Abstract: Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. The control circuit, in a second repair mode, receives second repair address information and provides the second repair address information to the storage latch circuit and disables storing the second address information into the non-volatile storage element.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Imc.
    Inventor: Hideyuki Yoko
  • Patent number: 10210949
    Abstract: A method of monitoring symptoms of a person includes repeating, over a period of time, the steps of: selecting, by the person, one or more symbolic representations corresponding to one or more symptoms from a predefined set of symbolic representations presented to the person; and electronically recording data regarding the one or more symbolic representations selected by the person such that the data is electronically accessible later for generating a history of the symptoms of the person over the period of time. The data is transferred over virtual networks using virtual dispersive routing and stored in dispersive storage area networks (SANs). The data is classified as trusted, corrupted, invalid or uncertain, and/or as trusted, ambiguous and inadequate.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: February 19, 2019
    Assignee: DISPERSIVE NETWORKS, INC.
    Inventors: Robert W. Twitchell, Jr., Thomas Andrew Dawson
  • Patent number: 10204037
    Abstract: An operation method of a memory controller may include: performing a preset number of write operations on a redundancy region of a memory device, reading data of the redundancy region of the memory device, and detecting error bits which occur in the data, and generating an identifier corresponding to the memory device based on the detected error bits.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: February 12, 2019
    Assignee: SK Hynix Inc.
    Inventors: Ja-Hyun Koo, Jung-Hyun Kwon
  • Patent number: 10198314
    Abstract: A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: February 5, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Suresh Rajan, Brent Haukness, Scott C. Best, Wayne F. Ellis
  • Patent number: 10199361
    Abstract: A stacked electronic structure comprises: a substrate and a magnetic device, wherein a plurality of electronic devices and a plurality of conductive pillars are disposed on and electrically connected to the substrate, wherein a molding body encapsulates the plurality of electronic devices, wherein the magnetic device is disposed over the top surface of the molding body and the plurality of conductive pillars, wherein a first terminal of the magnetic device is disposed over and electrically connected to a first conductive pillar and a second terminal of the magnetic device is disposed over and electrically connected to a second conductive pillar, without using any substrate.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 5, 2019
    Assignee: CYNTEC CO., LTD.
    Inventors: Chi-Feng Huang, Bau-Ru Lu, Da-Jung Chen
  • Patent number: 10199380
    Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: February 5, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Theodore W. Houston, Thomas J. Aton, Scott W. Jessen
  • Patent number: 10199432
    Abstract: Manufacturing methods of MOSFET-type compact three-dimensional memory (3D-MC) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A MOSFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 5, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10191111
    Abstract: Method to extract timing diagrams from synchronized single- or two-photon pulsed LADA by spatially positioning the incident laser beam on circuit feature of interest, temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. A Single-Photon Laser-Assisted Device Alteration apparatus applies picosecond laser pulses of wavelength having photon energy equal to or greater than the silicon band-gap. A Two-Photon Laser-Assisted Device Alteration apparatus applies femtosecond laser pulses of wavelength having photon energy equal to or greater than half the silicon band-gap at the area of interest. The laser pulses are synchronized with test vectors so that pass/fail ratios can be altered using either the single-photon or the two-photon absorption effect. A sequence of synthetic images with error data illustrates timing sensitive locations.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: January 29, 2019
    Assignees: DCG Systems, Inc., NXP USA, Inc.
    Inventors: Kent Erington, Daniel J. Bodoh, Keith Serrels, Theodore Lundquist
  • Patent number: 10186306
    Abstract: The semiconductor device may include an address conversion circuit configured for generating a variable address. The semiconductor device may include a column decoder configured for generating a first output select signal or a second output select signal from a column address based on the variable address.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: January 22, 2019
    Assignee: SK hynix Inc.
    Inventor: Dong Yoon Ka
  • Patent number: 10180455
    Abstract: Circuits and methods are provided for a signal path between circuit parts. During normal operation, a delay is deactivated. During a burn-in test, the delay is activated. In the deactivated state, a delay component may be disconnected from a supply voltage.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: January 15, 2019
    Assignee: Infineon Technologies AG
    Inventors: Rex Kho, Markus Schuemmer, Human Boluki
  • Patent number: 10168923
    Abstract: An aspect includes coherency management between volatile memory and non-volatile memory in a through-silicon via (TSV) module of a computer system. A plurality of TSV write signals is simultaneously provided to the volatile memory and the non-volatile memory. A plurality of values of the TSV write signals is captured within a buffer of the non-volatile memory corresponding to a data set written to the volatile memory. Storage space is freed within the buffer as the data set corresponding to the values of the TSV write signals stored within the buffer is written to a non-volatile memory array within the non-volatile memory.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edgar R. Cordero, Kyu-hyoun Kim, Warren E. Maule, Adam J. McPadden, Anuwat Saetow
  • Patent number: 10168922
    Abstract: An aspect includes data backup management between volatile memory and non-volatile memory in a through-silicon via module of a computer system. Data is copied data from the volatile memory to the non-volatile memory during a refresh cycle of the volatile memory. The data is written to one or more non-volatile memory cells within the non-volatile memory prior to a next refresh cycle of the volatile memory.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edgar R. Cordero, Kyu-hyoun Kim, Adam J. McPadden, Anuwat Saetow
  • Patent number: 10157018
    Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN) begins by detecting, by an access module, a write failure of an encoded data slice to a storage unit of a set of DSN storage units. The method continues when detecting the write failure, by adding by the access module, an error entry to an error list. The method continues by recovering, by an integrity module, the error entry from the error list. The method continues by generating, by the integrity module, a rebuilt encoded data slice for the encoded data slice of the write failure. The method continues by facilitating storage of the rebuilt encoded data slice in the storage unit associated with the write failure.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Asimuddin Kazi, Ravi V. Khadiwala, Jason K. Resch
  • Patent number: 10153015
    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran
  • Patent number: 10146912
    Abstract: The present invention relates to medical apparatus for monitoring one or more physiological conditions of a patient and a method for monitoring one or more physiological conditions of a patient. Apparatus for measuring medical data is described, comprising: at least one medical data gathering module, at least one microprocessor, and further wherein the apparatus further comprises a medical data handling module separate from the at least one microprocessor for buffering medical data transfer between the medical data gathering module and the microprocessor and optionally further wherein the medical data handling module can gather and store data in predetermined groups of data and the microprocessor can retrieve data from the medical data handling module in one or more multiples of predetermined groups of data.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: December 4, 2018
    Assignee: DanMedical Ltd.
    Inventors: Ian George Moir Drysdale, David Morris Williams
  • Patent number: 10147478
    Abstract: A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: December 4, 2018
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Atsuo Koshizuka
  • Patent number: 10147472
    Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: William F. Jones, Jeffrey P. Wright
  • Patent number: 10141059
    Abstract: A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device decodes the x-bit row address and/or the y-bit column address to provide wordlines (WLs) and/or bitlines (BLs) to access one or more cells from among a memory array of the data storage device. The data storage device compares one or more subsets of the WLs and/or of the BLs to each other to detect for the failure. The data storage device determines the failure is present in the decoding of the x-bit row address and/or the y-bit column of the (x+y)-bit address when one or more WL and/or BL from among the one or more subsets of the WLs and/or the BLs differ.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Ching-Wei Wu
  • Patent number: 10134486
    Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column, a plurality of peripheral logic circuits including a normal peripheral logic circuit and a redundancy peripheral logic circuit for repairing the normal peripheral logic circuit, and a first path selection logic circuit configured to form first paths between the plurality of columns and the plurality of peripheral logic circuits, based on at least one defect from among a defect in at least one of the plurality of columns or a defect in at least one of the plurality of peripheral logic circuits.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoonki Kim, Yongho Kim, Changnam Park, Taejoong Song, Woojin Rim, Jonghoon Jung
  • Patent number: 10124751
    Abstract: An Electronic Control Unit (ECU) includes a diagnosis control request calculator, a power controller, a vehicle behavior monitor and the like. The ECU performs an auto-drive of a vehicle, during which a vehicle power source is controlled by the ECU for improving a rate achieve ratio of a fault diagnosis item. The ECU obtains vehicle information from a drive support ECU, a navigation device and the like. The ECU performs a control for improving a rate achieve ratio during the auto-drive. The ECU ranks the diagnosis items by the rate achieve ratios, i.e., from a low achiever diagnosis item toward a high achiever diagnosis item. The rate achieve ratio of the low achiever diagnosis item is improved by the ECU, by changing a controllable-state detection condition within a detection condition range.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: November 13, 2018
    Assignee: DENSO CORPORATION
    Inventor: Yuuichi Murase
  • Patent number: 10118819
    Abstract: A system for driving a MEMS array having a number of MEMS structures, each defining at least one row terminal and one column terminal, envisages: a number of row driving stages, each for supplying row-biasing signals to the row terminal of each MEMS structure associated to a respective row; a number of column driving stages, each for supplying column-biasing signals to the column terminal of each MEMS structure associated to a respective column; and a control unit, for supplying row-address signals to the row driving stages for generation of the row-biasing signals and for supplying column-address signals to the column driving stages for generation of the column-biasing signals. The control unit further supplies row-deactivation and/or column-deactivation signals to one or more of the row and column driving stages, for causing deactivation of one or more rows and/or columns of the MEMS array.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: November 6, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alberto Cattani, Alessandro Gasparini, Federico Guanziroli, Pierangelo Confalonieri
  • Patent number: 10115479
    Abstract: A memory device that includes a memory cell array and control circuit in which the memory cell array includes a normal region including a first failed block and a redundant region including a first redundant block replacing the first failed block. The control circuit includes a mapping table storing replacement information. The control circuit refers to the mapping table for accessing the first redundant block. When testing the memory device, the control circuit writes “1” in the normal region and the first redundant block, writes “0” in the redundant region except the first redundant block, adds the replacement information regarding a second failed block and second redundant block in the redundant region to the mapping table and verifies the result of replacing the second failed block with the second redundant block based on entire data read from the memory cell array with respect to entire range assigned to the address signal.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: October 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Jung Kim, Young-Uk Chang
  • Patent number: 10108472
    Abstract: Memory systems may include a memory including a plurality of memory blocks, and a controller suitable for, incrementing a first counter corresponding to a block of the plurality of blocks when the block is read, incrementing a second counter when the first counter reaches a predefined count number, determining an error count of the block when the second counter is incremented, and initiating a reclaim function when the error count exceeds an error threshold.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: October 23, 2018
    Assignee: SK Hynix Inc.
    Inventors: Yu Cai, Fan Zhang, June Lee, Haibo Li
  • Patent number: 10101923
    Abstract: According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader. The host device is configured to determine whether a first condition is established based on information obtained from the nonvolatile memory device; and rewrite, when determined the first condition is established, the bootloader so that an emergency software is initiated when booting the host device. The emergency software is executed on the host device. The host device is capable of issuing only a read command to the nonvolatile memory device under a control of the emergency software.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 16, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Daisuke Hashimoto
  • Patent number: 10102886
    Abstract: Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: October 16, 2018
    Assignee: INTEL CORPORATION
    Inventors: John H. Crawford, Brian S. Morris, Sreenivas Mandava, Raj K. Ramanujan
  • Patent number: 10082960
    Abstract: A memory device is disclosed. The memory device includes a memory array. The memory array includes a main memory block and an extra memory block. The memory array includes a main bit line and an extra bit line. A ratio of a quantity of the extra memory block to a quantity of the main memory block is a block quantity ratio A. A ratio of a quantity of the extra bit line to a quantity of the main bit line is a bit line quantity ratio B. The block quantity ratio A is larger than the bit line quantity ratio B.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: September 25, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 10078544
    Abstract: An apparatus and method are described for an on-chip reliability controller. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a reliability controller to perform one or more self-test/diagnostic operations, the reliability controller to aggregate reliability data resulting from the self-test/diagnostic operations; a reliability estimator integral to the reliability controller to use the aggregated reliability data to perform a probability analysis to determine reliability estimates for one or more components of the processor; and a control unit integral to the reliability controller to adjust one or more variables and/or circuitry related to operation of the processor responsive to the reliability estimates.
    Type: Grant
    Filed: December 19, 2015
    Date of Patent: September 18, 2018
    Assignee: Intel Corporation
    Inventors: Clark N. Vandam, Balkaran Gill, Junho Song, Suriya Suriya Ashok Kumar, Kasyap Pasumarthi
  • Patent number: 10074443
    Abstract: Disclosed here is a semiconductor device that comprises plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded sepals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Hiroshi Akamatsu
  • Patent number: 10074416
    Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device includes a latch selectably coupled to a column of the memory cells and configured to store a data value moved from the sensing circuitry. The memory device includes a controller configured to direct movement of the data value from the sensing circuitry to the latch.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush