Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.

Abstract: A memory test system is disclosed that includes a memory integrated circuit (IC) and a memory functional tester. The memory IC includes a plurality of memory banks, where each memory bank includes a plurality of memory cells. The memory functional tester includes an adjustable voltage generator circuit, a read current measurement circuit, and a controller. The memory functional tester performs a write/read functional test on the memory bank over a number of write control voltages to determine a preferred write control voltage, where the preferred write control voltage is designated for use during subsequent write operations to the memory bank during an operational mode.

Abstract: A memory controller may include an address control block. The address control block may be configured to remap a write target address when a number of write data having a first logic level is within a correctable range and when a level of a datum corresponding to the write target address has the first logic level.

Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

Abstract: A memory system and an operating method thereof are provided. The memory system includes a storage device including a mode register suitable for activating or inactivating an auto mode and a memory suitable for storing data, and a storage device controller controlling the mode register to enter a test mode, after inactivating the auto mode, during a test operation of the storage device, and controlling the mode register to activate the auto mode again when the test operation of the storage device is completed.

Abstract: Systems and methods for mitigating defects in a crossbar-based computing environment are disclosed. In some implementations, an apparatus comprises: a first row wire; a second row wire having a defective device; and a crossbar array configured to receive a first input signal. The defective device is associated with a defect pattern; the first row wire and the second row wire are located within the crossbar array; and the first input signal is configured to be provided to the first row wire. The apparatus further comprises a shuffling module connected to the crossbar array and configured to divert the input signal from the first row wire to the second row wire in accordance with a determination that the defect pattern is within a predefined approximation to a target circuit pattern associated with the first input signal.

Abstract: A semiconductor device comprises an array region, a dummy region, pillars of an electrically insulative material in the array region and the dummy region. The semiconductor device further comprises electrically conductive contacts between adjacent pillars of the electrically insulative material in the array region, another electrically insulative material between adjacent pillars of the electrically insulative material in the dummy region, an electrically conductive material over the conductive contacts in the array region and over the electrically insulative material in the dummy region, and an oxide between the electrically conductive material in the dummy region and the electrically insulative material in the dummy region. Related semiconductor devices, systems, and methods are also disclosed.

Abstract: A phase change memory apparatus comprises at least one heating layer; and at least one phase change layer comprising a vanadium dioxide layer, wherein each of the at least one phase change layer is set corresponding to each of the at least one heating layer, the at least one heating layer is configured to heat the at least one phase change layer.

Abstract: A method for encoding and storing text information using DNA as a storage medium, a decoding method therefor and an application thereof. The method for using DNA to store text information comprises: encoding characters into computer binary digits by means of encoding, and converting the binary digits into DNA sequences by means of transcoding; and artificially synthesizing the DNA sequences encoded with character information, positioning the characters by means of a designed ligation adapter, and assembling the DNA sequences encoded with the character information according to a pre-set order. The method for using DNA to store text information has the advantages of a small storage volume, a large storage capacity, a strong stability and low maintenance costs.

Abstract: Various implementations described herein refer to an integrated circuit. The integrated circuit may include memory circuitry having multiple bitcell arrays with redundant rows of bitcells. The integrated circuit may include comparator logic disposed outside the memory circuitry to de-assert access to one or more faulty rows of bitcells and to assert access to the redundant rows of bitcells.

Abstract: Methods that can dynamically merge parity data for multiple data stripes are provided. One method includes detecting, by a processor, a disk failure in a redundant array of independent disks (RAID) configuration and, in response to detecting the disk failure, merging parity data stored in a plurality of sets of segments in a stripe of the RAID configuration to free space in a set of parity segments of the plurality of sets of segments. Systems and computer program products for performing the method are also provided.

Abstract: A lookup-table type TL-TCAM hardware search engine includes a SL decoder, a TL-TCAM array, and the data stored in the TL-TCAM hardware search engine is obtained by performing lookup table operation in the corresponding TCAM hardware search engine, the SL decoder is used to decode the search word and send it to the TL-TCAM hardware search engine array, and the decoding is to convert a search word SL corresponding to data in a TCAM hardware search engine table into a search word LSL corresponding to TL-TCAM hardware search engine table data, the effect is that TCAM adds a decoder, cooperates with the decoder and by lookup table method converts the TCAM table data to a new circuit unit that can be adapted to the added search line.

Abstract: A memory device includes a memory bank comprising a plurality of addressable groups of memory cells comprising a primary and a secondary set of addressable groups and control circuitry comprising repair address match circuitry, comprising first inputs to receive row address values corresponding to a first group of the primary set of addressable groups, second inputs to receive fused address values corresponding to a second group of the primary set of addressable groups having been repaired, and a selection element, comprising a first selection input to receive a first signal indicative of whether a first row address value is identical to a first fused address value, a second selection input to receive a second signal indicative of whether a second row address value is identical to a second fused address value, and an output to selectively transmit a result as one of the first or second signal.

Abstract: An example computer-implemented method includes receiving hardware testing results, an address, input/output (I/O) data, a redundancy status, and an input-memory-output mapping corresponding to a memory being tested. The method includes locating a failed cell of the memory based on the hardware testing results, the address, the input/output data, the redundancy status, and the input-memory-output mapping. The method also includes automatically repairing the failed cell.

Abstract: A power control system, method, and architecture are disclosed for a multi-bank memory which provides independent, concurrent memory access to at least one memory block in each memory bank by using observation circuits to monitor bus masters connected over bus master interface signals to an interconnect for memory access requests to the multi-bank memory and to provide notifications to a power control circuitry that a valid memory access request was issued by a bus master over the bus master interface, where the power control circuitry processes the notifications received from each observation circuit and generates therefrom power control signals that are provided directly to each memory block and to bypass the interconnect, thereby separately controlling a power state for each memory block with power-up control signals that arrive at each memory block at or before a memory access request sent over the interconnect.

Abstract: A self-test apparatus for use in an electronic system includes an inter-chip communication bus, a plurality of circuit devices, circuitry including memory, and test controller circuitry. The plurality of circuit devices each has a distributed self-test controller circuit and analog, mixed signal or digital circuit elements. The distributed self-test controller circuits are integrated communicatively via the inter-chip communication bus and negotiate a self-test protocol with each other. The circuitry including memory stores self-test properties of the circuit elements, the self-test properties corresponding to an identifier of each of the circuit elements and a manner or protocol in which the circuit elements are tested. The test controller circuitry collects the self-test properties of the circuit elements and controls execution of the self-test according to the negotiated self-test protocol and the self-test properties.

Abstract: A memory system includes a memory device; and a controller configured to transmit a target address to the memory device for performing an access operation, receive from the memory device a reference address at which the access operation has been performed, and selectively re-perform the access operation based on the reference address. The controller re-performs the access operation when the reference address is different from the target address.

Abstract: A semiconductor system may be configured to classify failure groups of data including erroneous bits and may replace a memory area in which the failure groups are stored with a redundancy area. The replacement of the memory area in which the failure groups are stored, with the redundancy area, may be performed according to priorities of the failure groups.

Abstract: According to one embodiment, a semiconductor memory device includes: planes each including a memory cell array including memory cells; a comparator configured to, when suspending a write operation and executing a read operation, compare a first plane address corresponding to the write operation with a second plane address corresponding to the read operation; and a controller configured to suspend the write operation and execute the read operation. The controller is configured to, based on an output signal from the comparator, execute the first read operation when the first and second plane addresses match, and execute the second read operation when the first and second plane addresses differ.

Abstract: A luminous solid-state disk, comprises: a solid-state disk; a light-emitting member; a light-emitting controller; a disk enclosure accommodating the solid-state disk, the light-emitting member and the light-emitting controller, the disk enclosure having a connection interface, the light-emitting controller in connection to the connection interface to receive, through the connection interface, a computer terminal information from a computer, the light-emitting controller uses, according to the computer terminal information, a control signal to control the light-emitting member, the disk enclosure having a main wall surface, which is transparent, wherein light from the light-emitting member directly transmits through the main wall surface or is reflected to transmit through the main wall surface. Through the above structure, the main wall surface can be used as an information display to inform the user of the computer information.

Abstract: A memory device includes a memory array, a first buffer, a second buffer, a repair logic circuit and an internal memory. The method of operating the memory device includes: the repair logic circuit receiving a bad column table from the internal memory, the bad column table containing information of a bad column in the memory array; the first buffer receiving first data; the repair logic circuit receiving the first data from the first buffer; and the repair logic circuit mapping the first data onto second data according to the bad column table.

Abstract: A semiconductor device includes a soft repair control circuit configured to generate an enable signal, in response to a soft repair control signal, wherein the enable signal is enabled when first and second internal addresses counted in a refresh operation have the same combination as first and second failure addresses, and the semiconductor device also includes a core circuit including first, second, third, and fourth regions each including a plurality of word lines which are activated based on a combination of the first, the second, third, and fourth internal addresses, wherein the core circuit is configured to repair, in response to the enable signal, a word line in which a failure has occurred and which is included in a region selected among the first, second, third, and fourth regions by the third and fourth internal addresses.

Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.

Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide the first power voltage for the plurality of first memory cells, and to provide the second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells and the plurality of second memory cells.

Abstract: A semiconductor device including a gate-all-around based non-volatile memory device includes isolated channels including tunnel dielectric material disposed around gate-all-around field effect transistor (GAA FET) channels, at least one floating gate including a first gate material encapsulating the isolated channels, and at least one control gate including a second gate material encapsulating the isolated channels.

Abstract: A memory device includes a memory cell array comprising a plurality of antifuse memory cells coupled to a plurality of word lines, a plurality of voltage lines and a plurality of bit lines, and a first decoder suitable for generating a word line driving signal associated with a target memory cell among the plurality of antifuse memory cells in response to a first address, and asserting the word line driving signal at least twice during a program operation.

Abstract: Disclosed herein are methods of using embedded disconnected circuits (EDC) in magnetic storage media to assist in reading data from and writing data to the magnetic storage media. A wireless activation signal is used to activate an EDC in a magnetic storage media. Once activated, the EDC may assist to record data in and/or read data from one or more memory locations of the magnetic storage media.

Abstract: A redundancy circuit includes a selection control signal generation circuit and a column control circuit. The selection control signal generation circuit drives an internal node, which is initialized, to generate a selection control signal when a logic level of a latched address signal is different from a logic level of a fuse signal. The column control circuit buffers a pre-column selection signal based on the selection control signal to generate a column selection signal for execution of a column operation of cells or to generate a redundancy column selection signal for execution of the column operation of redundancy cells.

Abstract: A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

Abstract: A Data Storage Device (DSD) includes a first memory for storing data and a Storage Class Memory (SCM) for storing data. The SCM has at least one characteristic of being faster than the first memory in storing data, using less power to store data than the first memory, and providing a greater usable life than the first memory for repeatedly storing data in a same memory location. At least a portion of the SCM is allocated or reserved for use by a host, and logical addresses assigned to the SCM are mapped to device addresses of the first memory identifying locations for storing data in the first memory. The host is provided with an indication of the logical addresses assigned to the SCM to allow the host to retrieve data from and store data in the DSD or to directly access data using the logical addresses assigned to the SCM.

Abstract: A power management system includes a memory component storing a plurality of configuration profiles. A plurality of configuration pins are operatively coupled to the memory component. One or more of the plurality of configuration pins receive one or more signals to selectively activate one of the plurality of configuration profiles.

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for storing an enable state of an address. The address may be broadcast from a fuse array to a fuse latch, and may be associated with enable information. The fuse latch may include a plurality of enable latch circuits, each of which may receive the enable information in common, and each of which may store the enable information as an enable bit. Each of the enable latch circuits may provide a respective enable signal based on a state of the stored enable bit. An enable logic circuit may provide an overall enable signal with a state determined by the states of all of the enable signals from the plurality of enable latch circuits.

Abstract: The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

Abstract: A stacked electronic structure comprises: a substrate and a magnetic device, wherein a plurality of electronic devices and a plurality of conductive pillars are disposed on and electrically connected to the substrate, wherein a molding body encapsulates the plurality of electronic devices, wherein the magnetic device is disposed over the top surface of the molding body and the plurality of conductive pillars, wherein a first terminal of the magnetic device is disposed over and electrically connected to a first conductive pillar and a second terminal of the magnetic device is disposed over and electrically connected to a second conductive pillar without using any substrate.

Abstract: A programmable logic device includes an integrated circuit die having a programmable fabric region including N identical programmable logic partitions. In some embodiments, N?1 of the identical programmable logic partitions are user-programmable. In addition, and in some cases, one of the identical programmable logic partitions is a spare logic partition. In some embodiments, the integrated circuit die further includes a network-on-a-chip (NOC) including a vertical NOC (VNOC) and a horizontal NOC (HNOC). By way of example, the N identical programmable logic partitions are configured to communicate exclusively through the NOC. In some embodiments, a defective one of the N?1 identical programmable logic partitions is configured for swapping with the spare logic partition.

Abstract: A circuit includes a memory configured to store a data unit and parity bits, the parity bits being based on a write address associated with the stored data unit. An address port is configured to receive a read address for the stored data unit. A decoding circuit is configured to generate a decoded write address from the read address and the parity bits, and an error detecting circuit is configured to determine if an address error exists based on a comparison of the decoded write address to the read address.

Abstract: A memory device includes a data storage region and a spare column remap storage. The data storage region includes a plurality of sub-arrays, each of which has a plurality of main columns and a plurality of spare columns. The spare column remap storage includes a plurality of storage units storing address information of the main columns repaired using the plurality of spare columns. At least one of the plurality of storage units included in the spare column remap storage is provided to store address information of the main column repaired in one of the plurality of sub-arrays and address information of the main column repaired in another of the plurality of sub-arrays.

Abstract: In one embodiment, an apparatus comprises a plurality of memory partitions, each memory partition comprising an array of 3D crosspoint memory, and a storage device controller comprising a memory comprising memory cells to store addresses of replacement memory partitions and addresses of unusable memory partitions and a partition address translation engine coupled to the memory, the partition address translation engine comprising logic to determine whether to redirect a memory access command received from a host computing device to a replacement memory partition based on the contents of the memory.

Abstract: Apparatuses, systems, and methods related to determination of a match between data values stored by several arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by two arrays selected from the plurality to determine whether there is a match between the data values stored by the two arrays. The apparatus further includes an output component configured to output data values of one of the two arrays responsive to determination of the match between the data values stored by the two arrays.

Abstract: A method for forming a high dielectric constant (high-?) dielectric layer on a substrate including performing a pre-clean process on a surface of the substrate. A chloride precursor is introduced on the surface. An oxidant is introduced to the surface to form the high-? dielectric layer on the substrate. A chlorine concentration of the high-? dielectric layer is lower than about 8 atoms/cm3.

Abstract: Provided is a technique which includes forming on a substrate an oxide film containing silicon or a metal element and doped with a dopant by performing a cycle a predetermined number of times, wherein the cycle includes sequentially and non-simultaneously performing: (a) supplying a first gas to the substrate wherein the first gas is free of chlorine and contains boron or phosphorus as the dopant; (b) supplying a second gas to the substrate wherein the second gas contains silicon or the metal element; and (c) supplying a third gas to the substrate wherein the third gas contains oxygen.

Abstract: A repair method of a display panel comprises: disposing a repair line on a non-display area; dividing the repair line into a first, a second, and a third segments sequentially connected; electrically connecting the first end of the target data line to an input end of the gate driving chip through the first segment; dividing the second segment of the repair line into a first and second parts, wherein the second part electrically connects the operational amplifiers (OPAs) of the gate driving chip for amplifying the repair signal transmitted through the repair line, and the first part electrically connects two gate driving chips; electrically connecting the last output end of the gate driving chip to the second end of the target data line through the third segment, for transmitting the repair signal amplified by the (OPA) to the breakpoint through the second end of the target data line.

Abstract: In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.

Abstract: An distance measurement apparatus includes a light source to emit irradiation light, circuitry to output, to the light source, a first current that changes in accordance of light-emission timing information defining at least turn-on timing of the light source, and a second current that does not change in accordance of the light-emission timing information, a sensor to detect reflection light reflected from an object irradiated with the irradiation light emitted from the light source. The circuitry calculates a distance to the object based on a detection amount of the reflection light detected by the sensor.

Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.

Abstract: A semiconductor memory device includes a memory cell array and an address decoder. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word-lines and bit-lines, each of the plurality of memory blocks are divided into a plurality of row blocks by row block identity bits of a row address, and each of the of row blocks includes a plurality of sub-array blocks arranged in a first direction. The address decoder changes a physical row address of a memory cell that stores or outputs data based on a column address received with a write command or a read command.

Abstract: A method for assisting a memory cell in an access operation is provided. The method includes: setting a supply voltage to a first supply voltage level to determine a reference probability value of the memory cell applied by the first supply voltage level; applying an assist voltage to an access line coupled to the memory cell, and setting the supply voltage to a second supply voltage level to determine a relationship between the assist voltage and the access failure probability of the memory cell applied by the second supply voltage level; determining, from the relationship, a target assist voltage level of the assist voltage corresponding to the reference probability value; and providing an assist circuit configured to apply the target assist voltage level to the access line during the access operation, wherein the memory cell is applied by the second supply voltage level during the access operation.

Abstract: A semiconductor memory device a memory cell array and a repair control circuit. The memory cell array including a normal cell region and a redundancy cell region, the normal cell region including a plurality of normal region groups, and redundancy cell region configured to replace failed memory cells of the normal cell region. The repair control circuit configured to, determine a target normal region group from among the plurality of normal region groups based on an input address, extract target fail addresses from among a plurality of fail addresses based on the target normal region group, and control a repair operation based on the target fail addresses and the input address.

Abstract: According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.