Abstract: Circuits and methods are provided for a signal path between circuit parts. During normal operation, a delay is deactivated. During a burn-in test, the delay is activated. In the deactivated state, a delay component may be disconnected from a supply voltage.

Abstract: An aspect includes coherency management between volatile memory and non-volatile memory in a through-silicon via (TSV) module of a computer system. A plurality of TSV write signals is simultaneously provided to the volatile memory and the non-volatile memory. A plurality of values of the TSV write signals is captured within a buffer of the non-volatile memory corresponding to a data set written to the volatile memory. Storage space is freed within the buffer as the data set corresponding to the values of the TSV write signals stored within the buffer is written to a non-volatile memory array within the non-volatile memory.

Abstract: An aspect includes data backup management between volatile memory and non-volatile memory in a through-silicon via module of a computer system. Data is copied data from the volatile memory to the non-volatile memory during a refresh cycle of the volatile memory. The data is written to one or more non-volatile memory cells within the non-volatile memory prior to a next refresh cycle of the volatile memory.

Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN) begins by detecting, by an access module, a write failure of an encoded data slice to a storage unit of a set of DSN storage units. The method continues when detecting the write failure, by adding by the access module, an error entry to an error list. The method continues by recovering, by an integrity module, the error entry from the error list. The method continues by generating, by the integrity module, a rebuilt encoded data slice for the encoded data slice of the write failure. The method continues by facilitating storage of the rebuilt encoded data slice in the storage unit associated with the write failure.

Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

Abstract: The present invention relates to medical apparatus for monitoring one or more physiological conditions of a patient and a method for monitoring one or more physiological conditions of a patient. Apparatus for measuring medical data is described, comprising: at least one medical data gathering module, at least one microprocessor, and further wherein the apparatus further comprises a medical data handling module separate from the at least one microprocessor for buffering medical data transfer between the medical data gathering module and the microprocessor and optionally further wherein the medical data handling module can gather and store data in predetermined groups of data and the microprocessor can retrieve data from the medical data handling module in one or more multiples of predetermined groups of data.

Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

Abstract: A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information.

Abstract: A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device decodes the x-bit row address and/or the y-bit column address to provide wordlines (WLs) and/or bitlines (BLs) to access one or more cells from among a memory array of the data storage device. The data storage device compares one or more subsets of the WLs and/or of the BLs to each other to detect for the failure. The data storage device determines the failure is present in the decoding of the x-bit row address and/or the y-bit column of the (x+y)-bit address when one or more WL and/or BL from among the one or more subsets of the WLs and/or the BLs differ.

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column, a plurality of peripheral logic circuits including a normal peripheral logic circuit and a redundancy peripheral logic circuit for repairing the normal peripheral logic circuit, and a first path selection logic circuit configured to form first paths between the plurality of columns and the plurality of peripheral logic circuits, based on at least one defect from among a defect in at least one of the plurality of columns or a defect in at least one of the plurality of peripheral logic circuits.

Abstract: An Electronic Control Unit (ECU) includes a diagnosis control request calculator, a power controller, a vehicle behavior monitor and the like. The ECU performs an auto-drive of a vehicle, during which a vehicle power source is controlled by the ECU for improving a rate achieve ratio of a fault diagnosis item. The ECU obtains vehicle information from a drive support ECU, a navigation device and the like. The ECU performs a control for improving a rate achieve ratio during the auto-drive. The ECU ranks the diagnosis items by the rate achieve ratios, i.e., from a low achiever diagnosis item toward a high achiever diagnosis item. The rate achieve ratio of the low achiever diagnosis item is improved by the ECU, by changing a controllable-state detection condition within a detection condition range.

Abstract: A system for driving a MEMS array having a number of MEMS structures, each defining at least one row terminal and one column terminal, envisages: a number of row driving stages, each for supplying row-biasing signals to the row terminal of each MEMS structure associated to a respective row; a number of column driving stages, each for supplying column-biasing signals to the column terminal of each MEMS structure associated to a respective column; and a control unit, for supplying row-address signals to the row driving stages for generation of the row-biasing signals and for supplying column-address signals to the column driving stages for generation of the column-biasing signals. The control unit further supplies row-deactivation and/or column-deactivation signals to one or more of the row and column driving stages, for causing deactivation of one or more rows and/or columns of the MEMS array.

Abstract: A memory device that includes a memory cell array and control circuit in which the memory cell array includes a normal region including a first failed block and a redundant region including a first redundant block replacing the first failed block. The control circuit includes a mapping table storing replacement information. The control circuit refers to the mapping table for accessing the first redundant block. When testing the memory device, the control circuit writes “1” in the normal region and the first redundant block, writes “0” in the redundant region except the first redundant block, adds the replacement information regarding a second failed block and second redundant block in the redundant region to the mapping table and verifies the result of replacing the second failed block with the second redundant block based on entire data read from the memory cell array with respect to entire range assigned to the address signal.

Abstract: Memory systems may include a memory including a plurality of memory blocks, and a controller suitable for, incrementing a first counter corresponding to a block of the plurality of blocks when the block is read, incrementing a second counter when the first counter reaches a predefined count number, determining an error count of the block when the second counter is incremented, and initiating a reclaim function when the error count exceeds an error threshold.

Abstract: Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.

Abstract: According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader. The host device is configured to determine whether a first condition is established based on information obtained from the nonvolatile memory device; and rewrite, when determined the first condition is established, the bootloader so that an emergency software is initiated when booting the host device. The emergency software is executed on the host device. The host device is capable of issuing only a read command to the nonvolatile memory device under a control of the emergency software.

Abstract: A memory device is disclosed. The memory device includes a memory array. The memory array includes a main memory block and an extra memory block. The memory array includes a main bit line and an extra bit line. A ratio of a quantity of the extra memory block to a quantity of the main memory block is a block quantity ratio A. A ratio of a quantity of the extra bit line to a quantity of the main bit line is a bit line quantity ratio B. The block quantity ratio A is larger than the bit line quantity ratio B.

Abstract: An apparatus and method are described for an on-chip reliability controller. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a reliability controller to perform one or more self-test/diagnostic operations, the reliability controller to aggregate reliability data resulting from the self-test/diagnostic operations; a reliability estimator integral to the reliability controller to use the aggregated reliability data to perform a probability analysis to determine reliability estimates for one or more components of the processor; and a control unit integral to the reliability controller to adjust one or more variables and/or circuitry related to operation of the processor responsive to the reliability estimates.

Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device includes a latch selectably coupled to a column of the memory cells and configured to store a data value moved from the sensing circuitry. The memory device includes a controller configured to direct movement of the data value from the sensing circuitry to the latch.

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute component coupled to the sense amplifier via pass gates coupled to logical operation selection logic. The logical operation selection logic can be configured to control pass gates based on a selected logical operation.

Abstract: Disclosed here is a semiconductor device that comprises plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded sepals, and a plurality of fuse circuits provided correspondingly with the decoded signals and configured to be programmed responsive to the decoded signals, respectively

Abstract: The present invention relates to the field of human-computer interaction and in particular, to apparatus, systems, and methods for facilitating interaction with computers and computing systems in an intuitive manner.

Abstract: Example implementations relate to post package repair (PPR) data in non-volatile memory. In example implementations, PPR data may be stored in non-volatile memory on a memory module. PPR data may indicate how many PPRs have been performed on the memory module.

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.

Abstract: A non-volatile memory may be resident in a data storage device. The non-volatile memory can consist of a rewritable in-place memory cell having a read-write asymmetry. The non-volatile memory may be divided into a first group of tiers with a selection module of the data storage device prior to adapting to an event by altering the non-volatile memory into a second group of tiers. The first and second groups of tiers being different.

Abstract: Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.

Abstract: A method of reducing quantum leakage in a qubit device which includes receiving a set of energy level values for a multi-level system which includes first and second working levels |0>, |1> which provide a qubit, and at least one other level |2>, and performing an iteration of determining quantum leakage from at least one of the first and second working levels to the at least one other level for a quantum operation A for at least one pulse wherein each pulse has a respective pulse duration, determining whether the quantum leakage is greater than or equal to a threshold value; and, based on the quantum leakage being greater than or equal to the threshold value, changing the duration of at least one of the at least one pulse.

Abstract: Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. The control circuit, in a second repair mode, receives second repair address information and provides the second repair address information to the storage latch circuit and disables storing the second address information into the non-volatile storage element.

Abstract: A dynamic random access memory (DRAM) has a main memory cell array and a redundant component unit. The redundant component unit includes a plurality of e-fuses and a latch region. The plurality of the e-fuses are arranged into a first e-fuse part and a second e-fuse part, wherein the first e-fuse part is used to store address information of a fault memory cell in the main memory cell array and the second e-fuse part is used as a plurality of capacitors. The latch region includes a plurality of latches used to store the address information of the fault memory cell stored in the first e-fuse part, wherein the plurality of the capacitors of the second e-fuse part are respectively coupled to the plurality of the latches to provide a capacitance value for an input/output (I/O) endpoint of each of the latches.

Abstract: A redundant system includes a primary system including a first node and a second node, and a secondary system including a third node and a fourth node. When the secondary system in place of the primary system operates, the fourth node executes first takeover processing or second takeover processing, the first takeover processing taking over the primary system on the basis of data update information acquired from either a second inter-system transfer path or a second intra-system transfer path, and the second takeover processing taking over the primary system on the basis of both the data update information acquired from the second inter-system transfer path and the data update information acquired from the second intra-system transfer path.

Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (NVM). The program verify sequence can have one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified. The memory controller can detect an approximate percentage of memory cells for each program verify level in which data is successfully written. The memory controller can determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold.

Abstract: A circuit for outputting information of a memory circuit during a self-refresh mode includes a driver. The driver is coupled to a self-refresh control circuit and a self-refresh address counter. The driver is used for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode. Each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.

Abstract: A memory device includes a memory cell array, a multiplexing circuit, and a control logic circuit. The memory cell array includes a first sub memory cell array, a second sub memory cell array, and a third sub memory cell array. The multiplexing circuit selects the first sub memory cell array, the second sub memory cell array, and the third sub memory cell array in a first mode of operation, and when the first sub memory cell array is defective in a second mode of operation, the multiplexing circuit selects the second sub memory cell array and the third sub memory cell array. The control logic circuit selects the first mode of operation or the second mode of operation. The control logic circuit controls the multiplexing circuit so that the first, second and third sub memory cell arrays are connected to input or output pads.

Abstract: A memory system includes a main memory array, a redundant memory array, and a content addressable memory (CAM). The CAM includes a plurality of entries, wherein each entry includes a plurality of column address bits and a plurality of maskable row address bits. When an access address for a memory operation matches an entry of the CAM, the memory system is configured to access the redundant memory array to perform the memory operation.

Abstract: A non-volatile semiconductor memory device includes a memory array 20, including a plurality of memory elements; a selection part, selecting the memory elements of the memory array based on address data; a mode selection part 30, selecting any one of a RAM mode and a flash mode, where the RAM mode is a mode adapted to overwrite data of the memory element according to writing data, and the flash mode is a mode adapted to overwrite data of the memory element when the writing data is a first value and prohibit overwrite when the writing data is a second value; and a write control part, writing the writing data to the selected memory element according to the RAM mode or the flash mode selected by the mode selection part 30.

Abstract: A fuse circuit may include a plurality of first fuse sets and a plurality of second fuse sets. The plurality of first fuse sets may be used to store a defect address detected before packaging of a semiconductor apparatus. The plurality of second fuse sets may be used to store a defect address detected after the packaging. The plurality of first fuse sets may be shared by a plurality of first redundant word lines, and the plurality of second fuse sets may be in one-to-one correspondence with a plurality of second redundant word lines.

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.

Abstract: In one embodiment, it is proposed a method for storing input data on a set of DNA strands, said input data being represented in a numeral system. This method is remarkable in that it comprises: formatting said input data into a set of blocks of data, each block of data having a size inferior to a size of one DNA strand; applying a first encoding with an erasure code on said set of blocks of data, defining a first set of modified blocks of data, each modified block of data having a size inferior to a size of one DNA strand; applying a second encoding using an error correcting code on each modified block of data of said first set, defining a second set of modified blocks of data, each modified block having a size inferior to a size of one DNA strand; encoding each modified block of data of said second set into a nucleotides block sequence; generating a set of DNA strands, each DNA strand comprising a nucleotides block sequence obtained through said encoding.

Abstract: The present disclosure provides a method. The method includes copying a data stored in memory cells associated with a normal word line subject to a row hammer effect into memory cells associated with a hot word line before a condition is satisfied, wherein the condition includes an access frequency of the normal word line reaching a threshold frequency; accessing, based on a logical address, the normal word line before the condition is satisfied; accessing, based on the logical address, the hot word line associated with the copied data only if the condition is satisfied; and accessing the data no longer from the normal word line only if the condition is satisfied.

Abstract: A search system executes: a first write procedure of extracting, for data in a data sequence, metadata from the data in input order and writing the metadata into a first storage module in association with identification information uniquely identifying the data; a second write procedure of writing, in parallel with the first write procedure, the data in the data sequence into a second storage module in input order in association with the identification information, and writing the identification information in the second storage module into a third storage module; a reception procedure of receiving a search request including a first search condition relating to search target data; a search procedure of searching a search destination, which is selected from the first and third storage modules in accordance with the search request received, for the identification information satisfying the first search condition; and an output procedure of outputting a search result.

Abstract: A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.

Abstract: An apparatus and method for securely suspending and resuming the state of a processor. For example, one embodiment of a method comprises: generating a data structure including at least the monotonic counter value; generating a message authentication code (MAC) over the data structure using a first key; securely providing the data structure and the MAC to a module executed on the processor; the module verifying the MAC, comparing the monotonic counter value with a counter value stored during a previous suspend operation and, if the counter values match, then loading processor state required for the resume operation to complete. Another embodiment of a method comprises: generating a first key by a processor; securely sharing the first key with an off-processor component; and using the first key to generate a pairing ID usable to identify a pairing between the processor and the off-processor component.

Abstract: An apparatus for storing X-bit digitized data, the register file comprising: a plurality of registers each register configured for storing X bits, wherein each register is partitioned into Y sub-registers such that each sub-register stores at least X/Y bits, and wherein at least one extra X/Y-bit sub-register is incorporated in each register to provide redundancy in the number of sub-registers for a total of at least Y+1 sub-registers per register, so that if a first sub-register in a first register includes faulty bits, data destined for storage in the first sub-register is stored in a second sub-register, in the first register, that does not include faulty bits.

Abstract: A nonvolatile storage circuit may include a nonvolatile storage unit configured to include fuse set groups respectively including a plurality of fuse sets and a flag fuse; a rupture control unit configured to program an input address to the fuse sets in a first program mode, and to program a same input address to a specific fuse set among the plurality of fuse sets in a specific fuse set group among the fuse set groups and to program the flag fuse of the specific fuse set group in a second program mode; and a boot-up control unit configured to control the address programmed in the fuse sets to be outputted as fuse data, and to control the address programmed in the specific fuse set to be outputted as fuse data of remaining fuse sets among the plurality of fuse sets in the specific fuse set group.

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include mirroring, in a distributed storage system having multiple storage nodes, data on the storage nodes. Upon the distributed storage system detecting a loss of communication with a given storage node, a log including updates to the data stored in the given storage node is recorded and, the recorded updates can be applied to the given storage node upon communication with the given storage node being reestablished. In some embodiments, the distributed storage system may be configured as a software defined storage system where the storage nodes can be implemented as either virtual machines or software containers. In additional embodiments, upon detecting the loss of communication, a redistribution of the mirrored data among remaining storage nodes is initiated upon detecting the loss of communication, and the redistribution is rolled back upon reestablishing the communication.

Abstract: Stacked semiconductor packages and methods for performing bare die testing on a functional silicon die in a stacked semiconductor package are described. In an example, a stacked semiconductor package includes a functional silicon die, a test controller having signature accumulation logic embedded therein, and a fabric to route transactions between the test controller and any of a plurality of near memory controllers of the functional silicon die.

Abstract: A method of operating a data storage device including a non-volatile memory device includes receiving an update command from a host; and closing a first log block, which is included in the non-volatile memory device and which includes an open word line, in response to the update command. The closing is performed to avoid update data, which is transmitted from the host and related to the update command, being subsequently written to an empty page of the first log block.

Abstract: In a memory module having a buffer component, a plurality of data signaling paths and a plurality of memory dies each coupled to a respective one of the data signaling paths, the buffer component receives and stores a first configuration value that specifies a memory-die quantity N, where N is permitted to range from a first value corresponding to the quantity of the data signaling paths to at least one value less than the first value. The buffer component further receives a memory read command and enables, in accordance with the first configuration value, a quantity N of the memory dies to output read data in response to the memory read command.

Abstract: Disclosed are a system and a method for address translation for a flash memory device, and particularly, disclosed is a technology that is capable of efficiently performing address translation between a logical address provided to the outside of a flash memory and a physical address of an actual flash memory in managing the flash memory device. The system includes: a flash memory system writing a corresponding data page by allocating a physical address space when there is a request for writing a data page from storage clients, and performing address translation between a physical address and a logical address; and a logical address space formed between the flash memory system and the storage client to provide the logical address.