Abstract: Disclosed herein is a decoder circuit including: a charge up transistor for maintaining the content of input address signals; a power supply switching transistor for controlling a charge up current which is supplied to the charge up transistor; a predetermined number of selection transistors which are connected at a connection node between the charge up transistor and the power supply switching transistor for selecting an output word line, and; a bootstrap transistor which is connected at an opposide side of the connection node with respect to the charge up transistor. The characteristic feature of the present invention is the provision of a charge compensation transistor which is connected at a connection node between the charge up transistor and the power supply switching transistor so as to compensate for the charges of the charge up transistor.

Abstract: A semiconductor memory device comprises a matrix array of a plurality of memory cells wherein a load circuit connected to column lines of the matrix array for charging the column lines is enabled to provide different resistance values between the actions of charging and discharging the column lines.

Abstract: Computer circuitry for rapidly discharging the deselected word lines in high-speed very low power random access memories that may be accidentally triggered by noise pulses if permitted to decay at the normal rate.

Abstract: A differential type amplifier circuit for use as a sensing amplifier in a memory circuit having a first stage amplifier and a second stage differential type amplifier. The first stage amplifier includes a pair of amplification circuits, the inputs of which are selectively clamped to a predetermined potential. The first stage amplifier functions to amplify low level differential input signals and these amplified signals are applied to the second stage amplifier, the amplified level of the input signals being sufficient to operate the second stage amplifier irrespective of changes in the threshold voltage of the second stage amplifier. Selectively clamping the inputs of the first stage amplifier to a predetermined potential allows the first stage amplifier to accurately amplify the low level input signals due to the fact that the threshold voltage of the first stage amplifier cannot vary from the predetermined potential.

Abstract: A method and apparatus is disclosed for a fast switching digital differential amplifier system useful in regenerating information signals in charge coupled devices. The amplifier system has a first capacitance at an input point which is charged and discharged in accordance with a binary "0" or binary "1" at the input. A second capacitance and an output capacitance is provided with a predetermined charge thereon. In the event of a binary "1", the predetermined charge on the second and output capacitance is retained while the first capacitance is discharged. In the event of a binary "0", the second and output capacitances are discharged via a current sink. A flip-flop is connected to the output capacitance for accelerating the discharge of the same. Switching transistors are additionally provided for activating the flip-flop to achieve the desired fast-switching.

Abstract: A function generator is connected to a node formed by the source electrodes of the switching transistors of flip-flops in which the flip-flops are each composed of two circuit arms. Each of the circuit arms has a load transistor and a switching transistor, constructed as MOS transistors, for the amplification of read-out signals supplied by a MOS memory. Each flip-flop is connected at the connection points of the load transistors and switching transistors to a sub-portion of a bit line of the MOS memory. The curve of the voltage supplied to the node is such that, at the beginning of a cycle of the read-out process, the node is charged, and for the evaluation of the read-out signals on the bit lines the node is discharged in a controlled manner such that the flip-flops trigger into a state governed by the read-out signal on the bit lines.

Abstract: A read-out amplifier circuit for a dynamic MOS memory has two arms each of which includes a switching transistor and a load transistor connected in series, the arms being connected in parallel with a feedback connection between the junction of a switching transistor and a load transistor and the control electrode of the switching transistor of the other arm. The junctions of the switching transistors and load transistors are connected to respective sub-portions of a bit line and are also connected by way of a balance transistor. The source electrodes of the switching transistors are connected to a node which is charged prior to the beginning of a reading cycle and, for evaluating a read-out signal, is discharged in a controlled manner such that the switching transistor whose drain electrode is subjected to the voltage change which gives rise to the read-out signal is rendered conductive.

Abstract: A nonvolatile (MNOS) memory array using varactor boosted select signals is disclosed. The memory utilizes a varactor circuit to boost the row select during the erase and write modes of operation.

Abstract: An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (first level) flows from the load elements to the internal cell nodes in the stand-by mode. During the initial portion of a read cycle, current flows from the bit lines to the cell nodes, in addition to the stand-by current (second level). In the recovery period of the read cycle or write cycle a short pulse is added to the stand-by current (third level), thereby reducing the recovery time. The practice of the invention provides a monolithic memory having minimal power requirements and a substantially reduced cycle time.