Abstract: A voltage booster circuit includes a driver circuit (117) for generating a 3-state output for driving wordlines via row decoder circuits in an array of flash EEPROM memory cells during read and programming modes of operation. The driver circuit effectively disconnects a large booster capacitor (115) in order to allow a small charge pump (114) to further pump up the wordline voltage during programming. As a result, the booster pump has improved efficiency since there is achieved a significant reduction in power consumption.

Abstract: An internal voltage boosting circuit for a semiconductor memory device comprises first and second boosted voltage generators for boosting an internal voltage of said memory device. A voltage level detector is operative to detect the internal voltage. A first logic circuit is operatively connected to the first generator and to the voltage level detector. The logic circuit activates the first generator when (a) the detected voltage falls below a predetermined voltage and (b) the memory device is in an active state. A second logic circuit is operatively connected to the second generator. The second logic circuit activates the second generator when said memory device is in a precharge state.

Abstract: An improved self-restore circuit and method for restoring the output line of a dynamic logic circuit. The self-restore circuit includes two transistors connected in series between the output line and the reference voltage node. The first transistor activates after an evaluation of the output line, while the second transistor only activates subsequent to the activation of the first transistor and the completion of an evaluation cycle. The self-restore circuit reduces the power consumption and safeguards against any soft error hits, wherein the second transistor protects against any soft error hits by actively pulling up the output line to the appropriate voltage.

Abstract: A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure, The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

Abstract: A semiconductor memory device includes a memory cell array composed of a plurality of memory cells arranged in a matrix manner and at least one reference memory cell, wherein a plurality of digit lines are respectively connected to columns of memory cells, a plurality of word lines are respectively connected to rows of memory cells, and a reference digit line is connected to the reference memory cell, an address circuit for selecting one of the plurality of digit lines and one of the plurality of word lines in response to input of an address to select one of the plurality of memory cells, a sense amplifier connected to the plurality of digit lines and the reference digit line, for sensing data which has been stored in the selected memory cell in response to a first portion of a sense control signal, a discharging circuit for discharging charge of at least one of the plurality of digit lines which is connected to the selected memory cell and charge of the reference digit line in response to a second portion of

Abstract: The present invention provides an SRAM device comprising a first discharger for discharging a first bit line at the write operation when the first bit line is at a low level; a second discharger for discharging a second bit line at the write operation when the second bit line is at a low level; and a pull-up transistor for providing power with the first and second bit lines at the read operation and preventing the power supply from being provided with the first and second bit lines at the write operation, whereby the first or second dischargers converts the voltage level in low level bit line into a ground level when the write operation is performed.

Abstract: A semiconductor memory device includes a bit line, a memory cell, and a precharge circuit responsive to a precharge signal for charging the bit line. The precharge circuit is enabled before cell data is read from the memory cell via the precharged bit line. The memory device further includes a potential controller responsive to the precharge signal for regulating the charge applied to the bit line by the precharge circuit. A charge supplying circuit is coupled to the bit line, and maintains the bit line potential at a predetermined voltage level by providing the bit line with charges during a period from when the precharge circuit completes its precharge operation to when the bit line potential changes in response to reading data from the memory cell.

Abstract: A system and method is disclosed for increasing read performance of domino SRAMS. A conventional word-line, which drives two transistors per cell, is replaced with two separate word-lines. The first word-line drives one transistor and the second word-line drives the other transistor. The first word-line is used to write zeros into cells, while the second word line is used to both write ones into cells and to read the contents of the cells. Since the second word-line drives only one transistor during read operations, one-half of the gate load on the writeead word-line is eliminated.

Abstract: After performing high speed sensing with shutting off digit line pair, in which digit line is connected to an objective memory cell for access, only the digit line which is connected to the memory cell is electrically connected to the sense amplifier to perform re-writing of information to the memory cell by the corresponding sense amplifier. In subsequent balancing and pre-charging process, pre-charging is performed after sufficient balance of potential is established in the digit line pairs. By this, no extra charging current will flow in the digit line and/or the pre-charging power source to reduce power consumption.

Abstract: Segment data line pairs connected to a bit line pair are separated into segment data line pair for reading, and segment data line pair for writing. Global data line pairs connected to segment data line pair are separated into global data line pair for reading and global data line pair for writing. Connection between bit line pair and segment data line pair for reading is provided through a first read amplifier, while segment data line pair for reading is connected to global data line pair for reading through a second read amplifier. The first read amplifier includes two MOS transistors connected in series between one of the segment data line pair for reading and the ground power supply, and two MOS transistors connected in series between the other one of the segment data line pair for reading and the ground power supply.

Abstract: A semiconductor memory device comprises a main bit line pair, a plurality of subbit line pairs, a plurality of selection transistor pairs, a plurality of word lines, a plurality of memory cells, and a plurality of first precharging circuits. The subbit line pairs are provided in correspondence to the main bit line pair. One and other subbit lines of the subbit line pairs are arranged in straight lines along the main bit line pair. The selection transistors are provided in correspondence to the subbit line pairs. Each of the selection transistor pairs is connected between the main bit line pair and the corresponding subbit line pair, and turned on in response to a prescribed selection signal. The word lines are arranged to intersect with one and the other subbit lines of the subbit line pairs. The memory cells are provided in correspondence to intersection points between one and the other subbit lines of the subbit line pairs and the word lines.

Abstract: A static type of semiconductor memory device includes a power supply line for supplying a power supply voltage, a pair of bit lines, a word line, and a memory cell connected to the word line and the pair of bit lines. The power supply voltage is boosted up to provide the boosted voltage on a boosted voltage line. A predetermined voltage is supplied to the word line using the boosted voltage and a write operation or read operation is performed to the memory cell via the pair of bit lines when the predetermined voltage is supplied on the word line. The predetermined voltage is approximately equal to a sum of the power supply voltage and a threshold voltage of a MOS transistor, resulting in a great low voltage operation margin.

Abstract: A data storage device is provided. The data storage device, which is coupled to a data processing device, includes a memory array partitioning into a plurality of memory banks. The data storage device further includes a bank enable circuit for enabling at least one of the memory banks from the plurality of memory banks of the memory array. The data storage device also includes an operation/pseudooperation enable circuit (OPEC) for generating an operation or a pseudooperation signal to one or more banks enabled by the bank enable circuit. The OPEC has a first input for receiving an operation request signal from the data processing device and a second input. Additionally the data storage device includes a pseudooperation control circuit for controllably generating a pseudooperation request signal to the bank enable circuit and to the second input of the OPEC.

Abstract: A voltage boost circuit is provided which supplies a gate voltage to an insulated gate transistor. The voltage boost circuit has a voltage supply circuit, a supply line for connection to the gate of the insulated gate transistor and connected to the voltage supply circuit for precharge, a boost precharge circuit connected to the supply line and a capacitive element for boosting the voltage on the supply line. The circuit also has a facility for resetting the voltage on the supply line to its initial value after operation of the boost circuit.A memory array including such a voltage boost circuit is also provided, together with a method of boosting a gate voltage for insulating gate transistors in a memory array.

Abstract: An apparatus and method for managing a memory is disclosed. A discharging unit discharges overcharged bit lines in memory. The discharging unit discharges the bit lines after a predetermined time after the last memory access. The discharging unit also discharges the bit lines after a microprocessor comes out of a low power mode.

Abstract: There is provided a method of controlling data transmission lines of a semiconductor memory device which has a first pair of data transmission lines to which a sense amplifier and memory cells are connected, and a second pair of data transmission lines to which a read circuit and a write circuit are connected at an end of the second pair of the data transmission lines, which is connected to the first pair of data transmission lines via a column gate. The method includes a) shortcircuiting the second pair of data transmission lines for a first period when a read operation is carried out, and b) shortcircuiting the second pair of data transmission lines for a second period when a write operation is carried out, the second period being shorter than the first period.

Abstract: A fast memory system including one or more asymmetrical sense amplifiers precharged to a first logic state and optimized to slew very fast towards the first logic state. Each sense amplifier is coupled to a corresponding pair of complementary bit lines, which are preferably precharged. When enabled, each sense amplifier tends towards an opposite, default logic state opposite the first logic state when sensing the precharged bit lines. Control logic enables a corresponding precharge amplifier to precharge the bit lines, and then enables the sense amplifier after the assertion of a clock signal. Also, the control logic enables a corresponding pull-up device to precharge the output of each sense amplifier. Thus, the sense amplifier begins in the first, precharged logic state and slews towards the opposite, default logic state. The control logic then asserts a word line select signal to a corresponding memory cell, which drives a voltage differential on the bit lines to assert a data bit.

Abstract: A refresh method of reusing electric charges from a refresh operation of a first memory array for pre-charging in an initial refresh operation of a second memory array in which charges that are charged/discharged to a bit line and its complementary bit line of one memory array via switching units provided between the one memory array and another memory array when performing a refresh operation in the one memory array are also used for performing an initial refresh operation of the other memory array, thereby reducing back-up currents by reducing refresh currents, and prolonging the life of dry cells or batteries for hours.

Abstract: A word line decoder gate including a plurality of parallel-coupled devices coupled to a common node for receiving and decoding an address upon assertion of a clock signal, where each parallel device receives a corresponding address signal or its inverted counterpart depending upon the particular address being decoded. A precharge device is coupled to the common node for keeping it at a first voltage level until the clock signal is asserted, and two series coupled charge devices are coupled between a source voltage and the common node, which charge devices attempt to charge the common node to a second voltage level during a time period while the clock signal is asserted and a delayed clock signal remains deasserted. A delay device receives the clock signal and asserts the delayed clock signal. However, any one or more of the parallel devices, if activated, provides a current path from said common node to override the two charge devices to keep the common node substantially at the first voltage level.

Abstract: An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods.

Abstract: The voltage boosting circuit of the present invention includes a voltage converting circuit connected between an oscillator and a pair of pumping capacitors. The pair of pumping capacitors are then connected to a single transmission transistor, which outputs a boosted voltage that is derived from the combination of a precharge voltage placed on the source of the transmission transistor and the voltage stored on the pumping capacitors. The presence of the voltage converting circuit, which uses cross-connected PMOS transistors coupled to ground through a pair of NMOS transistors and establishes a differential amplifier, substantially eliminates the body effect problems that would otherwise occur.

Abstract: A semiconductor memory has memory cells for data storage, connected to bit line pair a memory cell selection decoder for selecting the memory cell in the plurality of memory cells corresponding to a bit line direction address, a bit line load circuit for supplying a voltage potential to the bit line pair, and an impedance control circuit for receiving the bit line direction address and changing an impedance of the bit line load circuit according to the bit line direction address. The semiconductor memory performs data write-in and data readout operations from/to the memory cell in the plurality of memory cells selected by the memory cell selection decoder through the bit line pair.

Abstract: A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

Abstract: A reference cell for a IT-1C memory can be used in either an open or folded memory cell array. Each reference cell has two outputs each coupled to a bit line that each develop a voltage substantially half of that developed by a ferroelectric memory cell. The reference voltages and memory cell voltage are than resolved by a sense amplifier. Each reference cell includes two ferroelectric capacitors that are the same size and fabricated with the identical process as the memory cell ferroelectric capacitors. Any changes in the memory cell capacitor similarly affects the reference cell capacitor, and thus the reference voltage is always substantially half of that developed by the memory cell. The reference cells include a number of timing inputs, which control charge sharing and configure the cell to operate in either a DRAM or FRAM.RTM. mode. In a first embodiment, one of the reference cell capacitors is poled.

Abstract: A test circuit and method for testing a memory cell in a static random access memory. The memory cell is coupled to a bit line and a complementary bit line. The test circuit includes a charging device coupled to selectively charge one of the bit line or the complementary bit line and a discharging device coupled to selectively discharge the other of the bit line and the complementary bit line. To test a memory cell containing the first value, the test circuit performs a weak write of the second value to the memory cell. The weak write overwrites the first value contained in the memory cell with the second value if the memory cell is defective. The memory cell retains the first value if functioning properly.

Abstract: A memory element for a static random access memory which comprises a bit line and a bit line for providing a voltage on one of the lines indicative of a binary "1" or a "0" and the other of a "1" or a "0" on the other line. A sense amplifier is coupled to the bit and bit lines, the sense amplifier including a first switch coupled to the bit line and a second switch coupled to the bit line. The element also includes circuitry associated with the bit line and responsive to a select signal to indicate the voltage level of the bit line and to indicate the voltage level of the bit line. The first and second switches are responsive to the circuitry to turn off one of said first and second switches and turn on the other of said first and second switches when the difference in voltage level on the bit and bit lines is in one direction and to turn off and on the other of the switches when the difference in voltage level on the bit and bit lines is in the opposite direction.

Abstract: A random-access memory with an accelerated access time. One or more of the preliminary operations of the sequence of operations carried out for accessing the memory are anticipated by performing the anticipated operation or operations during the end of a sequence of a previous memory access. The anticipated operation is preferably that of the deselection of the bit lines of the memory.

Abstract: An integrated circuit has a built-in EEPROM which utilizes a high voltage to write or erase data. The integrated circuit operates with a lower power supply voltage. Switches supply a high voltage to bit lines, control gate lines, and word lines. Each switch includes a multi-stage charge pump comprising diode-connected transistors and capacitors. The switch has an enhanced charge capability and can transfer a high voltage from a low power supply voltage. Thus, the switch can operate successfully with a low power supply voltage.

Abstract: A synchronous sense amplifier stage includes means for shunting the signal input terminal of the sense amplifier stage to ground during a precharge interval for discharging charge on a read bit line connected to the input terminal of the synchronous sense amplifier during the precharge interval. Means are also provided for precharging predetermined internal nodes and the output terminal of the synchronous sense amplifier stage to predetermined voltages during the precharge interval.

Abstract: A semiconductor memory has a sense amplifier array shared by first and second memory cell arrays, which are selected by first and second selection signals. Interconnections between the sense amplifier array and the first memory cell array are controlled by a first transfer gate signal. When the first selection signal is inactive, the second selection signal is coupled through a first transfer gate driver to become the first transfer gate signal. When the first selection signal is active, the first transfer gate signal is decoupled from the second selection signal and driven to an elevated level.

Abstract: A voltage boosting circuit for boosting a supply voltage VCC supplied from a system to a desired boosting voltage VPP level. The voltage boosting circuit includes a transmission transistor formed by a triple-well process. The transmission transistor has bipolar characteristics and operates as a bipolar diode.

Abstract: A discharging circuit for bit lines for compensating for the effect of subthreshold leakage in pull-up transistors. The bit lines are periodically discharged to a level approximately equal to the level that the bit lines would be at if no leakage occurred. In this way, the discharging can occur even during an active memory cycle. The discharging occurs infrequently, for example, once every 512 memory cycles.

Abstract: There is provided a memory array including columns of memory cells, source lines and bit lines. The memory array includes precharging apparatus which discharge selected source lines while pre-charging the array. Two embodiments of the pre-charging apparatus are provided. In both, the source lines are connected to a common bit line (CNBL) via groups of source pull-up transistors. The source lines are also connected to a source decoder. In one embodiment, the source decoder discharges selected ones of the disconnected source lines. In another embodiment, the source decoder both discharges selected ones of the disconnected source lines and connects the remaining disconnected source lines to the CNBL line.

Abstract: A circuit and method for minimizing write recovery time in a Bi-CMOS SRAM by equalizing the bit-line voltages during a read access. A P-channel device whose drain, source and gate are connected to bit, bit-bar, and the write control signal, respectively, indirectly equalizes the bit-lines by equalizing the base voltages of the NPN bit-line load devices only when the column is selected for read access. This technique takes advantage of the current gain of the NPN transistor from the base to the emitter to provide fast bit-line equalization immediately following writes, thus minimizing the write recovery time.

Abstract: A word line loading compensating circuit compensates a word line boosted voltage level changed in accordance with a word line loading. A word line boosting circuit outputs a word line boosted voltage boosted over a power supply voltage input from the exterior of a chip, so as to boost a voltage of the word line connected to the memory cell array. A row decoder is connected to the word line boosted voltage output from the word line boosting circuit and selects a memory cell from an array of memory cells in correspondence with a predetermined row address signal. A capacitor connected between the word line boosted voltage and the row decoder stores a charge from the word line boosted voltage. A variable connecting device connects the word line boosted voltage to the capacitor before the word line boosted voltage reaches a saturation level, and cuts off the word line boosted voltage from the capacitor after the word line boosted voltage reaches the saturation level.

Abstract: A sense amplifier circuit includes a differential input circuit which receives first and second data inputs, din1and din2, and generates, in response to a first control signal .PHI..sub.1 being active LOW, a differential voltage across first and second nodes, which is indicative of a voltage difference between the first and second data inputs, din1 and din2; a pull-up circuit which connects, in response to a second control signal .PHI..sub.2 being active LOW, a high voltage reference Vdd to both the first and second nodes; a latching circuit which generates and latches, in response to voltages provided on the first and second nodes by the differential input and pull-up circuits, first and second latched data outputs; and an equalization circuit which equalizes, in response to a third control signal .PHI..sub.0 being active LOW, voltages on data lines respectively connected to the first and second data outputs. Timing of the first and second control signals, .PHI..sub.1 and .PHI..sub.

Abstract: A nonvolatile semiconductor memory apparatus of the present invention has a feature that charging of a control gate of a nonselective memory cell is simultaneously executed upon charging of a bit line. That is, in the case of normal reading (random accessing), charging of the control gate of the nonselective memory cell is conducted previously to at least one of source and drain side selective gates. Then, when the threshold value of the memory cell in the case of erasing the cell is judged, in a read mode, charging of the selective gate is started by delaying from the timing of charging the control gate of the nonselective memory cell to negative. That is, the selective gate is closed until the control gate is completely set to a negative testing voltage to prevent the bit line from being discharged. After the control gate is completely set to the negative testing voltage, the selective gate is delayed to be charged so that the selective gate is turned ON.

Abstract: A column selector of a dynamic random access memory device is implemented by a plurality of switching circuits for transferring a potential difference from a sense amplifier to a shared data line pair, and one of the switching circuits selectively discharge the data lines of the pair to a ground voltage line for transferring the potential difference to the shared data line pair, wherein a potential control circuit is coupled between the switching circuits and the ground voltage line for decreasing the current flowing from the data line to the ground voltage line after production of an output data signal, thereby decreasing the current consumption.

Abstract: A non-volatile semiconductor memory device includes read charging transistors for setting bit lines at a predetermined read potential to perform a data read operation, and read discharging transistors for setting non-selected bit lines at the ground potential during the read operation. These transistors are controlled by different control signals, obtained by detecting an address change, for every other bit line in accordance with an input address so that the read discharging transistors are kept ON to set the non-selected bit lines at the ground potential before and during the data read operation.

Abstract: There is disclosed an associative memory capable of reducing electricity to be consumed. Prior to a retrieval, a number of match lines, which associate with a number of word memories, respectively, are precharged. In the retrieval, among the multiple match lines which are subjected to the precharge, the match line associated with the word memory which stores a bit pattern equivalent to that for the retrieval is discharged.

Abstract: In the memory cell provided with spare cells and normal cells, the time required to discriminate the spare column address from the normal column address or vice versa can be reduced, and thereby a high speed memory access can be realized. When an address is given from the counter to a memory circuit having the spare address and the normal address, before the counter outputs an address to the memory circuit, the spare/normal discriminating circuit acquires previously the address outputted from the counter and discriminates whether the address is the spare address or the normal address. On the basis of this discrimination, the select circuits switch the address to be applied from the select circuits to the memory circuit from the normal address to the spare address or vice versa.

Abstract: A precharge circuit for adjusting and maintaining a bitline of a ROM to a pre-determined precharge voltage. The circuit is comprised of P-channel pull-up transistors for initially placing an input line and a node of the precharge circuit at the supply voltage. A relatively small transistor is coupled to the node. Its function is to pull the node's voltage down when a control signal is activated. A larger transistor is also coupled to the node. The larger transistor is used to compensate for the pull down action of the small transistor. The relative sizes of the small transistor versus the larger transistor is made such that the node is placed at the desired quiescent level. The node is maintained at this level until the wordline is activated and the programmed bitline begins discharging. When discharging of the bitline causes the node's voltage to fall below a given threshold voltage through the source follower action of the large transistor, the output from the circuit is pulled down hard to a ground level.

Abstract: A semiconductor storage device having a word-line voltage booster circuit includes: a plurality of word-lines connected to each memory cell array; a drive signal generation circuit for producing a word-line drive signal having a voltage higher than a power supply voltage; a decoder circuit for transmitting the word-line drive signal produced by the drive signal generation circuit, when the drive signal generation circuit is selected by an address signal; and a charging circuit connected to a signal path which transmits the word-line drive signal from the drive signal generation circuit to the decoder circuit. The charging circuit charges the signal path before the word-line drive signal is output to the signal path.

Abstract: An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase pulse signal (ERPULSE) into a pulse control signal (ERPCL) that is subsequently translated into a higher voltage level bias signal (ECL.sub.--). The higher voltage level bias signal (ECL.sub.--) drives array source signal generator circuits (16) that produce array source signals (AS) to erase particular array subsections of memory as determined by a selection circuit (17). The array source signal generator circuits (16) also generate array source command signals (ASCOM.sub.--) to indicate a discharging status of all array source signals (AS). An erase completion detector circuit (18) monitors the array source command signals (ASCOM.sub.--) and generates an array source detect signal (ASDET) to indicate completion of array source signal (AS) discharging.

Abstract: A high-speed decoder for salvaging defective memory cells which has voltage generators VG0 and VG3 for generating voltages having binary logic levels corresponding to the bit information of each column of the addresses of defective memory cells. Upon input of a memory address signal, the voltage level of the bits of each column of the address signal are checked against the voltage levels corresponding to each column from the voltage generator. When all of the columns agree, an address agreement signal is generated by an address corroboration circuit including exclusive OR gates EX0 to EX3 and a NAND gate 10.

Abstract: In a semiconductor static RAM which includes at least one static RAM memory cell connected to a pair of complementary bit lines and each connected to a different word line. A bit line load circuit is connected between the pair of complementary bit lines and a voltage supply potential, and a column selection circuit is connected between the pair of complementary bit lines and a pair of complementary common data bus lines coupled to an input/output data control circuit. The bit line load circuit includes a pair of precharge P-channel insulated gate field effect transistors connected between the voltage supply potential and the pair of complementary bit lines. A bit line equalizing P-channel insulated gate field effect transistor is connected between the pair of complementary bit lines. A gate of each of these P-channel transistors is connected to receive the same internal precharge signal.

Abstract: A bit line load (380) is coupled to a bit line pair and includes bipolar pull up transistors (389, 403), P-channel load transistors (390, 404), a NAND logic gate (395), and a P-channel equalization transistor. The NAND logic gate (395) senses a differential voltage on the bit line pair, and provides an equalization signal. When a write control signal indicates the end of a write cycle, the equalization signal initiates precharge and equalization of the bit line pair.

Abstract: A dynamic random access memory device is equipped with sense amplifier circuits for developing differential voltage levels on associated bit line pairs, and the sense amplifier circuits are coupled through a discharging path with a ground voltage line, wherein the discharging path is implemented by a plurality of discharging sub-paths sequentially grounded by a control circuit so that the differential voltage levels are rapidly developed by smooth voltage decay on the associated discharging sub-paths, thereby improving the data access time.

Abstract: An integrated circuit memory array includes column conductors that are precharged during a precharge period in order to reduce the effects of power supply voltage variations, a load resistor is connected between the column conductors and ground during a portion of the precharge period. In this manner, a voltage-divider is formed that provides a discharge path which prevents over-charging of the column conductors. An increase in power supply noise immunity is gained, thereby avoiding degradation of the worst-case memory access time that could otherwise occurs.

Abstract: A precharge transistor precharges a bus. A discharge transistor discharges the bus. A push-pull driver is connected to the bus, and consists of a p-channel MOS transistor and an n-channel MOS transistor. The push-pull driver sets the potential of the bus to "H" level or "L" level. A detection circuit detects which one of the discharge transistor and the push-pull driver is being driven. When the push-pull drive is being driven, a control circuit renders the precharge transistor inoperative.