Abstract: A system and method for bidirectionally based electrical information storage, processing and communication. Bidirectional memory (tristate) offers the capability to store and interpret multiple bits (Shannon's) of information per memory cell, for structures such as dynamic random-access memory (DRAM), and read-only memory (ROM), and communication circuits, for operation, rather than traditional memory able to store a single “bit” (Shannon) of information per cell. Where, instead of traditional memory cells capable of two possible states (binary digit) and a single defined bit (1 Shannon), bidirectional memory is capable of three states (tristate), where the third information representing state can be a specifically defined state capable of representing multiple bits (multiple Shannon's) for each individual cell, which may be defined to represent a specific sequence of bits (sequence of Shannon's).

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: A method of programming a ferroelectric memory device is disclosed. The method includes applying a first voltage to a first word line; applying a second voltage to the first word line; and applying a pass voltage to a second word line during a period of applying the first voltage to the first word line and during a period of applying the second voltage to the first word line. The pass voltage is between the first threshold voltage and the second threshold voltage.

Abstract: A memory cell includes a memory circuit and a multiplier circuit. The multiplier circuit includes an output node configured to output the output signal, a first transistor and an initialization circuit. The first transistor is coupled to the output node and the memory circuit, and is configured to receive at least the second signal. The initialization circuit is coupled to the first transistor by the output node, and is configured to initialize the multiplier circuit in response to at least a third signal or a fourth signal. The memory circuit is configured to store a first value of a first signal of a first storage node. The multiplier circuit is coupled to the memory circuit. The multiplier circuit is configured to generate an output signal in response to the first signal and a second signal. The output signal corresponds to a product of the first signal and the second signal.

Abstract: A circuit includes a control circuit having a first control circuit input, a second control circuit input, a first control circuit output, and a second control circuit output, and a first transistor having a first current terminal, a second current terminal, and a control terminal, the control terminal coupled to the first control circuit output, the first current terminal coupled to the first control circuit input and to a second transistor, and the second current terminal adapted to be coupled to the second transistor, a logic circuit having a first logic input, a second logic input, and a logic output, the first logic input coupled to the second control circuit output and a switch having a first switch terminal, a second switch terminal, and a switch control terminal, the switch control terminal coupled to the logic output and the first switch terminal coupled to the second current terminal.

Abstract: A semiconductor memory device according to the present invention has a memory cell array, a write-driving/bias-reading circuit, a control circuit and a sense amplifier. The control circuit outputs a VSLC (Verify Sense Load Control) signal generated according to writing data. After the write-driving/bias-reading circuit applied the writing pulse and the complementary writing pulse, the sense amplifier receives the VSLC signal and detects the current difference between two currents respectively flowing through a first data line and a second data line; the first data line and the second data line respectively connecting a true memory cell and a complementary memory cell of the selected pair of memory cell. The control circuit controls to provide the additional current to at least one of the first data line and the second data line so as to make the detected current difference meet the required margin.

Abstract: The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

Abstract: An image capturing and display apparatus includes a plurality of image capturing units, a plurality of display units, and a signal processing unit. The plurality of image capturing units includes a first image capturing unit and a second image capturing unit configured to output a signal corresponding to an incident light quantity higher than that of the first image capturing unit. The signal processing unit generates a single third image signal based on a first image signal from the first image capturing unit and a second image signal from the second image capturing unit, and the plurality of display devices displays images based on the third image signal.

Abstract: This document describes apparatuses and techniques for multi-rail power transition. In various aspects, a power rail controller transitions a memory circuit (e.g., of a memory die) from a first power rail to a second power rail. The power rail controller then changes a voltage of the first power rail from a first voltage to a second voltage. The power rail controller may also adjust termination impedance or a clock frequency of the memory circuit before transitioning the memory circuit to the second power rail. The power rail controller then transitions the memory circuit from the second power rail to the first power rail to enable operation of the memory circuit at the second voltage. By so doing, the power rail controller may improve the reliability of memory operations when transitioning operation of the memory circuit from the first voltage to the second voltage.

Abstract: Provided are a sense amplifying circuit and method, and a semiconductor memory. The sense amplifying circuit includes: a transmission circuit, configured to receive a signal to be processed and perform transmission on the signal to be processed to obtain an initial transmission signal; and an amplifying circuit, configured to receive a first control signal and the signal to be processed, and perform amplification on the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal.

Abstract: A memory and a sense amplifying device are provided. The sense amplifying device includes a differential amplifier, a first pre-charge circuit, and a control voltage generator. The differential amplifier has a first input terminal and a second input terminal to receive a data signal and a reference signal, respectively. The first pre-charge circuit is coupled to the first input terminal of the differential amplifier. The first pre-charge circuit, based on a power voltage, performs a pre-charge operation on the first input terminal of the differential amplifier according to a pre-charge enable signal and a control voltage. The control voltage generator generates the control voltage according to the power voltage, and the control voltage and the power voltage are in a positive correlation.

Abstract: A bit line sense amplifier includes a first inverter having an output terminal connected to a complementary sensing bit line, a second inverter having an output terminal connected to a sensing bit line, a first offset element connecting a bit line to the complementary sensing bit line and a second offset element connecting a complementary bit line to the sensing bit line, in response to an offset cancellation signal. During a first time interval, the first offset element and the second offset element are turned off and a capacitor of a first memory cell is connected to the bit line. During a second time interval after the first time interval, the first offset element and the second offset element are turned on and the capacitor of the first memory cell is disconnected from the bit line.

Abstract: In a memory device, pages are arrayed in a column direction on a substrate, each page constituted by memory cells arrayed in row direction on a substrate. Each memory cell includes a zonal P layer. N+ layers continuous with a source line and a bit line respectively are on both sides of the P layer. Gate insulating layers surround part of the P layer continuous with the N+ layer and part of the P layer continuous with the N+ layer, respectively. One side surface of the gate insulating layer is covered with a gate conductor layer continuous with a first plate line, and the other side surface is covered with a gate conductor layer continuous with a second plate line. A gate conductor layer continuous with a word line surrounds the gate insulating layer.

Abstract: A low voltage one-time-programmable memory includes a first conductive layer, a first via, a second conductive layer, a select transistor, a second via and a third conductive layer. The first via is electrically connected to the first conductive layer. The second conductive layer is electrically connected to the first via. The select transistor is electrically connected to the second conductive layer. The second via is electrically connected to the second conductive layer. The third conductive layer is electrically connected to the second via. A first current passed through the second via is a sum of a second current passed through the first via and a third current passed through the select transistor.

Abstract: A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

Abstract: A first transistor is coupled to a capacitor. A first inverter circuit is coupled between first and second nodes, and includes a p-type second transistor and an n-type third transistor coupled at a third node. A second inverter circuit is coupled between the first and second nodes, and includes a p-type fourth transistor and an n-type fifth transistor coupled at a fourth node. A sixth transistor is coupled between gates of the fourth and fifth transistors, and the third node. A seventh transistor is coupled between gates of the second and third transistors, and the fourth node. An eighth transistor is coupled between the gate of the second transistor and the third node. A ninth transistor is coupled between the gate of the fourth transistor and the fourth node.

Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.

Abstract: This document discloses a solution for controlling refreshing of memory resources of a dynamic random access memory. According to an aspect, there is disclosed an apparatus for a radio device, comprising: a dynamic random access memory circuit; a memory allocator configured to allocate memory resources from the dynamic random access memory circuit and to determine unallocated memory resources; a radio modem configured to communicate with the memory allocator in order to gain memory resources from the dynamic random access memory circuit; a memory refresh circuit configured to refresh the memory resources of the dynamic random access memory circuit; and a controller configured to determine, on the basis of a state change signal received from a radio modem of the radio device, that the radio modem is in an idle state and, in response to said determining, to control the memory refresh circuit to disable said refresh of the unallocated memory resources.

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

Abstract: A command decoder circuit, a memory, and an electronic device are provided. The circuit includes a first decoder unit, configured to perform decoding for a first command signal based on a dynamic clock signal; a second decoder unit, configured to perform decoding for a second command signal based on the dynamic clock signal; and the clock gate, configured to generate the dynamic clock signal after a chip select signal of the first decoder unit indicates that decoding to be started for the first command signal and before the second decoder unit has performed decoding for the second command signal, and cut off the dynamic clock signal before the chip select signal of the first decoder unit indicates that the decoding to be started for the first command signal or after the second decoder unit has performed decoding for the second command signal.

Abstract: In certain aspects, a comparator includes an input stage and a regeneration stage. The input stage includes a first input circuit coupled to a first node and a second node, a first switching transistor configured to enable the first input circuit if a previous bit value is one, a second input circuit coupled to the first node and the second node, and a second switching transistor configured to enable the second input circuit if the previous bit value is zero. The regeneration stage includes a first inverter, a second inverter cross coupled with the first inverter, a first drive transistor coupled to the first inverter, wherein a gate of the first drive transistor is coupled to the second node, and a second drive transistor coupled to the second inverter, wherein a gate of the second drive transistor is coupled to the first node.

Abstract: A method for accessing memory and a memory device using the same method are provided. The method includes: coupling, by a first sense amplifier (SA) of a memory, to a memory cell of the memory to receive data from the memory cell; coupling a first terminal of a transistor of the memory to the first SA; coupling a first command terminal of a system on chip (SoC) to a second terminal of the transistor, and coupling a first input/output (I/O) terminal of the SoC to a third terminal of the transistor; and issuing, by the SoC, an access command to the second terminal of the transistor to access the data output by the first SA through the third terminal of the transistor.

Abstract: The sense amplifier includes: an amplification module configured to amplify a voltage transmitted by a bit line or a reference bit line, when the sense amplifier is at an amplification stage; a first switch module configured to control the amplification module to be disconnected from the reference bit line, when the sense amplifier performs a read operation for the bit line and is at the amplification stage. In the disclosure, the power consumption of the sense amplifier may be reduced.

Abstract: An efficient, high density, inline converter module includes a power conversion circuit and an input wiring harness for connecting the input of the power circuit to a unipolar source. A second wiring harness or electrical connectors may be provided for connecting the output of the power conversion circuit to a load. Connections between a wiring harness and the power conversion circuit may comprise conductive contacts, configured to distribute heat. The power circuit may be over molded to provide electrical insulation and efficient heat transfer to external ambient air. A DC transformer based inline converter module may be used in AC adapter, vehicular, and power system architectures. An input connector for connecting the input wiring harness to the input source may be provided. In some embodiments the input source may be an AC source and the input connector may comprise a rectifier for delivering a rectified, unipolar, voltage to the input of the power conversion assembly via an input wiring harness.

Abstract: A semiconductor memory device includes first and second memory cell arrays spaced apart from each other in a first direction, a plurality of column selection transistors in a second direction which intersects the first direction, between the first and second memory cell arrays, at least two of the column selection transistors include respective portions of a central gate pattern, which intersects a central line extending in the first direction at a center of the first memory cell array and has a closed loop shape, and first and second local input/output lines configured to provide electric potential through the first memory cell array to a local sense amplifier based on operations of the column selection transistors. The first and second local input/output lines are electrically connected to the central gate pattern, and the center line is spaced apart from and does not intersect the first and second local input/output lines.

Abstract: A sense amplifier includes a first switch unit, a second switch unit, and an amplifier-latch module. A first port of the amplifier-latch module is electrically connected, via the first switch unit, to a bit line connected with a storage unit, and a second port of the amplifier-latch module is electrically connected to a reference voltage signal via the second switch unit. The amplifier-latch module is configured to amplify a signal in a sensing amplification phase. The first switch unit is configured to transmit a voltage on the bit line to the first port before the sensing amplification phase. The second switch unit is configured to transmit the reference voltage signal to the second port before the sensing amplification phase, and disconnect an electrical connection between the reference voltage signal and the second port in the sensing amplification phase.

Abstract: A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, the package test, the module test or the mounting test is failed.

Abstract: Methods, systems, and devices for deck-level signal development cascodes are described. A memory device may include transistors that support both a signal development and decoding functionality. In a first operating condition (e.g., an open-circuit condition), a transistor may be operable to isolate first and second portions of an access line based on a first voltage applied to a gate of the transistor. In a second operating condition (e.g., a signal development condition), the transistor may be operable to couple the first and second portions of the access line and generate an access signal based on a second voltage applied to the gate of the transistor. In a third operating condition (e.g., a closed-circuit condition), the transistor may be operable to couple the first and second portions of the access line based on applying a third voltage greater than the second voltage to the gate of the transistor.

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.

Abstract: A sense amplifier includes a bit line sense amplifier including a first transistor and a second transistor spaced apart from each other in a first direction, a second conductive line configured to electrically connect the first transistor to the second transistor and extending in the first direction and a local sense amplifier configured to at least partially overlap the second conductive line and disposed between the first transistor and the second transistor.

Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.

Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.

Abstract: A comparator includes a second-stage circuit, a first input circuit, a second input circuit, a first cross-coupled circuit and a second cross-coupled circuit. The first input circuit is configured to generate a first data terminal voltage and a first reference terminal voltage. The first cross-coupled circuit is configured to perform mutual positive feedback on the first data terminal voltage and the first reference terminal voltage to generate a first differential signal. The second input circuit is configured to generate a second data terminal voltage and a second reference terminal voltage. The second cross-coupled circuit is configured to perform mutual positive feedback on the second data terminal voltage and the second reference terminal voltage to generate a second differential signal. The second-stage circuit is configured to amplify and latch the first differential signal or the second differential signal in a regeneration phase to output a comparison signal.

Abstract: A radio frequency (RF) summer circuit having a characteristic impedance Zo comprises first and second ports coupled by first and second resistances, respectively, to a junction. The circuit further comprises a series combination of a third resistance and a switch movable between open and closed positions and an amplifier having input and output terminals and operable in an off state and an on state wherein the series combination is coupled across the input and output terminals of the amplifier between the junction and a third port. The first resistance, second resistance, and the third resistance are all substantially equal to Z0/3. Further, when the switch is moved to the closed position and the amplifier is switched to the off state a passive mode of operation is implemented and when the switch is moved to the open position and the amplifier is switched to the on state an active mode of operation is implemented.

Abstract: A static random access memory (SRAM) system includes a plurality of SRAM storage cells, each of the plurality of SRAM storage cells coupled to a respective read bit line, and a dynamic keeper coupled to the read bit line. The dynamic keeper includes a first keeper to support a read operation at a first temperature range, and a second keeper to support the read operation at a second temperature range, and a temperature-sensitive control circuit to select the first keeper or the second keeper based on temperature.

Abstract: A method of encrypting data in a nonvolatile memory device (NVM) includes; programming data in selected memory cells, sensing the selected memory cells at a first time during a develop period to provide random data, sensing the selected memory cells at a second time during the develop period to provide main data, encrypting the main data using the random data to generate encrypted main data, and outputting the encrypted main data to an external circuit, wherein the randomness of the random data is based on a threshold voltage distribution of the selected memory cells.

Abstract: The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.

Abstract: Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell.

Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.

Abstract: A method and a display device are provided. The method includes: generating a plurality of timing control signals for controlling a plurality of LED driving circuits, wherein the plurality of timing control signals include a first timing control signal and a second timing control signal; allowing the first LED driving circuit to drive an Nth scan line of a first display region at a first driving timing through the first timing control signal; and allowing the second LED driving circuit to drive an Nth scan line of the second display region at a second driving timing that is different from the first driving timing through the second timing control signal.

Abstract: The embodiments of the present disclosure provide a gate driving circuit, a display device, and a display control method. The gate driving circuit includes: a first gate driving sub-circuit configured to output a scan signal and control the first display area to display according to the scan signal; a display area control unit having an input terminal configured to receive the scan signal output by the first gate driving sub-circuit, a control terminal configured to receive a split-screen control signal output by the split-screen control signal terminal, and an output terminal configured to output or not output the scan signal according to the split-screen control signal; and a second gate driving sub-circuit configured to control a display state of the second display area according to whether the scan signal is received or not.

Abstract: An efficient, high density, inline converter module includes a power conversion circuit and an input wiring harness for connecting the input of the power circuit to a unipolar source. A second wiring harness or electrical connectors may be provided for connecting the output of the power conversion circuit to a load. Connections between a wiring harness and the power conversion circuit may comprise conductive contacts, configured to distribute heat. The power circuit may be over molded to provide electrical insulation and efficient heat transfer to external ambient air. A DC transformer based inline converter module may be used in AC adapter, vehicular, and power system architectures. An input connector for connecting the input wiring harness to the input source may be provided. In some embodiments the input source may be an AC source and the input connector may comprise a rectifier for delivering a rectified, unipolar, voltage to the input of the power conversion assembly via an input wiring harness.

Abstract: A sense amplification device is provided. The sense amplification device includes a first sense amplifier, a second sense amplifier, and a third sense amplifier. An input terminal of the first sense amplifier is coupled to a first bit line. An input terminal of the second sense amplifier is coupled to a second bit line. The third sense amplifier has a differential input pair and a differential output pair, wherein a first input terminal of the differential input pair is coupled to an output terminal of the first sense amplifier, a second input terminal of the differential input pair is coupled to an output terminal of the second sense amplifier, a first output terminal of the differential output pair is coupled to the input terminal of the first sense amplifier, and a second output terminal of the differential output pair is coupled to the input terminal of the second sense amplifier.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.

Abstract: In one example, a fluid property sensor includes an electrical circuit assembly (ECA), an elongated circuit (EC), and an external interface. The EC is attached to the ECA and includes multiple point sensors distributed along a length of the EC. The external interface is electrically coupled to a proximal end of the EC. The EC and the external interface are packaged together with an encasement on both sides of the ECA to form the fluid property sensor.