Flip-flop Used For Sensing Patents (Class 365/205)
  • Patent number: 11495307
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Masato Dome, Kensuke Yamamoto, Masaru Koyanagi, Ryo Fukuda, Junya Matsuno, Kenro Kubota
  • Patent number: 11495174
    Abstract: A method and a display device are provided. The method includes: generating a plurality of timing control signals for controlling a plurality of LED driving circuits, wherein the plurality of timing control signals include a first timing control signal and a second timing control signal; allowing the first LED driving circuit to drive an Nth scan line of a first display region at a first driving timing through the first timing control signal; and allowing the second LED driving circuit to drive an Nth scan line of the second display region at a second driving timing that is different from the first driving timing through the second timing control signal.
    Type: Grant
    Filed: November 7, 2021
    Date of Patent: November 8, 2022
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Fu-Zhi Xiao, Ching-Wen Wang, Cheng-Che Tsai, Chao-Chen Huang
  • Patent number: 11482156
    Abstract: The embodiments of the present disclosure provide a gate driving circuit, a display device, and a display control method. The gate driving circuit includes: a first gate driving sub-circuit configured to output a scan signal and control the first display area to display according to the scan signal; a display area control unit having an input terminal configured to receive the scan signal output by the first gate driving sub-circuit, a control terminal configured to receive a split-screen control signal output by the split-screen control signal terminal, and an output terminal configured to output or not output the scan signal according to the split-screen control signal; and a second gate driving sub-circuit configured to control a display state of the second display area according to whether the scan signal is received or not.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: October 25, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Yao Huang, Weiyun Huang
  • Patent number: 11482943
    Abstract: An efficient, high density, inline converter module includes a power conversion circuit and an input wiring harness for connecting the input of the power circuit to a unipolar source. A second wiring harness or electrical connectors may be provided for connecting the output of the power conversion circuit to a load. Connections between a wiring harness and the power conversion circuit may comprise conductive contacts, configured to distribute heat. The power circuit may be over molded to provide electrical insulation and efficient heat transfer to external ambient air. A DC transformer based inline converter module may be used in AC adapter, vehicular, and power system architectures. An input connector for connecting the input wiring harness to the input source may be provided. In some embodiments the input source may be an AC source and the input connector may comprise a rectifier for delivering a rectified, unipolar, voltage to the input of the power conversion assembly via an input wiring harness.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: October 25, 2022
    Assignee: Vicor Corporation
    Inventors: Patrizio Vinciarelli, Andrew T. D'Amico
  • Patent number: 11404110
    Abstract: A sense amplification device is provided. The sense amplification device includes a first sense amplifier, a second sense amplifier, and a third sense amplifier. An input terminal of the first sense amplifier is coupled to a first bit line. An input terminal of the second sense amplifier is coupled to a second bit line. The third sense amplifier has a differential input pair and a differential output pair, wherein a first input terminal of the differential input pair is coupled to an output terminal of the first sense amplifier, a second input terminal of the differential input pair is coupled to an output terminal of the second sense amplifier, a first output terminal of the differential output pair is coupled to the input terminal of the first sense amplifier, and a second output terminal of the differential output pair is coupled to the input terminal of the second sense amplifier.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 2, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Takuya Kadowaki
  • Patent number: 11393545
    Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: July 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yoshihiko Kamata, Naofumi Abiko
  • Patent number: 11318750
    Abstract: In one example, a fluid property sensor includes an electrical circuit assembly (ECA), an elongated circuit (EC), and an external interface. The EC is attached to the ECA and includes multiple point sensors distributed along a length of the EC. The external interface is electrically coupled to a proximal end of the EC. The EC and the external interface are packaged together with an encasement on both sides of the ECA to form the fluid property sensor.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: May 3, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, Michael W Cumbie, Anthony D. Studer
  • Patent number: 11315632
    Abstract: Disclosed is a memory drive device. The memory drive device comprises a control circuit, a reference voltage generation circuit, and a first switch. The control circuit is used to generate a first signal according to an input signal. The reference voltage generation circuit comprises a reference resistor and is used to generate a reference signal according to the first signal. The first switch is coupled to a memory resistor and is used to generate a drive signal according to the first signal so as to set a resistance value of the memory resistor. When the input signal is decreased and a resistance value of the memory resistor is greater than a resistance value of the reference resistor, the time when the drive signal is decreased is greater than the time when the reference signal is decreased.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 26, 2022
    Assignees: JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD., JIANGSU ADVANCED MEMORY SEMICONDUCTOR CO., LTD., ALTO MEMORY TECHNOLOGY CORPORATION
    Inventor: Jui-Jen Wu
  • Patent number: 11315610
    Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module, configured to read data in a storage unit on a bit line or a storage unit on a reference bit line; and a first switch module, configured to control the amplification module to be disconnected from the reference bit line when the sense amplifier reads a first state for the bit line and the sense amplifier is in an amplification stage, and control the amplification module to be connected to the reference bit line when the sense amplifier reads a second state for the bit line and the sense amplifier is in the amplification stage. The present disclosure can reduce the power consumption of the sense amplifier.
    Type: Grant
    Filed: December 25, 2020
    Date of Patent: April 26, 2022
    Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., ANHUI UNIVERSITY
    Inventors: Chunyu Peng, Zijian Wang, Wenjuan Lu, Xiulong Wu, Jun He, Xin Li, Zhan Ying, Kanyu Cao, Zhiting Lin, Junning Chen
  • Patent number: 11295788
    Abstract: A method provided herein is adapted to a sense amplifier having a first cross-coupled latch and a second cross-coupled latch, each of which includes a first pair of transistors and a pair of coupling capacitors coupled to respective gate terminals of the first pair of transistors. The method includes, during a first phase, charging the pair of coupling capacitors of a first pair of transistors at a first cross-coupled latch to achieve zeroing and providing a first set of input voltages to a second cross-coupled latch, and, during a second phase following the first phase, discharging the pair of coupling capacitors to cancel a mismatch between the first pair of transistors and comparing the first set of input voltages provided to the second cross-coupled latch to generate a first set of output voltages.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 5, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Wei-Ming Ku
  • Patent number: 11289151
    Abstract: Compensation for threshold voltage mismatches in cross-coupled pairs of transistors and related systems, devices, and methods are disclosed. An apparatus includes a cross-coupled pair of transistors, and a compensation pair of transistors. The cross-coupled pair of transistors includes a first transistor and a second transistor. A first gate of the first transistor is coupled to a first bit line and a second gate of the second transistor coupled to a second bit line. The compensation pair of transistors includes a third transistor and a fourth transistor. The third transistor is coupled in series with the first transistor between a first source of the first transistor and a common source line. The fourth transistor is coupled in series with the second transistor between a second source of the second transistor and the common source line. A memory device includes the sense amplifier. A computing system includes the memory device.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Kyoichi Nagata
  • Patent number: 11270748
    Abstract: Technologies for various memory structures for artificial intelligence (AI) applications and methods thereof are described. An XNOR circuit along with a sense amplifier may be combined with an array (or multiple arrays) of memory such as non-volatile memory (NVM) or an NVM, SRAM combination to perform an XNOR operation on the data read from the memory. Various versions may include different connections allowing simplification of circuitry or timing. In some examples, memory array may include programmable resistor/switch device combinations, or multiple columns connected to a single XNOR+SA circuit.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: March 8, 2022
    Assignee: Aspiring Sky Co., Limited
    Inventors: Zhijiong Luo, Xuntong Zhao
  • Patent number: 11270741
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: March 8, 2022
    Assignee: Rambus Inc.
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Patent number: 11238903
    Abstract: Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Fuad Badrieh, Thomas H. Kinsley, Baekkyu Choi
  • Patent number: 11217303
    Abstract: Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan J. Strand, Sukneet Singh Basuta, Shashank Bangalore Lakshman, Jonathan D. Harms
  • Patent number: 11069385
    Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. A first true digit line has first and second segments along the first deck. A first complementary digit line has third and fourth segments along the second deck. The first true digit line is comparatively compared to the first complementary digit line. A second true digit line has a third region along the first deck and a fourth region along the second deck. The third region is adjacent the first segment, and the fourth region is adjacent the third segment. A second complementary digit line has a fifth region along the first deck and has a sixth region along the second deck. The fifth region is adjacent the second segment, and the sixth region is adjacent the fourth segment. The second true digit line is comparatively compared to the second complementary digit line.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jiyun Li, Scott J. Derner
  • Patent number: 11062763
    Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ferdinando Bedeschi, Stefan Frederik Schippers
  • Patent number: 11049572
    Abstract: A memory device, a source line voltage adjuster and a source line voltage adjusting method thereof are provided. The source line voltage adjuster includes an operation amplifier, a current drainer and a current generator. The operation amplifier includes a first input end coupled to a common source line and a second input end for receiving a reference voltage. The operation amplifier generates an bias voltage. The current drainer drains a drain current from the common source line according to the bias voltage. The current generator provides an output current for the common source line. The current generator generates a first current according to the bias voltage, and generates a second current according to a reference current. The current generator generates the output current according to a difference of the second current and the first current.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: June 29, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chung-Kuang Chen, Yi-Ting Lai
  • Patent number: 11024365
    Abstract: Provided are a time interleaved sampling sense amplifier and a memory device including the same. The sense amplifier senses a voltage stored in the memory cell as 1-bit data or a most significant bit (MSB) and a least significant bit (LSB) of 2-bit data and latches the same to a sensing bit line and a complementary sensing bit line. The sense amplifier includes a first sense amplifier that samples a voltage change of a first bit line when the odd equalizing signal is disabled and a second sense amplifier that samples a voltage change of a second bit line when the even equalizing signal is disabled. The first sense amplifier and the second sense amplifier are alternately arranged, and the odd equalizing signal and the even equalizing signal are disabled with a certain time difference.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: June 1, 2021
    Inventors: Younghun Seo, Bokyeon Won, Dongil Lee
  • Patent number: 11016701
    Abstract: Techniques and mechanisms for a memory device to perform in-memory computing based on a logic state which is detected with a voltage-controlled oscillator (VCO). In an embodiment, a VCO circuit of the memory device receives from a memory array a first signal indicating a logic state that is based on one or more currently stored data bits. The VCO provides a conversion from the logic state being indicated by a voltage characteristic of the first signal to the logic state being indicated by a corresponding frequency characteristic of a cyclical signal. Based on the frequency characteristic, the logic state is identified and communicated for use in an in-memory computation at the memory device. In another embodiment, a result of the in-memory computation is written back to the memory array.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Ian Young, Ram Krishnamurthy, Sasikanth Manipatruni, Amrita Mathuriya, Abhishek Sharma, Raghavan Kumar, Phil Knag, Huseyin Sumbul, Gregory Chen
  • Patent number: 11004481
    Abstract: An internal voltage generation device includes: a voltage detection circuit generating a first detection signal by comparing a first voltage with a target voltage; a voltage difference detection circuit enabled in response to an operation enable signal, generating a second detection signal by comparing a voltage difference between the first voltage and a second voltage with a target gap voltage; a control circuit generating a first up/down code and the operation enable signal according to the first detection signal, and generating a second up/down code according to the second detection signal; a first voltage generation circuit generating the first voltage by down-converting a supply voltage, and adjusting a level of the first voltage according to the first up/down code; and a second voltage generation circuit generating the second voltage by boosting up the supply voltage, and adjusting a level of the second voltage according to the second up/down code.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang-Hoon Lee
  • Patent number: 10978164
    Abstract: A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: April 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takuya Futatsuyama, Kenichi Abe
  • Patent number: 10916299
    Abstract: A semiconductor storage device comprises a memory cell, a write word line and a read word line connected to the memory cell, first and second write bit lines connected to the memory cell, first and second read bit lines connected to the memory cell, a precharge circuit, and a sense amplifier circuit. The precharge circuit is configured to charge, before reading from the memory cell, the first read bit line to a first potential and the second read bit line to a second potential lower than the first potential. The sense amplifier circuit is configured to amplify a difference in potential between the first read bit line and the second read bit line during the reading from the memory cell and output a signal corresponding to the difference in potential as a read value.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Koji Kohara
  • Patent number: 10910054
    Abstract: The present provision includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Di Vincenzo, Riccardo Muzzetto, Ferdinando Bedeschi
  • Patent number: 10910024
    Abstract: A memory device includes a memory array, a sensing circuit, a delay circuit and a controller. The memory array includes a plurality of blocks. The sensing circuit reads data of a selected block of the memory array according to a sensing signal and outputs corresponding output data according to a latch signal. The delay circuit outputs the latch signal. After the sensing signal is enabled, the controller controls the delay circuit to count, to delay output of the latch signal accordingly.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: February 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Chien-Lung Chen
  • Patent number: 10861787
    Abstract: Some embodiments include an integrated memory having a first bitline coupled with a first set of memory cells, and having a second bitline coupled with a second set of memory cells. The first and second bitlines are comparatively coupled through a sense amplifier. A first noise suppression line is adjacent to a region of the first bitline and extends parallel to the region of the first bitline. The first noise suppression line is electrically connected with one of the first and second bitlines and not with the other of the first and second bitlines. A second noise suppression line is adjacent to a region of the second bitline and extends parallel to the region of the second bitline. The second noise suppression line is electrically connected with the other of the first and second bitlines.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Mitsunari Sukekawa, Christopher J. Kawamura
  • Patent number: 10861565
    Abstract: Devices and techniques are disclosed herein to compensate for variance in one or more electrical parameters across multiple signal lines of an array of memory cells. A compensation circuit can provide a bias signal to a first one of the multiple signal lines, the bias signal having an overdrive voltage greater than a target voltage by a selected increment for a selected overdrive period according to a functional compensation profile.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Luyen Tien Vu
  • Patent number: 10839869
    Abstract: A multi-level sensing circuit for a multi-level memory device configured to “recognize” more than two different voltages. The multi-level voltage sensing circuit may include a pre-charge controller configured to pre-charge a pair of bit lines with a bit-line pre-charge voltage level in response to an equalizing signal during a sensing mode. The multi-level voltage sensing circuit may include a read controller configured to maintain a voltage of the pair of bit lines at the bit-line pre-charge voltage level in response to a read control signal during a sensing operation. The multi-level voltage sensing circuit may include a sense-amplifier configured to generate data of the pair of bit lines during the sensing mode. The multi-level voltage sensing circuit may include a voltage sensor configured to generate the equalizing signal by comparing a bit-line voltage with a reference voltage.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyung Sik Won, Tae Hun Kim
  • Patent number: 10839861
    Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 17, 2020
    Assignee: Arm Limited
    Inventors: Vivek Nautiyal, Satinderjit Singh, Abhishek B. Akkur, Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Jungtae Kwon, Jitendra Dasani, Manoj Puthan Purayil
  • Patent number: 10811062
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 20, 2020
    Assignee: Rambus Inc.
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Patent number: 10811061
    Abstract: Memory devices may employ flip-flops with paired transistors in sense amplifying circuitry to sense charges stored in memory cells to perform read and/or activate operations. Sense amplifying circuitry may employ driving devices in driving circuitry to latch the read memory to a high or low voltage. Embodiments include systems and methods that facilitate reduced memory devices with faster memory cell restore by sharing the driving circuitry in different sense amplifying modules. Embodiments may employ switching circuitry in the sense amplifying circuitry to prevent unintentional or faulty readouts.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Harish N. Venkata
  • Patent number: 10803925
    Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Wook Kim, Hyuk-Joon Kwon, Sang-Keun Han, Bok-Yeon Won
  • Patent number: 10796735
    Abstract: In certain aspects, a memory device includes memory bit cells coupled to a read bit line, and a first sense amplifier having a first input coupled to the read bit line, and a first output. The memory device also includes a latch amplifier having a first input coupled to the first output of the first sense amplifier, an enable input, and an output. The memory device also includes one or more dummy bit cells coupled to a dummy bit line, and a second sense amplifier having a first input coupled to the dummy bit line, and an output. The memory device further includes a trigger circuit having an input coupled to the output of the second sense amplifier, and an output coupled to the enable input of the latch amplifier.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 6, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Hochul Lee, Keejong Kim, Anil Chowdary Kota, Chulmin Jung
  • Patent number: 10763265
    Abstract: Some embodiments include an integrated assembly having a first transistor adjacent to a second transistor. The first transistor has a first conductive gate material over a first insulative region, and the second transistor has a second conductive gate material over a second insulative region. A continuous high-k dielectric film extends across both of the first and second insulative regions. In some embodiments, the transistors may be incorporated into a sense amplifier.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Takuya Imamoto, Takeshi Nagai, Yoichi Fukushima
  • Patent number: 10714154
    Abstract: Even when a driven circuit has a large-scale load, a small-scale step-down driver circuit can supply an internal potential to the driven circuit at high speed. A semiconductor integrated circuit device includes a step-down driver circuit which supplies, to a driven circuit to be driven by an internal potential lower than an external potential supplied from an external power supply, the internal potential. The step-down driver circuit includes an NMOS transistor having a drain coupled to an external power supply terminal to be coupled to the external power supply and a source to be coupled to a voltage supply point of the driven circuit and a driver circuit to drive the gate of the NMOS transistor.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: July 14, 2020
    Assignee: RENESAS ELELCTRONICS CORPORATION
    Inventors: Hiroyuki Takahashi, Muneaki Matsushige
  • Patent number: 10679683
    Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device. A walk back circuit is provided to mimic propagation delays of an internal command signal, such as a write command signal, and to speed up the delayed internal command signal an amount equivalent to the propagation delays. The walk back circuit includes a mixture of delay elements provided to mimic propagation delays caused by both gate delays and routing delays.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Liang Chen, Ming-Bo Liu
  • Patent number: 10607671
    Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device. A walk back circuit is provided to mimic propagation delays of an internal command signal, such as a write command signal, and to speed up the delayed internal command signal an amount equivalent to the propagation delays. The walk back circuit includes a mixture of delay elements provided to mimic propagation delays caused by both gate delays and routing delays.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Liang Chen, Ming-Bo Liu
  • Patent number: 10607663
    Abstract: Even when a driven circuit has a large-scale load, a small-scale step-down driver circuit can supply an internal potential to the driven circuit at high speed. A semiconductor integrated circuit device includes a step-down driver circuit which supplies, to a driven circuit to be driven by an internal potential lower than an external potential supplied from an external power supply, the internal potential. The step-down driver circuit includes an NMOS transistor having a drain coupled to an external power supply terminal to be coupled to the external power supply and a source to be coupled to a voltage supply point of the driven circuit and a driver circuit to drive the gate of the NMOS transistor.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 31, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Takahashi, Muneaki Matsushige
  • Patent number: 10607687
    Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Toby D. Robbs, Charles L. Ingalls
  • Patent number: 10608072
    Abstract: A transparent display panel, a manufacturing method thereof, and a transparent display apparatus are disclosed. The transparent display panel includes: a substrate including a non-transparent region and a transparent region; a first power line and a first read line both disposed on the substrate and arranged in the same layer; a dielectric layer covering both the first power line and the first read line; a second power line and a second read line both disposed on a side of the dielectric layer facing away from the substrate and arranged in the same layer. The second power line is electrically connected to the first power line through a first conductive plug extending through the dielectric layer, and the second read line is electrically connected to the first read line through a second conductive plug extending through the dielectric layer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 31, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang
  • Patent number: 10586586
    Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes isolation transistors, equalization transistors and precharge transistors that are used to provide threshold voltage compensation.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyuseok Lee, Sangmin Hwang, Si-Woo Lee
  • Patent number: 10559356
    Abstract: A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of bit cells during write operations. A first write control line is coupled to the control circuit in a first memory tile, and the first write control line is configured to initiate a first write operation in the first memory tile. And a second write control line is coupled to the control circuit in a second memory tile, and the second write control line configured to initiate a second write operation in the second memory tile. The second write operation may be initiated before the first write operation is completed.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: February 11, 2020
    Assignee: NXP USA, INC.
    Inventors: Perry H. Pelley, Anirban Roy, Gayathri Bhagavatheeswaran
  • Patent number: 10541679
    Abstract: Various aspects of amplifying amplitude of a pulse are disclosed herein. In sonic embodiments, a device includes driver circuitry that receives an input pulse swinging or transitioning between a first reference voltage and a second reference voltage higher than the first reference voltage, In some embodiments, the driver circuitry generates a driving pulse swinging between a third reference voltage and the second reference voltage according to the input pulse, where the third reference voltage is between the first reference voltage and the second reference voltage. In some embodiments, the device further includes a transistor coupled to the driver circuitry. In some embodiments, the transistor outputs an output pulse swinging between the first reference voltage and an output voltage according to the driving pulse from the driver circuitry, where the output voltage is higher than the second reference voltage.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: January 21, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Yong Liu, Chang Liu, Delong Cui, Jun Cao
  • Patent number: 10522198
    Abstract: A semiconductor memory device includes a sense amplifier, a voltage supply circuit and a voltage supply control circuit. The sense amplifier may be activated by receiving driving voltages from first to third voltage supply lines to detect and amplify voltage levels of a data line and a data bar line. The voltage supply circuit may apply the driving voltages to the first to third voltage supply lines in response to first to third voltage supply signals and a bias control signal. The voltage supply control circuit may generate the first to third voltage supply signals and the bias control signal in response to an active signal.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyung Sik Won
  • Patent number: 10497414
    Abstract: Various implementations described herein refer to an integrated circuit having dummy wordline driver circuitry coupled to a dummy wordline and dummy bitline pulldown circuitry coupled between a dummy bitline and the dummy wordline. The integrated circuit may include dummy wordline tracking circuitry coupled to the dummy wordline between the dummy wordline driver circuitry and the dummy bitline pulldown circuitry. The dummy wordline tracking circuitry may have one or more variable capacitors that are coupled between the dummy wordline and a variable voltage source.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 3, 2019
    Assignee: Arm Limited
    Inventors: Rahul Mathur, Rajesh Reddy Challa, Gaurang Prabhakar Narvekar
  • Patent number: 10490260
    Abstract: A semiconductor device includes an equalizing circuit and a control circuit. The equalizing circuit executes an operation of pre-charging the signal input/output line pair used for data inputting/outputting and an operation of equalizing it independently of each other. In case a plurality of data write operations occur in succession, the control circuit halts pre-charge control in the equalizing circuit in the course of consecutive write operations.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kyoichi Nagata, Yuuji Motoyama
  • Patent number: 10482938
    Abstract: A semiconductor memory device and method of operation that is capable of reducing disturbance of adjacent word lines. A memory cell array includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. A first word-line, which is selected in response to an access address received from the memory controller, is enabled in response to a first command received from a memory controller, and the first word-line is disabled internally in the semiconductor memory device or in response to a disable command received from the memory controller after a reference time interval elapses. The reference time interval starts from a first time point when the first command is applied to the semiconductor memory device, and corresponds to a time interval equal to or greater than a row active time interval of the semiconductor memory device.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Pil Son, Seong-Il O
  • Patent number: 10453521
    Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Yeop Baeck, Tae-Hyung Kim, Daeyoung Moon, Dong-Wook Seo, Inhak Lee, Hyunsu Choi, Taejoong Song, Jae-Seung Choi, Jung-Myung Kang, Hoon Kim, Jisu Yu, Sun-Yung Jang
  • Patent number: 10423018
    Abstract: A display panel includes a plurality of amplifying circuits arranged in a non-display area and a plurality of gate lines. An input terminal of the amplifying circuit is connected to an output terminal of one or more cascade circuit. An output terminal of the amplifying circuit is connected to a gate line. The amplifying circuit is configured to adjust an output signal from the connected cascade circuit to be a scanning signal and output the scanning signal to the gate line. A liquid crystal display using the display panel is also proposed. The present disclosure simplifies the gate driving circuit, thereby solving the problem of unstable signal transmitting among various stages in the gate driving circuit.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: September 24, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Sikun Hao
  • Patent number: 10410690
    Abstract: A reference-free multi-level sensing circuit for computing-in-memory applications is controlled by a first bit line and a second bit line. An encoding unit generates a first register output value and a plurality of encoded values. The first register output value feedback controls a precharging unit so as to enable the precharging unit to precharge one of the first bit line and the second bit line according to the first register output value. A voltage level of the one of the first bit line and the second bit line is lower than a voltage level of the other one of the first bit line and the second bit line. The encoded values and the first register output value are formed a multi-bit signal to estimate voltage levels of the first bit line and the second bit line.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 10, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Jia-Jing Chen