Flip-flop Used For Sensing Patents (Class 365/205)
  • Patent number: 10811062
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 20, 2020
    Assignee: Rambus Inc.
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Patent number: 10811061
    Abstract: Memory devices may employ flip-flops with paired transistors in sense amplifying circuitry to sense charges stored in memory cells to perform read and/or activate operations. Sense amplifying circuitry may employ driving devices in driving circuitry to latch the read memory to a high or low voltage. Embodiments include systems and methods that facilitate reduced memory devices with faster memory cell restore by sharing the driving circuitry in different sense amplifying modules. Embodiments may employ switching circuitry in the sense amplifying circuitry to prevent unintentional or faulty readouts.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Harish N. Venkata
  • Patent number: 10803925
    Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Wook Kim, Hyuk-Joon Kwon, Sang-Keun Han, Bok-Yeon Won
  • Patent number: 10796735
    Abstract: In certain aspects, a memory device includes memory bit cells coupled to a read bit line, and a first sense amplifier having a first input coupled to the read bit line, and a first output. The memory device also includes a latch amplifier having a first input coupled to the first output of the first sense amplifier, an enable input, and an output. The memory device also includes one or more dummy bit cells coupled to a dummy bit line, and a second sense amplifier having a first input coupled to the dummy bit line, and an output. The memory device further includes a trigger circuit having an input coupled to the output of the second sense amplifier, and an output coupled to the enable input of the latch amplifier.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 6, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Hochul Lee, Keejong Kim, Anil Chowdary Kota, Chulmin Jung
  • Patent number: 10763265
    Abstract: Some embodiments include an integrated assembly having a first transistor adjacent to a second transistor. The first transistor has a first conductive gate material over a first insulative region, and the second transistor has a second conductive gate material over a second insulative region. A continuous high-k dielectric film extends across both of the first and second insulative regions. In some embodiments, the transistors may be incorporated into a sense amplifier.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Takuya Imamoto, Takeshi Nagai, Yoichi Fukushima
  • Patent number: 10714154
    Abstract: Even when a driven circuit has a large-scale load, a small-scale step-down driver circuit can supply an internal potential to the driven circuit at high speed. A semiconductor integrated circuit device includes a step-down driver circuit which supplies, to a driven circuit to be driven by an internal potential lower than an external potential supplied from an external power supply, the internal potential. The step-down driver circuit includes an NMOS transistor having a drain coupled to an external power supply terminal to be coupled to the external power supply and a source to be coupled to a voltage supply point of the driven circuit and a driver circuit to drive the gate of the NMOS transistor.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: July 14, 2020
    Assignee: RENESAS ELELCTRONICS CORPORATION
    Inventors: Hiroyuki Takahashi, Muneaki Matsushige
  • Patent number: 10679683
    Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device. A walk back circuit is provided to mimic propagation delays of an internal command signal, such as a write command signal, and to speed up the delayed internal command signal an amount equivalent to the propagation delays. The walk back circuit includes a mixture of delay elements provided to mimic propagation delays caused by both gate delays and routing delays.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Liang Chen, Ming-Bo Liu
  • Patent number: 10607671
    Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device. A walk back circuit is provided to mimic propagation delays of an internal command signal, such as a write command signal, and to speed up the delayed internal command signal an amount equivalent to the propagation delays. The walk back circuit includes a mixture of delay elements provided to mimic propagation delays caused by both gate delays and routing delays.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Liang Chen, Ming-Bo Liu
  • Patent number: 10608072
    Abstract: A transparent display panel, a manufacturing method thereof, and a transparent display apparatus are disclosed. The transparent display panel includes: a substrate including a non-transparent region and a transparent region; a first power line and a first read line both disposed on the substrate and arranged in the same layer; a dielectric layer covering both the first power line and the first read line; a second power line and a second read line both disposed on a side of the dielectric layer facing away from the substrate and arranged in the same layer. The second power line is electrically connected to the first power line through a first conductive plug extending through the dielectric layer, and the second read line is electrically connected to the first read line through a second conductive plug extending through the dielectric layer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 31, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang
  • Patent number: 10607663
    Abstract: Even when a driven circuit has a large-scale load, a small-scale step-down driver circuit can supply an internal potential to the driven circuit at high speed. A semiconductor integrated circuit device includes a step-down driver circuit which supplies, to a driven circuit to be driven by an internal potential lower than an external potential supplied from an external power supply, the internal potential. The step-down driver circuit includes an NMOS transistor having a drain coupled to an external power supply terminal to be coupled to the external power supply and a source to be coupled to a voltage supply point of the driven circuit and a driver circuit to drive the gate of the NMOS transistor.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 31, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Takahashi, Muneaki Matsushige
  • Patent number: 10607687
    Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Toby D. Robbs, Charles L. Ingalls
  • Patent number: 10586586
    Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes isolation transistors, equalization transistors and precharge transistors that are used to provide threshold voltage compensation.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyuseok Lee, Sangmin Hwang, Si-Woo Lee
  • Patent number: 10559356
    Abstract: A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of bit cells during write operations. A first write control line is coupled to the control circuit in a first memory tile, and the first write control line is configured to initiate a first write operation in the first memory tile. And a second write control line is coupled to the control circuit in a second memory tile, and the second write control line configured to initiate a second write operation in the second memory tile. The second write operation may be initiated before the first write operation is completed.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: February 11, 2020
    Assignee: NXP USA, INC.
    Inventors: Perry H. Pelley, Anirban Roy, Gayathri Bhagavatheeswaran
  • Patent number: 10541679
    Abstract: Various aspects of amplifying amplitude of a pulse are disclosed herein. In sonic embodiments, a device includes driver circuitry that receives an input pulse swinging or transitioning between a first reference voltage and a second reference voltage higher than the first reference voltage, In some embodiments, the driver circuitry generates a driving pulse swinging between a third reference voltage and the second reference voltage according to the input pulse, where the third reference voltage is between the first reference voltage and the second reference voltage. In some embodiments, the device further includes a transistor coupled to the driver circuitry. In some embodiments, the transistor outputs an output pulse swinging between the first reference voltage and an output voltage according to the driving pulse from the driver circuitry, where the output voltage is higher than the second reference voltage.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: January 21, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Yong Liu, Chang Liu, Delong Cui, Jun Cao
  • Patent number: 10522198
    Abstract: A semiconductor memory device includes a sense amplifier, a voltage supply circuit and a voltage supply control circuit. The sense amplifier may be activated by receiving driving voltages from first to third voltage supply lines to detect and amplify voltage levels of a data line and a data bar line. The voltage supply circuit may apply the driving voltages to the first to third voltage supply lines in response to first to third voltage supply signals and a bias control signal. The voltage supply control circuit may generate the first to third voltage supply signals and the bias control signal in response to an active signal.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyung Sik Won
  • Patent number: 10497414
    Abstract: Various implementations described herein refer to an integrated circuit having dummy wordline driver circuitry coupled to a dummy wordline and dummy bitline pulldown circuitry coupled between a dummy bitline and the dummy wordline. The integrated circuit may include dummy wordline tracking circuitry coupled to the dummy wordline between the dummy wordline driver circuitry and the dummy bitline pulldown circuitry. The dummy wordline tracking circuitry may have one or more variable capacitors that are coupled between the dummy wordline and a variable voltage source.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 3, 2019
    Assignee: Arm Limited
    Inventors: Rahul Mathur, Rajesh Reddy Challa, Gaurang Prabhakar Narvekar
  • Patent number: 10490260
    Abstract: A semiconductor device includes an equalizing circuit and a control circuit. The equalizing circuit executes an operation of pre-charging the signal input/output line pair used for data inputting/outputting and an operation of equalizing it independently of each other. In case a plurality of data write operations occur in succession, the control circuit halts pre-charge control in the equalizing circuit in the course of consecutive write operations.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kyoichi Nagata, Yuuji Motoyama
  • Patent number: 10482938
    Abstract: A semiconductor memory device and method of operation that is capable of reducing disturbance of adjacent word lines. A memory cell array includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. A first word-line, which is selected in response to an access address received from the memory controller, is enabled in response to a first command received from a memory controller, and the first word-line is disabled internally in the semiconductor memory device or in response to a disable command received from the memory controller after a reference time interval elapses. The reference time interval starts from a first time point when the first command is applied to the semiconductor memory device, and corresponds to a time interval equal to or greater than a row active time interval of the semiconductor memory device.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Pil Son, Seong-Il O
  • Patent number: 10453521
    Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Yeop Baeck, Tae-Hyung Kim, Daeyoung Moon, Dong-Wook Seo, Inhak Lee, Hyunsu Choi, Taejoong Song, Jae-Seung Choi, Jung-Myung Kang, Hoon Kim, Jisu Yu, Sun-Yung Jang
  • Patent number: 10423018
    Abstract: A display panel includes a plurality of amplifying circuits arranged in a non-display area and a plurality of gate lines. An input terminal of the amplifying circuit is connected to an output terminal of one or more cascade circuit. An output terminal of the amplifying circuit is connected to a gate line. The amplifying circuit is configured to adjust an output signal from the connected cascade circuit to be a scanning signal and output the scanning signal to the gate line. A liquid crystal display using the display panel is also proposed. The present disclosure simplifies the gate driving circuit, thereby solving the problem of unstable signal transmitting among various stages in the gate driving circuit.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: September 24, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Sikun Hao
  • Patent number: 10410690
    Abstract: A reference-free multi-level sensing circuit for computing-in-memory applications is controlled by a first bit line and a second bit line. An encoding unit generates a first register output value and a plurality of encoded values. The first register output value feedback controls a precharging unit so as to enable the precharging unit to precharge one of the first bit line and the second bit line according to the first register output value. A voltage level of the one of the first bit line and the second bit line is lower than a voltage level of the other one of the first bit line and the second bit line. The encoded values and the first register output value are formed a multi-bit signal to estimate voltage levels of the first bit line and the second bit line.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 10, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Jia-Jing Chen
  • Patent number: 10395717
    Abstract: Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Di Vincenzo, Ferdinando Bedeschi
  • Patent number: 10388337
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: August 20, 2019
    Assignee: Rambus Inc.
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Patent number: 10381063
    Abstract: Single thyristor memory cells form a volatile memory array. A sense amplifier reads the state of the thyristor in a selected memory cell against a dummy cell through precharged lines.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: August 13, 2019
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 10355941
    Abstract: A system maintains, generates, and manages infrastructure layouts. The infrastructure layouts include structural relationships for the handling of received sensor data. The infrastructure layouts may be traversed to determine datastore options for the sensor data and contextual information that may be used to enrich the received sensor data.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 16, 2019
    Assignee: Accenture Global Services Limited
    Inventors: Teresa Sheausan Tung, Karthik Gomadam, Qing Xie
  • Patent number: 10290340
    Abstract: Aspects disclosed in the detailed description include offset-canceling (OC) write operation sensing circuits for sensing switching in a magneto-resistive random access memory (MRAM) bit cell in an MRAM for a write operation. The OC write operation sensing circuit is configured to sense when MTJ switching occurs in MRAM bit cell. In an example, the OC write operation sensing circuit includes a voltage sensing circuit and a sense amplifier. The voltage sensing circuit employs a capacitive-coupling effect so that the output voltage drops in response to MTJ switching for both logic ‘0’ and logic ‘1’ write operations. The sense amplifier has a single input and a single output node with an output voltage indicating when MTJ switching has occurred in the MRAM bit cell. A single input transistor and pull-up transistor are provided in the sense amplifier in one example to provide an offset-canceling effect.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 14, 2019
    Assignees: QUALCOMM Technologies, Incorporated, Yonsei University, University-Industry Foundation
    Inventors: Seong-Ook Jung, Sara Choi, Hong Keun Ahn, Seung Hyuk Kang, Sungryul Kim
  • Patent number: 10290919
    Abstract: An electronic device is provided, including a display module, an input module, a hinge module, and an antenna. The hinge module connects the display module and the input module and has a first side and an opposite second side. The antenna is disposed in the hinge module and is situated on the first side. When the display module is rotated with respect to the input module, the hinge module forces the antenna to move from the first side to the second side.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 14, 2019
    Assignee: WISTRON CORP.
    Inventors: Yu Chen Hsu, Ching Pin Hsu, Chien An Chou
  • Patent number: 10255968
    Abstract: A dynamic random-access memory (DRAM) for use with a display includes a plurality of capacitive elements coupled to store one or more bits of data, and a plurality of switches where at least one individual switch in the plurality of switches is coupled to an individual capacitive element in the plurality of capacitive elements. A plurality of input/output (I/O) bit lines including 32 or more input/output bit lines is coupled to read out the data from the plurality of capacitive elements. A plurality of column select lines is coupled to enable readout of the plurality of capacitive elements.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 9, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventors: Jongsik Na, Taehyung Jung
  • Patent number: 10224101
    Abstract: A data holding device 100 has an inverter loop 101, a differential pair circuit 102 connected to the ground terminals of inverters, a first potential setter 103 configured to turn the output terminals of the inverters to a first potential (VDD), and a second potential setter 104 configured to turn the ground terminals of the inverters to a second potential (VSS). During data holding, the differential pair circuit 102 and the first potential setter 103 are disabled so that the ground terminals of the inverters are at the second potential. During data writing, the differential pair circuit 102 is disabled so that the output terminal of one inverter is at the first potential and the ground terminal of the other inverter is at the second potential.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: March 5, 2019
    Assignee: Rohm Co., Ltd.
    Inventors: Hiromitsu Kimura, Takanori Ozawa
  • Patent number: 10168758
    Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Anupama Suryanarayanan, Avinash N. Ananthakrishnan, Chinmay Ashok, Jeremy J. Shrall
  • Patent number: 10109344
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of bank arrays and a control logic circuit. The control logic circuit controls access to the memory cell array in response to a command and an address. A first number of memory cells are coupled to a bit-line of a first bank array of the plurality of bank arrays, a second number of memory cells are coupled to a bit-line of a second bank array of the plurality of bank arrays and the first number is different from the second number.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang-Kyu Kang
  • Patent number: 10096346
    Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
  • Patent number: 10020043
    Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: July 10, 2018
    Assignee: TC Lab, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 10007439
    Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: June 26, 2018
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Jin-Ki Kim
  • Patent number: 9997213
    Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: June 12, 2018
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l.
    Inventors: Francesco La Rosa, Gineuve Alieri
  • Patent number: 9978444
    Abstract: A memory and a method for operating the memory are presented. The memory includes a memory cell, a sense amplifier configured to sense read data from the memory cell, a write driver configured to provide write data to the memory cell, a first circuit configured to enable the sense amplifier during a time period, and a second circuit configured to enable the write driver during at least a portion of the time period. The method includes enabling a sense amplifier to sense read data from a memory cell during a time period and enabling a write driver to provide write data to the memory cell during at least a portion of the time period. Another memory and method for operating the memory are presented. The memory and method further include an address input circuit configured to receive a write address while the sense amplifier is enabled.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: May 22, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Tony Chung Yiu Kwok, Changho Jung
  • Patent number: 9979649
    Abstract: An associative memory that can be integrated with standard computer memory flexibly reduces its parallelism to match the memory bus speed thereby providing substantial increases in memory density possible by a multiplexing of sense amplifiers that otherwise dominate the memory structure. Apparent parallel operation is provided by an accumulator that reassembles the multiplex data. Higher memory density makes dual use of the associative memory as a content addressable memory and random-access memory possible.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: May 22, 2018
    Assignee: Wisconsin Alumin Research Foundation
    Inventor: Jing Li
  • Patent number: 9978447
    Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Yih Wang, Muhammad M. Khellah, Fatih Hamzaoglu
  • Patent number: 9947385
    Abstract: A semiconductor memory device includes: a first memory cell coupled to a first bit line; a second memory cell coupled to a second bit line; and a sense amplification circuit for sensing and amplifying a voltage difference between the first and second bit lines, wherein the sense amplification circuit includes: a first sense amplifier including a cross-coupled pair of first and second transistors coupled to the first bit line and the second bit line, respectively; a second sense amplifier including a cross-coupled pair of third and fourth transistors coupled to the first and second bit lines, respectively; and an offset supplier for controlling a timing for supplying a voltage of the first bit line to the first transistor and a timing for supplying a voltage of the second bit line to the second transistor according to a selected memory from the first and second memory cells.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 17, 2018
    Assignee: SK Hynix Inc.
    Inventor: Hae-Rang Choi
  • Patent number: 9880938
    Abstract: In accordance with an embodiment, described herein is a system and method for compacting a pseudo linear byte array, for use with supporting access to a database. A database driver (e.g., a Java Database Connectivity (JDBC) driver) provides access by software application clients to a database. When a result set (e.g., ResultSet) is returned for storage in a dynamic byte array (DBA), in response to a database query (e.g., a SELECT), the database driver determines if the DBA is underfilled and, if so, calculates the data size of the DBA, creates a static byte array (SBA) in a cache at the client, compacts the returned data into the SBA, and stores the data size as part of the metadata associated with the cache. In accordance with an embodiment, the DBA and the SBA can use a same interface for access by client applications.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: January 30, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Ashok Shivarudraiah, Douglas Surber, Jean De Lavarene
  • Patent number: 9847110
    Abstract: An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical OR between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. The control component can cause storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: December 19, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Patrick A. La Fratta
  • Patent number: 9831179
    Abstract: A semiconductor device includes a plurality of line patterns formed apart from one another on a substrate, the plurality of line patterns having a first width and extending parallel to one another in a first direction. A first line pattern of the plurality of line patterns may include a wider portion having a second width in a second direction perpendicular to the first direction that is greater than the first width. One or more second line patterns may be located adjacent to the first line pattern and include a conformal portion conformally formed about the wider portion of the first line pattern. One or more third line patterns may be located adjacent to the second line pattern and include an end portion near the conformal portion of the one or more second line pattern.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: November 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-hoon Kim, Woo-sung Yang, Jee-hoon Hwang
  • Patent number: 9792967
    Abstract: A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local evaluation circuit to a global bit line (GBL) of the global evaluation circuit. The global evaluation circuit can include a holding circuit. The wake transistor can be turned on in response to a read signal, and remain on while the GBL is precharged to a logical “high” voltage. Memory cells connected to the at least one local bit line can be addressed, and the local bit line can be pulled to a logical “low” voltage for a first time period. The GBL can be pulled to a logical low voltage for a second time period, and the holding circuit polarity can be reversed during a third time period.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: October 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul A. Bunce, Yuen H. Chan, John D. Davis, Silke Penth, David E. Schmitt, Tobias Werner, Brian J. Yavoich
  • Patent number: 9792856
    Abstract: An organic light emitting display device includes a display area and a non-display area. The display area includes display pixels at crossing areas of data lines, scan lines, and emission control lines. The non-display area includes auxiliary pixels at crossing positions of auxiliary data lines, scan lines, and emission control lines. The display device also includes a scan driver to supply scan signals to the scan lines, a first data driver to supply data voltages to the data lines, a second data driver to supply an auxiliary data voltage to the auxiliary data line, and a demultiplexer between the data lines and the first data driver.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: October 17, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyong-Tae Park, Dong-Yoon So, Sung-Ho Cho, Yu-Hyun Cho
  • Patent number: 9779783
    Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Darren L. Anand, John A. Fifield, Eric D. Hunt-Schroeder, Mark D. Jacunski
  • Patent number: 9773544
    Abstract: A switchable sense amplifier includes a sense amplification unit and a plurality of switches. The sense amplification unit senses a voltage change of a bit line connected to a memory cell and amplifies a voltage difference between the bit line and a complementary bit line. The plurality of switches operate according to switching signals, and thus, enable the sense amplification unit to perform a pre-charging operation, an offset cancellation operation, a charge sharing operation, a sensing operation, and a re-storing operation. The sense amplifier may enhance an effective sensing margin by compensating for an offset of the sense amplifier, through an offset cancellation operation, and thus enhance performance of a memory apparatus.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: September 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Myung Woo, Young-Seok Park
  • Patent number: 9754655
    Abstract: In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: September 5, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Mosaddiq Saifuddin, SankaraRao Kunapareddy, Keunsoo Roh, Chun Xiang He, Pratik Patel, Nicholas Ambur, Jeremy Haugen
  • Patent number: 9711194
    Abstract: A circuit for controlling the operation of a memory system having different types of memory is described. The circuit comprises a first memory having a first type of memory element and having a first access time; a second memory having a second type of memory element and having a second access time, wherein the second type of memory element is different than the first type of memory element; a memory control circuit enabling access to the first memory and the second memory; a delay buffer coupled to the second memory to compensate for a difference in the first access time and the second access time; and a circuit for merging outputs of the first memory and delayed outputs of the second memory to generate ordered output data. A method of controlling the operation of a memory system is also disclosed.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: July 18, 2017
    Assignee: XILINX, INC.
    Inventors: Michaela Blott, Ling Liu, Kornelis A. Vissers
  • Patent number: 9704545
    Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of word lines and a plurality of bit lines, wherein each memory cell is coupled to a respective word line and bit line. The semiconductor memory device includes a plurality of sense amplifiers, wherein each sense amplifier is coupled to two bit lines. The semiconductor memory device is configured to receive a first positive supply voltage, a second positive supply voltage, and a negative supply voltage, and determine a low level of an amplified voltage based on the negative supply voltage in an operation of amplifying data in a memory cell.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: July 11, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Heon Yu, Jonghyun Choi, Dongwoo Sohn, Ki-Seok Oh
  • Patent number: 9697879
    Abstract: In some examples, a memory device may be configured to use shared read circuitry to sample a voltage drop across both a bit cell and a resistive circuit in order to perform a comparison that produces an output corresponding to the bit stored in the bit cell. The shared read circuitry can include a shared sense amplifier as well as shared N-MOS and P-MOS followers used to apply read voltages across the bit cell and resistive circuit.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: July 4, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Syed M. Alam, Chitra K. Subramanian