Abstract: A command decoder circuit, a memory, and an electronic device are provided. The circuit includes a first decoder unit, configured to perform decoding for a first command signal based on a dynamic clock signal; a second decoder unit, configured to perform decoding for a second command signal based on the dynamic clock signal; and the clock gate, configured to generate the dynamic clock signal after a chip select signal of the first decoder unit indicates that decoding to be started for the first command signal and before the second decoder unit has performed decoding for the second command signal, and cut off the dynamic clock signal before the chip select signal of the first decoder unit indicates that the decoding to be started for the first command signal or after the second decoder unit has performed decoding for the second command signal.

Abstract: In certain aspects, a comparator includes an input stage and a regeneration stage. The input stage includes a first input circuit coupled to a first node and a second node, a first switching transistor configured to enable the first input circuit if a previous bit value is one, a second input circuit coupled to the first node and the second node, and a second switching transistor configured to enable the second input circuit if the previous bit value is zero. The regeneration stage includes a first inverter, a second inverter cross coupled with the first inverter, a first drive transistor coupled to the first inverter, wherein a gate of the first drive transistor is coupled to the second node, and a second drive transistor coupled to the second inverter, wherein a gate of the second drive transistor is coupled to the first node.

Abstract: A method for accessing memory and a memory device using the same method are provided. The method includes: coupling, by a first sense amplifier (SA) of a memory, to a memory cell of the memory to receive data from the memory cell; coupling a first terminal of a transistor of the memory to the first SA; coupling a first command terminal of a system on chip (SoC) to a second terminal of the transistor, and coupling a first input/output (I/O) terminal of the SoC to a third terminal of the transistor; and issuing, by the SoC, an access command to the second terminal of the transistor to access the data output by the first SA through the third terminal of the transistor.

Abstract: The sense amplifier includes: an amplification module configured to amplify a voltage transmitted by a bit line or a reference bit line, when the sense amplifier is at an amplification stage; a first switch module configured to control the amplification module to be disconnected from the reference bit line, when the sense amplifier performs a read operation for the bit line and is at the amplification stage. In the disclosure, the power consumption of the sense amplifier may be reduced.

Abstract: An efficient, high density, inline converter module includes a power conversion circuit and an input wiring harness for connecting the input of the power circuit to a unipolar source. A second wiring harness or electrical connectors may be provided for connecting the output of the power conversion circuit to a load. Connections between a wiring harness and the power conversion circuit may comprise conductive contacts, configured to distribute heat. The power circuit may be over molded to provide electrical insulation and efficient heat transfer to external ambient air. A DC transformer based inline converter module may be used in AC adapter, vehicular, and power system architectures. An input connector for connecting the input wiring harness to the input source may be provided. In some embodiments the input source may be an AC source and the input connector may comprise a rectifier for delivering a rectified, unipolar, voltage to the input of the power conversion assembly via an input wiring harness.

Abstract: A semiconductor memory device includes first and second memory cell arrays spaced apart from each other in a first direction, a plurality of column selection transistors in a second direction which intersects the first direction, between the first and second memory cell arrays, at least two of the column selection transistors include respective portions of a central gate pattern, which intersects a central line extending in the first direction at a center of the first memory cell array and has a closed loop shape, and first and second local input/output lines configured to provide electric potential through the first memory cell array to a local sense amplifier based on operations of the column selection transistors. The first and second local input/output lines are electrically connected to the central gate pattern, and the center line is spaced apart from and does not intersect the first and second local input/output lines.

Abstract: A sense amplifier includes a first switch unit, a second switch unit, and an amplifier-latch module. A first port of the amplifier-latch module is electrically connected, via the first switch unit, to a bit line connected with a storage unit, and a second port of the amplifier-latch module is electrically connected to a reference voltage signal via the second switch unit. The amplifier-latch module is configured to amplify a signal in a sensing amplification phase. The first switch unit is configured to transmit a voltage on the bit line to the first port before the sensing amplification phase. The second switch unit is configured to transmit the reference voltage signal to the second port before the sensing amplification phase, and disconnect an electrical connection between the reference voltage signal and the second port in the sensing amplification phase.

Abstract: A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, the package test, the module test or the mounting test is failed.

Abstract: Methods, systems, and devices for deck-level signal development cascodes are described. A memory device may include transistors that support both a signal development and decoding functionality. In a first operating condition (e.g., an open-circuit condition), a transistor may be operable to isolate first and second portions of an access line based on a first voltage applied to a gate of the transistor. In a second operating condition (e.g., a signal development condition), the transistor may be operable to couple the first and second portions of the access line and generate an access signal based on a second voltage applied to the gate of the transistor. In a third operating condition (e.g., a closed-circuit condition), the transistor may be operable to couple the first and second portions of the access line based on applying a third voltage greater than the second voltage to the gate of the transistor.

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

Abstract: Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: A sense amplifier includes a bit line sense amplifier including a first transistor and a second transistor spaced apart from each other in a first direction, a second conductive line configured to electrically connect the first transistor to the second transistor and extending in the first direction and a local sense amplifier configured to at least partially overlap the second conductive line and disposed between the first transistor and the second transistor.

Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.

Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.

Abstract: A comparator includes a second-stage circuit, a first input circuit, a second input circuit, a first cross-coupled circuit and a second cross-coupled circuit. The first input circuit is configured to generate a first data terminal voltage and a first reference terminal voltage. The first cross-coupled circuit is configured to perform mutual positive feedback on the first data terminal voltage and the first reference terminal voltage to generate a first differential signal. The second input circuit is configured to generate a second data terminal voltage and a second reference terminal voltage. The second cross-coupled circuit is configured to perform mutual positive feedback on the second data terminal voltage and the second reference terminal voltage to generate a second differential signal. The second-stage circuit is configured to amplify and latch the first differential signal or the second differential signal in a regeneration phase to output a comparison signal.

Abstract: A radio frequency (RF) summer circuit having a characteristic impedance Zo comprises first and second ports coupled by first and second resistances, respectively, to a junction. The circuit further comprises a series combination of a third resistance and a switch movable between open and closed positions and an amplifier having input and output terminals and operable in an off state and an on state wherein the series combination is coupled across the input and output terminals of the amplifier between the junction and a third port. The first resistance, second resistance, and the third resistance are all substantially equal to Z0/3. Further, when the switch is moved to the closed position and the amplifier is switched to the off state a passive mode of operation is implemented and when the switch is moved to the open position and the amplifier is switched to the on state an active mode of operation is implemented.

Abstract: A static random access memory (SRAM) system includes a plurality of SRAM storage cells, each of the plurality of SRAM storage cells coupled to a respective read bit line, and a dynamic keeper coupled to the read bit line. The dynamic keeper includes a first keeper to support a read operation at a first temperature range, and a second keeper to support the read operation at a second temperature range, and a temperature-sensitive control circuit to select the first keeper or the second keeper based on temperature.

Abstract: A method of encrypting data in a nonvolatile memory device (NVM) includes; programming data in selected memory cells, sensing the selected memory cells at a first time during a develop period to provide random data, sensing the selected memory cells at a second time during the develop period to provide main data, encrypting the main data using the random data to generate encrypted main data, and outputting the encrypted main data to an external circuit, wherein the randomness of the random data is based on a threshold voltage distribution of the selected memory cells.

Abstract: The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.

Abstract: Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell.

Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.

Abstract: A method and a display device are provided. The method includes: generating a plurality of timing control signals for controlling a plurality of LED driving circuits, wherein the plurality of timing control signals include a first timing control signal and a second timing control signal; allowing the first LED driving circuit to drive an Nth scan line of a first display region at a first driving timing through the first timing control signal; and allowing the second LED driving circuit to drive an Nth scan line of the second display region at a second driving timing that is different from the first driving timing through the second timing control signal.

Abstract: An efficient, high density, inline converter module includes a power conversion circuit and an input wiring harness for connecting the input of the power circuit to a unipolar source. A second wiring harness or electrical connectors may be provided for connecting the output of the power conversion circuit to a load. Connections between a wiring harness and the power conversion circuit may comprise conductive contacts, configured to distribute heat. The power circuit may be over molded to provide electrical insulation and efficient heat transfer to external ambient air. A DC transformer based inline converter module may be used in AC adapter, vehicular, and power system architectures. An input connector for connecting the input wiring harness to the input source may be provided. In some embodiments the input source may be an AC source and the input connector may comprise a rectifier for delivering a rectified, unipolar, voltage to the input of the power conversion assembly via an input wiring harness.

Abstract: The embodiments of the present disclosure provide a gate driving circuit, a display device, and a display control method. The gate driving circuit includes: a first gate driving sub-circuit configured to output a scan signal and control the first display area to display according to the scan signal; a display area control unit having an input terminal configured to receive the scan signal output by the first gate driving sub-circuit, a control terminal configured to receive a split-screen control signal output by the split-screen control signal terminal, and an output terminal configured to output or not output the scan signal according to the split-screen control signal; and a second gate driving sub-circuit configured to control a display state of the second display area according to whether the scan signal is received or not.

Abstract: A sense amplification device is provided. The sense amplification device includes a first sense amplifier, a second sense amplifier, and a third sense amplifier. An input terminal of the first sense amplifier is coupled to a first bit line. An input terminal of the second sense amplifier is coupled to a second bit line. The third sense amplifier has a differential input pair and a differential output pair, wherein a first input terminal of the differential input pair is coupled to an output terminal of the first sense amplifier, a second input terminal of the differential input pair is coupled to an output terminal of the second sense amplifier, a first output terminal of the differential output pair is coupled to the input terminal of the first sense amplifier, and a second output terminal of the differential output pair is coupled to the input terminal of the second sense amplifier.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.

Abstract: In one example, a fluid property sensor includes an electrical circuit assembly (ECA), an elongated circuit (EC), and an external interface. The EC is attached to the ECA and includes multiple point sensors distributed along a length of the EC. The external interface is electrically coupled to a proximal end of the EC. The EC and the external interface are packaged together with an encasement on both sides of the ECA to form the fluid property sensor.

Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module, configured to read data in a storage unit on a bit line or a storage unit on a reference bit line; and a first switch module, configured to control the amplification module to be disconnected from the reference bit line when the sense amplifier reads a first state for the bit line and the sense amplifier is in an amplification stage, and control the amplification module to be connected to the reference bit line when the sense amplifier reads a second state for the bit line and the sense amplifier is in the amplification stage. The present disclosure can reduce the power consumption of the sense amplifier.

Abstract: Disclosed is a memory drive device. The memory drive device comprises a control circuit, a reference voltage generation circuit, and a first switch. The control circuit is used to generate a first signal according to an input signal. The reference voltage generation circuit comprises a reference resistor and is used to generate a reference signal according to the first signal. The first switch is coupled to a memory resistor and is used to generate a drive signal according to the first signal so as to set a resistance value of the memory resistor. When the input signal is decreased and a resistance value of the memory resistor is greater than a resistance value of the reference resistor, the time when the drive signal is decreased is greater than the time when the reference signal is decreased.

Abstract: A method provided herein is adapted to a sense amplifier having a first cross-coupled latch and a second cross-coupled latch, each of which includes a first pair of transistors and a pair of coupling capacitors coupled to respective gate terminals of the first pair of transistors. The method includes, during a first phase, charging the pair of coupling capacitors of a first pair of transistors at a first cross-coupled latch to achieve zeroing and providing a first set of input voltages to a second cross-coupled latch, and, during a second phase following the first phase, discharging the pair of coupling capacitors to cancel a mismatch between the first pair of transistors and comparing the first set of input voltages provided to the second cross-coupled latch to generate a first set of output voltages.

Abstract: Compensation for threshold voltage mismatches in cross-coupled pairs of transistors and related systems, devices, and methods are disclosed. An apparatus includes a cross-coupled pair of transistors, and a compensation pair of transistors. The cross-coupled pair of transistors includes a first transistor and a second transistor. A first gate of the first transistor is coupled to a first bit line and a second gate of the second transistor coupled to a second bit line. The compensation pair of transistors includes a third transistor and a fourth transistor. The third transistor is coupled in series with the first transistor between a first source of the first transistor and a common source line. The fourth transistor is coupled in series with the second transistor between a second source of the second transistor and the common source line. A memory device includes the sense amplifier. A computing system includes the memory device.

Abstract: Technologies for various memory structures for artificial intelligence (AI) applications and methods thereof are described. An XNOR circuit along with a sense amplifier may be combined with an array (or multiple arrays) of memory such as non-volatile memory (NVM) or an NVM, SRAM combination to perform an XNOR operation on the data read from the memory. Various versions may include different connections allowing simplification of circuitry or timing. In some examples, memory array may include programmable resistor/switch device combinations, or multiple columns connected to a single XNOR+SA circuit.

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

Abstract: Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

Abstract: Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. A first true digit line has first and second segments along the first deck. A first complementary digit line has third and fourth segments along the second deck. The first true digit line is comparatively compared to the first complementary digit line. A second true digit line has a third region along the first deck and a fourth region along the second deck. The third region is adjacent the first segment, and the fourth region is adjacent the third segment. A second complementary digit line has a fifth region along the first deck and has a sixth region along the second deck. The fifth region is adjacent the second segment, and the sixth region is adjacent the fourth segment. The second true digit line is comparatively compared to the second complementary digit line.

Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.

Abstract: A memory device, a source line voltage adjuster and a source line voltage adjusting method thereof are provided. The source line voltage adjuster includes an operation amplifier, a current drainer and a current generator. The operation amplifier includes a first input end coupled to a common source line and a second input end for receiving a reference voltage. The operation amplifier generates an bias voltage. The current drainer drains a drain current from the common source line according to the bias voltage. The current generator provides an output current for the common source line. The current generator generates a first current according to the bias voltage, and generates a second current according to a reference current. The current generator generates the output current according to a difference of the second current and the first current.

Abstract: Provided are a time interleaved sampling sense amplifier and a memory device including the same. The sense amplifier senses a voltage stored in the memory cell as 1-bit data or a most significant bit (MSB) and a least significant bit (LSB) of 2-bit data and latches the same to a sensing bit line and a complementary sensing bit line. The sense amplifier includes a first sense amplifier that samples a voltage change of a first bit line when the odd equalizing signal is disabled and a second sense amplifier that samples a voltage change of a second bit line when the even equalizing signal is disabled. The first sense amplifier and the second sense amplifier are alternately arranged, and the odd equalizing signal and the even equalizing signal are disabled with a certain time difference.

Abstract: Techniques and mechanisms for a memory device to perform in-memory computing based on a logic state which is detected with a voltage-controlled oscillator (VCO). In an embodiment, a VCO circuit of the memory device receives from a memory array a first signal indicating a logic state that is based on one or more currently stored data bits. The VCO provides a conversion from the logic state being indicated by a voltage characteristic of the first signal to the logic state being indicated by a corresponding frequency characteristic of a cyclical signal. Based on the frequency characteristic, the logic state is identified and communicated for use in an in-memory computation at the memory device. In another embodiment, a result of the in-memory computation is written back to the memory array.

Abstract: An internal voltage generation device includes: a voltage detection circuit generating a first detection signal by comparing a first voltage with a target voltage; a voltage difference detection circuit enabled in response to an operation enable signal, generating a second detection signal by comparing a voltage difference between the first voltage and a second voltage with a target gap voltage; a control circuit generating a first up/down code and the operation enable signal according to the first detection signal, and generating a second up/down code according to the second detection signal; a first voltage generation circuit generating the first voltage by down-converting a supply voltage, and adjusting a level of the first voltage according to the first up/down code; and a second voltage generation circuit generating the second voltage by boosting up the supply voltage, and adjusting a level of the second voltage according to the second up/down code.

Abstract: A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.

Abstract: A semiconductor storage device comprises a memory cell, a write word line and a read word line connected to the memory cell, first and second write bit lines connected to the memory cell, first and second read bit lines connected to the memory cell, a precharge circuit, and a sense amplifier circuit. The precharge circuit is configured to charge, before reading from the memory cell, the first read bit line to a first potential and the second read bit line to a second potential lower than the first potential. The sense amplifier circuit is configured to amplify a difference in potential between the first read bit line and the second read bit line during the reading from the memory cell and output a signal corresponding to the difference in potential as a read value.

Abstract: A memory device includes a memory array, a sensing circuit, a delay circuit and a controller. The memory array includes a plurality of blocks. The sensing circuit reads data of a selected block of the memory array according to a sensing signal and outputs corresponding output data according to a latch signal. The delay circuit outputs the latch signal. After the sensing signal is enabled, the controller controls the delay circuit to count, to delay output of the latch signal accordingly.

Abstract: The present provision includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

Abstract: Devices and techniques are disclosed herein to compensate for variance in one or more electrical parameters across multiple signal lines of an array of memory cells. A compensation circuit can provide a bias signal to a first one of the multiple signal lines, the bias signal having an overdrive voltage greater than a target voltage by a selected increment for a selected overdrive period according to a functional compensation profile.

Abstract: Some embodiments include an integrated memory having a first bitline coupled with a first set of memory cells, and having a second bitline coupled with a second set of memory cells. The first and second bitlines are comparatively coupled through a sense amplifier. A first noise suppression line is adjacent to a region of the first bitline and extends parallel to the region of the first bitline. The first noise suppression line is electrically connected with one of the first and second bitlines and not with the other of the first and second bitlines. A second noise suppression line is adjacent to a region of the second bitline and extends parallel to the region of the second bitline. The second noise suppression line is electrically connected with the other of the first and second bitlines.