Abstract: There is provided a semiconductor device having a wiring configuration which can suppress an increase in the delay time of a wiring extending over the memory cell area even if the cell size is reduced. Wirings of preset wiring length are formed over a semiconductor substrate. A wiring of wiring length larger than that of the former wirings is formed over the former wirings with an inter-level insulation film disposed therebetween and the width of the latter wiring is made large. Thus, the wiring resistance is reduced and the wiring delay time can be effectively reduced. The semiconductor device is applied to a semiconductor memory or the like in which cell selection is made by use of the hierarchical structure such as a duplex word line system.

Abstract: In a DRAM, buffer circuits constituting a column address buffer are provided near address input pads receiving external address signals to be input thereto, and switch circuits arranged near the address input pads are connected between the address input pads and a row address buffer. Driving capability of each buffer circuits is set larger than in the prior art. Each switch circuit is controlled to be OFF while a column address signal is being supplied to a corresponding one of the address input pads. While the column address signal is externally applied to the address input pads, the capacitance and resistance of the interconnection layer which affects the waveform of the internal column address signal can be reduced, and hence time required for selecting one column of memory cells in each of memory cell array blocks in response to the external column address signal can be reduced, thus reducing the access time in the DRAM.

Abstract: According to this invention, a semiconductor apparatus includes a word line group consisting of four word lines, a bit line pair group, word line drive circuits, arrangement patterns of which are alternately inverted, for outputting boosted word line signals to the word line group, and memory contact portions provided to the bit line pair group in a 1/4-pitch system, wherein output terminals of the word line drive circuit having an inverted arrangement pattern are connected to memory cells so as to be aligned in the same order as in output terminals of the word line drive circuit having a non-inverted arrangement pattern.

Abstract: The semiconductor device of the present invention utilizes pairs of compensation capacitors serially connected between corresponding pairs of bit lines and interconnected to a ground line of a sense amplifier driver, so that the transistional potential change in the ground line due to reading out current from adjacent memory cells is restricted, thereby eliminating the delay in the level change of the bit lines, thus enabling high speed access.

Abstract: A semiconductor integrated circuit includes a circuit block whose operation is controlled by a inverted control signal whose significant potential level is set at a ground potential, and a wiring for transmitting a control signal for controlling the operation of the circuit block. An inverting circuit provided near the circuit block inverts the control signal and then supplies the inverted signal to the circuit block via a wiring. The inverter includes a first capacitor connected between the power source terminal and a node which is set at a high potential level in the inverter circuit when the control signal is set at the non-significant potential level and a second capacitor connected between a ground potential terminal and a node which is set at a ground potential level when the control signal is set at the non-significant potential level.

Abstract: A semiconductor integrated circuit device chip mounts a group of voltage amplifier circuits and a group of output transistors on the surface thereof. The group of voltage amplifier circuits are arranged at an area remote from the group of output transistors on the chip to prevent the voltage amplifiers from operating erroneously due to a potential variation caused by a switching operation of the output transistors.

Abstract: A dual-port memory device is provided which has a memory array divided approximately in half. The bit lines for the array are crossed over between array halves in order to minimize stray capacitance and cross-coupling capacitance for the device. Redundant rows are provided for the device which can be programmed to substitute for array rows containing non-functional bits. Preferably, the redundant rows are provided only in one-half of the array. The redundant rows can all be located in a first half of the array, with the second half of the array being the half which provides inverted data for one of the ports. If a redundant row replaces an array row in the second half of the array, and is written to by the port which reads and writes inverted data, the data must be reinverted prior to writing it to, or reading it from, the redundant row.

Abstract: The present invention provides an architecture of a DRAM cell array having a plurality of bit lines and word lines. The word lines are formed by arranging metal word lines on poly-silicon word lines in parallel, and two bit lines construct a column. The metal word lines and the poly-silicon word lines are contacted to each other every predetermined column. The contacts form metal shunted areas of word lines in a high bit density semiconductor device. In the present invention, the two bit lines that are located in the vicinity of metal shunted area are conjoined together in order to construct a column, and the column is connected to a bit line sense amplifier.

Abstract: A memory arrangement is comprised of a plurality of memory chips, and address and control lines connected to the chips. In order to minimize the effect of interference of signals from the address lines on the control lines, the address lines coupled to a portion of the chips carry address signals in inverted form, as compared with the address signals applied to the remainder of the chips, whereby interference signals of opposite polarity are induced in the control lines and cancel each other.

Abstract: In a semiconductor device having a signal line on which a voltage higher than the voltage supply is generated, a conductive layer following the potential variance of the voltage supply is positioned under an insulating film directly below the signal line in order to make the level of the signal line follow the potential variance of the voltage supply.

Abstract: The signal-to-noise ratio as measured by the ratio of the full select magnetic field levels to the half select magnetic field levels, is improved in a coincident current magnetic printing head by providing means for producing a bias magnetic field which is at least somewhat opposed to the signal magnetic fields.

Abstract: A third conductor is added to a pair of first and second parallel conductors transmitting signals, a part of which conductors are located in an alternating magnetic field. The three conductors are so arranged that the first and third conductors are symmetrical with respect to the center line of the second conductor, and the first and third conductors are interconnected at both extremities thereof.