Differential Sensing Patents (Class 365/207)
  • Patent number: 11450365
    Abstract: An input/output circuit including: an input circuit configured to load differential input data to setup nodes based on a data strobe clock; an output circuit configured to compare and amplify the data loaded to the setup nodes, and output differential output data; and a voltage retention circuit configured to retain the setup nodes at voltage levels corresponding to the differential output data, based on the data strobe clock and the differential output data.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: September 20, 2022
    Assignee: SK hynix Inc.
    Inventor: Joo Hyung Chae
  • Patent number: 11450375
    Abstract: In some examples, a subword driver block of a memory device includes a plurality of active regions of a first type and a plurality of active regions of a second type adjacent to the plurality of active regions of the first type. The subword driver block further includes a plurality of first gate electrodes overlapping with the plurality of active regions of the first type to form a plurality of first transistors, and a plurality of second gate electrodes overlapping with the plurality of active regions of the first type to form a plurality of second transistors. Each of the second transistors is shared by a first subword driver and a second subword driver. Each of the second transistors may include a drain and a source respectively coupled to a first and second word line, which are driven by the first subword driver and the second subword driver, respectively.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Takefumi Shirako, Masahiro Yokomichi, Kyuseok Lee, Sangmin Hwang
  • Patent number: 11423956
    Abstract: The present invention provides a sensitivity amplifier, its control method, a memory read-write circuit and a memory device. The sensitivity amplifier includes: a first PMOS transistor and a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, a first input/output terminal, and a second input/output terminal; four switch unit, the first PMOS and the first NMOS transistors are respectively connected to the first input/output terminal through one switch unit, the second PMOS and the second NMOS transistors are respectively connected to the second input/output terminal through another switch unit. The switch units configure each PMOS transistor and each NMOS transistor in an amplifier mode or in a diode mode. The first NMOS transistor's gate connects to the bit line, and the second NMOS transistor's gate connects to the reference bit line. The disclosed sensitivity amplifier has improved performance.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 23, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: WeiBing Shang, KanYu Cao
  • Patent number: 11423957
    Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and a control module, electrically connected to the amplification module; wherein, in an offset compensation stage of the sense amplifier, the control module is used to configure the amplification module to comprise a diode structure, a current mirror structure, and an inverter with an input and an output connected together; and in a first amplification stage of the sense amplifier, the control module is used to configure the amplification module as an inverter. The present disclosure can realize the offset compensation of the sense amplifier, thereby improving the performance of semiconductor memories.
    Type: Grant
    Filed: December 25, 2020
    Date of Patent: August 23, 2022
    Assignees: ANHUI UNIVERSITY, CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Chunyu Peng, Junlin Ge, Jun He, Zhan Ying, Xin Li, Kanyu Cao, Wenjuan Lu, Zhiting Lin, Xiulong Wu, Junning Chen
  • Patent number: 11410724
    Abstract: A semiconductor device is provided. The device includes a memory that stores data in a non-volatile and volatile manner and a memory controller configured to control the memory. The memory includes a word line pair including a first and second word line, a first bit line pair orthogonal to the first and the second word line and including a first bit line and a first complementary bit line, and a memory cell pair including first and second memory cells adjacent to the first memory cell in a word line direction. A left node of the first memory cell, and a right node of the first memory cell and a left node of the second memory cell, are all connected to the first word line, and a value of the data stored in the memory cell pair in the non-volatile manner is determined according to the selected first word line.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: August 9, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongsoo Lee, Daehyun Kim, Guyeon Wei
  • Patent number: 11410720
    Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: August 9, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Lava Kumar Pulluru, Ankur Gupta, Parvinder Kumar Rana
  • Patent number: 11404114
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 11386936
    Abstract: A memory device for sensing memory cell in a memory array includes at least one first memory cell, a first sensing amplifier, a first multiplexer circuit, a plurality of first reference cells, and a controller. The first sensing amplifier is coupled to the at least one first memory cell. An output terminal of the first multiplexer circuit is coupled to the reference terminal of the first sensing amplifier. Each of the first reference cells is coupled to each input node of the first multiplexer circuit. The controller is coupled to a control terminal of the first multiplexer circuit. The first sensing amplifier comprises an output terminal and a reference terminal. The controller controls the first multiplexer circuit to select one of the first reference cells as a selected reference cell to couple to the reference terminal of the first sensing amplifier when each read operation to the at least one first memory cell is performed.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hiroki Noguchi, Ku-Feng Lin, Yih Wang
  • Patent number: 11372026
    Abstract: A resistance measuring device includes an amplifying unit including an amplifier, a first and a second current supply unit, a voltage detection unit, and a controller. The controller controls the voltage detection unit to detect a first output voltage of an output terminal of the amplifier in a state where the current of the first current source flows in a forward direction to a measurement target resistor by controlling the first current supply unit, controls the voltage detection unit to detect a second output voltage of the output terminal of the amplifier in a state where the current of the second current source flows in a reverse direction to the measurement target resistor by controlling the second current supply unit, and calculates a resistance value of the measurement target resistor based on the detected first output voltage and the detected second output voltage.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: June 28, 2022
    Assignee: Ulsan National Institute of Science and Technology
    Inventors: Jae Joon Kim, Subin Choi
  • Patent number: 11368332
    Abstract: A circuit device includes: a first physical layer circuit to which a first bus compliant with a USB standard is connected; a second physical layer circuit to which a second bus compliant with the USB standard is connected; a processing circuit that performs transfer processing in which a packet received from the first bus via the first physical layer circuit is transferred to the second bus via the second physical layer circuit, and a packet received from the second bus via the second physical layer circuit is transferred to the first bus via the first physical layer circuit; a bus monitor circuit that performs a monitor operation with respect to the first and second buses; and a bus switch circuit that switches on or off a connection between the first bus and the second bus based on a monitor result from the bus monitor circuit.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: June 21, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Yoshiyuki Kamihara, Ryuichi Kagaya, Toshimichi Yamada
  • Patent number: 11361141
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes receiving layout data representing information for manufacturing the semiconductor structure having a metal layer over a substrate. A first parasitic capacitance and a second parasitic capacitance are formed between the metal layer and the substrate. The method further includes determining a parasitic capacitance difference between a first region and a second region. The method further includes forming a dummy capacitor to minimize the parasitic capacitance difference. A system for manufacturing a semiconductor device is also provided.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsuan-Ming Huang, An Shun Teng, Mingni Chang, Ming-Yih Wang, Yinlung Lu
  • Patent number: 11307244
    Abstract: The present techniques disclose a logic gate for an adaptive voltage scaling monitor, the logic gate comprising an inverting output and further comprising an imbalance between the drive strength of an NMOS component and a PMOS component thereof, and wherein the imbalance is operable to cause a switching delay of the gate to be primarily dependent on one of the NMOS component or the PMOS component.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 19, 2022
    Assignee: Arm Limited
    Inventor: Rainer Herberholz
  • Patent number: 11255726
    Abstract: An optical sensor and a method having a high linearity digital controlling mechanism are provided. An optoelectronic component converts a light energy into a photocurrent. Then, the photocurrent flows to a current mirror and is amplified by a gain to form a charging current by the current mirror to charge a capacitor. A comparator compares a voltage of the capacitor with a reference voltage multiple times to generate a comparison signal. A counter determines a digital value capturing range according to the gain, and counts bit values that fall within the digital value capturing range from the comparison signal to output a counted signal. A noise cancellation processor reduces the digital value capturing range according to the gain, and removes one or more of the bit values that do not fall within the digital value capturing range from the counted signal to output a sensed signal.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 22, 2022
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventor: Jing-Min Chen
  • Patent number: 11228283
    Abstract: A circuit includes a first operational amplifier having an inverting input and a non-inverting input, and a negative resistance circuit connected to the inverting input of the operational amplifier. The negative resistance circuit includes a second operational amplifier, a current source controlled by the second operational amplifier, and a cross-coupled transistor circuit having at least one transistor biased by a current produced by the current source.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: January 18, 2022
    Assignee: MEDIATEK Singapore Pte. Ltd.
    Inventors: Taehoon Jeong, Patrick Cooney
  • Patent number: 11195468
    Abstract: A display apparatus includes a display panel, a first gate driver, a second gate driver, a third gate driver, and a data driver. The display apparatus is operable in a low frequency driving mode, and the low frequency driving mode includes a writing frame and a holding frame. At least one of gate power voltages used to generate a first gate signal, a second gate signal, and an emission signal has a first voltage level in the writing frame of the low frequency driving mode and a second voltage level in the holding frame of the low frequency driving mode. The data voltage is applied to the pixel in the writing frame of the low frequency driving mode. The data voltage applied to the pixel in the writing frame of the low frequency driving mode is maintained in the holding frame of the low frequency driving mode.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: December 7, 2021
    Inventors: Se Hyuk Park, Hong Soo Kim, Jin Young Roh, Hyo Jin Lee, Jae Keun Lim
  • Patent number: 11139022
    Abstract: An example of an apparatus includes a plurality of memory cells arranged in a plurality of NAND strings that are connected to a source line and a control circuit connected to the source line. The control circuit is configured to provide a first current to the source line to pre-charge the source line to a target voltage for sensing data states of the plurality of memory cells and provide a second current to the source line to return the source line to the target voltage in a recovery period between sensing data states. The control circuit is configured to provide the second current at any one of a plurality of current levels.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: October 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Kou Tei, Ohwon Kwon, Jongyeon Kim, Chia-Kai Chou, Yuedan Li
  • Patent number: 11087819
    Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, Dean D. Gans, Jiyun Li, Nathaniel J. Meier, Randall J. Rooney
  • Patent number: 11069411
    Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: July 20, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Patent number: 11068639
    Abstract: Various implementations described herein refer to a method. The method may include providing a metal layout for an integrated circuit, wherein the metal layout includes multiple lines associated with bitlines. The method may include inserting at least one additional line between the multiple lines and the bitlines. The method may include arranging the at least one additional line with respect to the multiple lines and the bitlines so as to reduce capacitance associated with the bitlines.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: July 20, 2021
    Assignee: Arm Limited
    Inventors: Marlin Wayne Frederick, Jr., Ettore Amirante, Ronald Paxton Preston, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong
  • Patent number: 11018687
    Abstract: A time-multiplexed group of MAC circuits for a machine learning application is provided in which at least one MAC circuit in the time-multiplexed group also functions as a capacitive-digital-to-analog converter (CDAC) within a successive approximation analog-to-digital converter (ADC). A comparator in the ADC is shared by the time-multiplexed group of MAC circuits.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: May 25, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Ankit Srivastava, Seyed Arash Mirhaj
  • Patent number: 11017843
    Abstract: In memory devices where a memory cell includes a thin film cell select transistor, selection between layers of such memory cells may further comprise another thin film select transistor. Bitline and wordline encoding suitable for a memory device having a single layer of memory cells may be scaled up to a 3D memory device having two or more memory cell layers. In a DRAM device one layer of (1TFT-1C) cells may include a 2D array of metal-insulator-metal capacitors over an array of TFTs. Additional layers of such 1TFT-1C cells may be stacked monolithically to form a 3D array. Memory cells in each layer may be accessed through a wordline and local bitline. A local bitline of one cell layer may be coupled to global bitline applicable to all cell layers through a layer-selected TFT according to a voltage applied to a layer-select gate voltage.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Sharma, Gilbert Dewey, Willy Rachmady, Van Le, Matthew Metz, Jack Kavalieros
  • Patent number: 10998031
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Patent number: 10990725
    Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Gabor Drasny, Gavin B. Meil
  • Patent number: 10984874
    Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
  • Patent number: 10969416
    Abstract: An integrated circuit including at least one circuit node, multiple duplicate circuit blocks integrated on the integrated circuit in close proximity with each other, each including at least one device that is susceptible to random telegraph noise (RTN), and a switch circuit that swaps electrical coupling of the duplicate circuit blocks, one at a time, to the at least one circuit node in sequential cycles of a clock signal. The duplicate circuit blocks may be large functional blocks, such as an oscillator or a comparator or the like, or limited to circuits including RTN susceptible devices, such as differential pairs or the like. Each duplicate circuit block may include any number of connections for coupling to corresponding circuit nodes. The swapping may further include chopping in which multiple inputs are swapped with each other while multiple outputs are swapped with each other in consecutive clock cycles.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 6, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: Vitor Pereira, Arup Mukherji
  • Patent number: 10965301
    Abstract: Included are a loop filter, a quantization circuit section, and a current steering digital-analog conversion section. The quantization circuit section converts a loop filter output into a digital value. The current steering digital-analog conversion section is provided in a feedback loop that feeds back the output of the quantization circuit section to the loop filter. Then, each of the analog-digital converters includes a first input signal current path, a second input signal current path, a first feedback current path, and a second feedback current path. The first input signal current path feeds a first input signal current to an input end of a first stage integrator of the loop filter. The second input signal current path feeds a second input signal current, a current opposite in sign to the first input signal current, to an input end of a second stage integrator of the loop filter.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: March 30, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takashi Moue, Takashi Matsumoto
  • Patent number: 10957382
    Abstract: Some embodiments include an integrated assembly having a base with sense-amplifier-circuitry. A first deck is over the base, and includes a first array of first memory cells. A second deck over the first deck, and includes a second array of second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 10937655
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and peripheral circuits configured to sequentially program the pages. The memory device may include control logic configured to control the peripheral circuits such that a program voltage is applied to a word line coupled to a page selected from among the pages such that different pass voltages are applied to all or some word lines coupled to pages on which a program operation has been performed among unselected pages other than the selected page, and to word lines coupled to pages on which a program operation has not been performed among the unselected pages.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10937496
    Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chung H. Lam, Scott C. Lewis, Thomas M. Maffitt, Jack Morrish
  • Patent number: 10923194
    Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 16, 2021
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
  • Patent number: 10867652
    Abstract: In some embodiments, the present application provides a memory device. The memory device includes a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The MTJ memory cell includes an MTJ memory element and a first access transistor. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first current mirror transistor. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gaurav Gupta, Zhiqiang Wu
  • Patent number: 10868234
    Abstract: A storage device includes: a plurality of first magnetic tunnel junction (MTJ) cells disposed on a first portion of a substrate; and a plurality of second MTJ cells disposed on a second portion different from the first portion of the substrate; wherein each of the plurality of first MTJ cells has a first cross-sectional surface area viewing from a top of the substrate, each of the plurality of second MTJ cells has a second cross-sectional surface area viewing from the top of the substrate, and the second cross-sectional surface area is greater than the first cross-sectional surface area.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Chang-Hung Chen, Kuei-Hung Shen, Wen-Chun You, Tien-Wei Chiang
  • Patent number: 10847238
    Abstract: An analog content addressable memory cell includes a high side and a low side. The high side encodes a high bound on a range of values and includes a first voltage divider formed of a first programmable resistor and a first electronically controlled variable resistor. The low side encodes a low bound on the range of values and includes a second voltage divider formed of a second programmable resistor and a second electronically controlled variable resistor.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 24, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Patent number: 10754807
    Abstract: A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus that comply with a USB standard on in a first period and off in a second period, and a processing circuit that performs, in the second period, packet transfer processing on a transfer route that includes the first bus, the first and second physical layer circuits, the second bus. The bus switch circuit includes a first switch circuit, a second switch circuit, and a signal line connected between the first switch circuit and the second switch circuit.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 25, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Toshimichi Yamada
  • Patent number: 10726898
    Abstract: A sense amplifier circuit for sensing a data state of a data cell during a read cycle is described. The circuit includes a first stage with first circuitry to output a reference voltage and a data voltage relating to the data state of the data cell. The circuit further includes a second stage with circuitry to amplify a difference between the reference voltage and the data voltage. This circuitry includes a plurality of inverters and a plurality of capacitors. The read cycle includes a compensation phase. During the compensation phase the circuitry stores, at the capacitors, a voltage difference caused by a device mismatch of the inverters. After the compensation phase the circuitry amplifies the difference between the reference voltage and the data voltage, and compensates for the device mismatch using the stored voltage difference at the capacitors.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Thomas Martin Maffitt, John Kenneth Debrose
  • Patent number: 10726191
    Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes receiving layout data representing mask information for manufacturing a semiconductive substrate with a conductor over the semiconductive substrate. A first capacitor is formed between the conductor and the semiconductive substrate. The method further includes determining a capacitance difference between capacitances of the first capacitor and a neighboring capacitor. The method further includes forming a dummy capacitor to minimize the capacitance difference. A system for manufacturing a semiconductor device is also provided.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsuan-Ming Huang, An Shun Teng, Mingni Chang, Ming-Yih Wang, Yinlung Lu
  • Patent number: 10726901
    Abstract: A memory cell within an integrated-circuit memory component receives a first control signal that transitions between supply voltage levels of a first voltage domain and a second control signal that transitions between supply voltage levels of a second voltage domain different from the first voltage domain. In response to the transitions of the first and second control signal, output-enable circuitry within the memory cell transitions an output-enable signal between one of the supply voltage levels of the first voltage domain and one of the supply voltage levels of the second voltage domain to enable output signal generation on an output signal line coupled to the memory cell.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 28, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt
  • Patent number: 10643716
    Abstract: A nonvolatile memory device includes a plurality of memory cells coupled to a single bit line, wherein each of the plurality of memory cells is coupled to a different word line from a plurality of word lines. The nonvolatile memory device includes a decoder configured to sequentially apply a read voltage of a first level to target word lines among the word lines, based on a multi-read command. The nonvolatile memory device includes a read circuit configured to obtain first sensing values of target memory cells coupled to the target word lines, by sensing the bit line each time the read voltage of the first level is applied to each of the target word lines.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventor: Sok Kyu Lee
  • Patent number: 10622035
    Abstract: A sense amplifier includes a first sample and hold circuit, a second sample and hold circuit, a latch-type amplifier. The first sample and hold circuit is coupled to a bit line and configured to sample and hold memory cell data during a pre-charge phase of a sensing operation. The second sample and hold circuit is coupled to a reference bit line and configured to sample and hold data of a reference memory cell data during the pre-charge phase of the sensing operation. The latch-type amplifier, coupled to the first sample and hold circuit and the second sample and hold circuit, and configured to compare the memory cell data and the reference cell data during an evaluation phase of the sensing operation to output a sensing signal. The sense amplifier is isolated from the bit line and the reference bit line during the evaluation phase of the sensing operation. A sensing method adapted to a sense amplifier and a non-volatile memory include a sense amplifier are also introduced.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chang Yu, Ta-Ching Yeh
  • Patent number: 10622066
    Abstract: A resistive memory device according to an example embodiment of the inventive concepts includes: a cell array including a first section and a second section; a first column switch circuit connected to a memory cell and a reference cell of the first section through first bit lines; a second column switch circuit connected to a memory cell and a reference cell of the second section through second bit lines; and a column decoder configured to control the first and second column switch circuits such that one of the first bit lines connected to the memory cell and one of the second bit lines connected to the reference cell are selected according to a first column address, and one of the first bit lines connected to the reference cell and one of the second bit lines connected to the memory cell are selected according to a second column address.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Artur Antonyan
  • Patent number: 10545724
    Abstract: A controller for granting a user input device control of a controllable device including a receiver arranged for receiving a first sound signal recorded within a first time frame by a first sound sensor and receiving a second sound signal recorded within a second time frame by a second sound sensor located at the user input device. The controller further includes a processor arranged for determining a level of similarity between the first sound signal and the second sound signal. The processor is further arranged for granting the user input device control of the controllable device if a sufficient level of similarity has been determined. This enables the controller to determine if the user input device is in the same space as the first sound sensor, and it allows the creation of a control space of the controllable device based on the characteristics of the first sound sensor.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 28, 2020
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Adrianus Johannes Stephanus Maria De Vaan, Jan Van Wijgerden, Johan-Paul Marie Gerard Linnartz
  • Patent number: 10535379
    Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: January 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Darren L. Anand, John A. Fifield, Eric D. Hunt-Schroeder, Mark D. Jacunski
  • Patent number: 10523126
    Abstract: This present invention comprises the multiple power sections and a multi-input operational amplifier, wherein the pilot device places at the different location of the main power MOSFET form multiple individual power section, the multi-input operational amplifier drives a transistor to detect the overall current of each power section furthermore report the overall current to system.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 31, 2019
    Assignee: DONGGUAN CHANGGONG MICROELECTRONICS LTD
    Inventors: Xuening Li, Guanghua Ye
  • Patent number: 10490235
    Abstract: A read-only memory (ROM) device includes a memory cell that is electrically coupled to a bitline (BL) or to a BL which represents a complement of the BL. The ROM device precharges the BL and the BL to a first logical value. The ROM device activates the memory cell which discharges the BL when the memory cell is coupled to the BL or discharges the BL when the memory cell is coupled to the BL. The ROM device reads the first logical value as being stored within the memory cell when the BL is less than the BL. Otherwise, the ROM device reads the second logical value as being stored within the memory cell when the BL is greater than the BL.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuoyuan Hsu, Jacklyn Chang
  • Patent number: 10482962
    Abstract: A ternary content addressable memory (TCAM) device includes a memory cell. The memory cell includes a data storage circuit, a limiter circuit, and a discharge circuit. The data storage circuit includes a first resistor and a second resistor connected in series to divide a voltage corresponding to search data, and configured to store cell data. The limiter circuit is configured to receive the divided voltage through an input terminal and transmit an output voltage through an output terminal based on a level of the divided voltage. The discharge circuit discharges a matching line indicating whether the stored cell data matches with the search data, based on the output voltage of the limiter circuit.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 19, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Research & Business Foundation, Sungkyunkwan Univ.
    Inventors: Cheol Kim, Hyun-Suk Kang, Kee-Won Kwon, Rak-Joo Sung, Sung-Gi Ahn
  • Patent number: 10468371
    Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having comprising a hole and a conductive layer surrounding the hole, the conductive layer including a first connection point and a second connection point that are located so that a straight line between the first connection point and the second connection point crosses over the hole; an external terminal coupled to the first connection point of the conductive layer of the connection wiring; and an internal circuit coupled to the second connection point of the conductive layer of the connection wiring.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Ken Ota
  • Patent number: 10431283
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Patent number: 10388355
    Abstract: A memory cell within an integrated-circuit memory component receives a first control signal that transitions between supply voltage levels of a first voltage domain and a second control signal that transitions between supply voltage levels of a second voltage domain different from the first voltage domain. In response to the transitions of the first and second control signal, output-enable circuitry within the memory cell transitions an output-enable signal between one of the supply voltage levels of the first voltage domain and one of the supply voltage levels of the second voltage domain to enable output signal generation on an output signal line coupled to the memory cell.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 20, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt
  • Patent number: 10361093
    Abstract: A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Eduard A. Cartier, Chandrasekharan Kothandaraman
  • Patent number: 10354705
    Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a plurality of sense amplifier control circuits coupled to a plurality of corresponding sense amplifiers, wherein each sense amplifier control circuit of the plurality of sense amplifier control circuits provides one or more control signals to a corresponding sense amplifier of a plurality of sense amplifiers; and a driver that provides a selection signal to a plurality of word drivers responsive, at least in part, to a first control signal that is responsive to the one or more control signals from the plurality of sense amplifier control circuits.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Takeshi Ohgami