Abstract: In some aspects of the present disclosure, a memory array includes: a plurality of memory cells; and a plurality of logic gates, each of the plurality of logic gates having a first input, a second input, and an output gating a corresponding one of the plurality of memory cells, wherein the first input of each of the plurality of logic gates of a first subset is coupled to a first bit select line.

Abstract: Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.

Abstract: Fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. Fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. The fuse arrays can be fabricated and then programmed to cause different delays for different dies.

Abstract: A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through tis second and third transistors.

Abstract: The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. An embodiment includes a memory having a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells, and circuitry configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.

Abstract: A circuit includes a reference voltage node, first and second data lines, a sense amplifier, first and second switching devices coupled between the first and second data lines and first and second input terminals of the sense amplifier, third and fourth switching devices coupled between the first and second data lined and first and second nodes, fifth and sixth switching devices coupled between the first and second nodes and the reference voltage node, and first and second capacitive devices coupled between the first and second nodes and second and first input terminals. Each of the first through fourth switching devices is switched on and each of the fifth and sixth switching devices is switched off in a first operational mode, and each of the first through fourth switching devices is switched off and each of the fifth and sixth switching devices is switched on in a second operational mode.

Abstract: Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect, an integrated circuit includes: a latch circuit including a latch and a sensing transistor coupled to the latch, and a compensation circuit coupled to the sensing transistor. The sensing transistor includes a gate terminal coupled to a sensing node and an additional terminal coupled to the compensation circuit, and the compensation circuit is configured to apply a control voltage to the additional terminal to compensate for a variation of a threshold voltage of the sensing transistor.

Abstract: One implementation described herein is related to a device having memory with sense amplifiers and precharge blocks arranged in an array with a first side and a second side. The first side has first sense amplifiers and first precharge blocks coupled together with first bitlines, and the second side has second sense amplifiers and second precharge blocks coupled together with second bitlines. The device has a first delay block coupled to the first precharge blocks in the first side of the array, and the first delay block delays precharge of the first bitlines with a first precharge burst in a multi-burst precharge event. The device has a second delay block coupled to the second precharge blocks in the second side of the array, and the second delay block delays precharge of the second bitlines with a second precharge burst in the multi-burst precharge event.

Abstract: Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.

Abstract: Disclosed are a method and apparatus for determining mismatch of a sense amplifier, a storage medium, and an electronic equipment, relating to the field of integrated circuit technology. The method for determining mismatch of a sense amplifier includes: determining a first signal threshold on a first bit line when a first memory cell executes write and read operations; determining a second signal threshold on a second bit line when a second memory cell executes write and read operations; and determining, according to the first signal threshold and the second signal threshold, whether the sense amplifier is mismatched. A method for determining whether the sense amplifier is mismatched is provided.

Abstract: Methods, systems, and devices for techniques for memory cell refresh are described. A memory system may support a low power mode in which the memory system may periodically perform a refresh operation. In some cases, the memory system and a host system coupled with the memory system may support a command to enter the low power mode. As part of the low power mode, the memory system may receive at least one power supply of one or more supported power supplies, such that the memory system may remain active and thus periodically perform the refresh operation. In some cases, the memory system may adjust the periodicity of the refresh operation in response to detecting a triggering event, such as a high temperature, a large system age, or a combination thereof.

Abstract: The disclosure provides a Sense Amplifier (SA), a memory and a method for controlling the SA, and relates to the technical field of semiconductor memories. The SA includes: an amplifier module; an offset voltage storage unit electrically connected to the amplifier module and configured to store an offset voltage of the amplifier module in an offset elimination stage of the SA; and a load compensation unit electrically connected to the amplifier module and configured to compensate a difference between loads of the amplifier module in an amplification stage of the SA. The disclosure may improve an accuracy of reading data of the SA.

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.

Abstract: A method and a device for testing a memory chip are provided. The method includes: writing test data into memory cells of a memory chip to-be-tested; reading stored data from the memory cells; and generating a test result of the memory chip to-be-tested according to the test data and the stored data; a word line turn-on voltage tested in the memory chip to-be-tested being greater than a standard bit line and word line turn-on voltage of the memory chip to-be-tested, and/or a sense amplification time tested in the memory chip to-be-tested being greater than a standard sense amplification time of the memory chip to-be-tested.

Abstract: An integrated circuit is provided. The integrated circuit includes: a first data line group, including a plurality of local data lines arranged in an array; a second data line group, including a plurality of complementary local data lines arranged in an array, the plurality of complementary local data lines and the plurality of local data lines respectively transmitting signals having opposite phases; and a plurality of read circuits, configured to read, in response to a read control signal, signals of the local data lines or the complementary local data lines during a read operation, each of the plurality of read circuits being electrically connected to a local data line at a boundary of the first data line group or connected to a complementary local data line at a boundary of the second data line group.

Abstract: Apparatuses for controlling power supply to sense amplifiers are described. An example apparatus includes a bank. The bank includes: a first plurality of memory cells; a second plurality of memory cells; first sense amplifiers coupled to the first plurality of memory cells; second sense amplifiers coupled to the second plurality of memory cells; a first power control circuit and a coupled to the first sense amplifiers at a common power supply node; and a second power control circuit coupled to the second sense amplifiers at the common power supply node. The first and second power control circuits receive a plurality of control signals. The first and second power control circuits comprise first and second drive strengths respectively responsive to activation of a control signal of the plurality of control signals. The first drive strength and the second drive strength are different from each other.

Abstract: A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

Abstract: A three-dimensional memory device, such as 3D AND Flash memory device, includes a first page buffer, a second page buffer, a sense amplifier, a first path selector, and a second path selector. The first page buffer and the second page buffer are respectively configured to temporarily store a first write-in data and a second write-in data. The first path selector couples the sense amplifier or the first page buffer to a first global bit line according to a first control signal. The second path selector couples the sense amplifier or the second page buffer to a second global bit line according to a second control signal.

Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal.

Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

Abstract: A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.

Abstract: The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.

Abstract: A sense amplifier includes: an amplification circuit, configured to read data of a memory cell on a first bit line or a second bit line; and a first offset voltage storage cell and a second offset voltage storage cell, respectively and electrically connected to the amplification circuit, wherein in a case where the data in the memory cell on the first bit line is read, in an offset elimination stage of the sense amplifier, the sense amplifier is configured to store an offset voltage of the sense amplifier in the first offset voltage storage cell; and in a case where the data in the memory cell on the second bit line is read, in the offset elimination stage of the sense amplifier, the sense amplifier is configured to store the offset voltage of the sense amplifier in the second offset voltage storage cell.

Abstract: According to one embodiment, a semiconductor memory device includes the following structure. A memory array is provided on a first-direction side of a substrate. The first direction intersects the substrate. The first peripheral circuit is provided between the substrate and the memory array. The second peripheral circuit is provided between the substrate and the memory array and on a second-direction side of the first peripheral circuit. The second direction intersects the first direction. The sense amplifier is provided between the substrate and the memory array and between the first and second peripheral circuits. A second-direction length of the second peripheral circuit is smaller than half a second-direction length of the sense amplifier.

Abstract: A comparison circuit includes a reference adjustment module, a signal receiving module, and a control module. The reference adjustment module is configured to receive a first reference signal and output a second reference signal. The reference adjustment module is further configured to receive an adjustment signal, and unidirectionally adjust the equivalent coefficient within a preset value interval when the adjustment signal is received. The signal receiving module is configured to receive the second reference signal and an external signal. The control module is configured to: receive an enable signal and the comparison signal; and during a period of continuously receiving the enable signal, when the comparison signal jumps, terminate the output of the adjustment signal.

Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

Abstract: At least one embodiment of the disclosure is directed to a memory circuit having a leakage current blocking mechanism and a memory device having the memory circuit. In an aspect, one embodiment of the disclosure describes a memory circuit which includes not limited to a memory array which includes a first memory cell connected to a first bit line and a second memory cell connected to a second bit line, a pre-charge circuit which is connected to the memory array and includes a first pre-charge device, and a programming circuit which is connected to the pre-charge circuit and comprises a programming transistor which has a higher drive capability than the first pre-charge device so as to drive the first bit line to a ground voltage in response to the first write operation, wherein in response to a first write operation on the first memory cell, a current flow exists between the programming circuit and the first pre-charge device.

Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.

Abstract: In some examples, this disclosure describes a method of operating a circuit. The method may comprise performing a circuit function under normal operating conditions, wherein performing the circuit function under the normal operating conditions includes performing at least a portion of the circuit functions via a characteristic circuit, performing at least the portion of the circuit function under enhanced stress conditions via a characteristic circuit replica, and predicting a potential future problem with the circuit function under the normal conditions based on an evaluation of operation of the characteristic circuit relative to operation of the characteristic circuit replica.

Abstract: Memory devices might include an array of memory cells, a plurality of access lines connected to the array of memory cells, a plurality of data lines connected to the array of memory cells, a plurality of shield lines, and control logic. The plurality of shield lines might be interleaved with the plurality of data lines. The control logic might be configured to implement a program verify operation of respective memory cells of the array of memory cells connected to a selected access line including charging the plurality of shield lines to a first voltage level, discharging the plurality of shield lines to a voltage level less than the first voltage level, and sensing a voltage level on each data line to determine whether each respective memory cell coupled to the selected access line has been programmed to a target level for the respective memory cell.

Abstract: Methods, systems, and devices for techniques to perform a sense operation are described. In some examples, a memory device may include a pair of transistor to precharge a digit line. A first transistor of the pair of transistors may be coupled with a first node and a second transistor of the pair of transistors may be coupled with a second node. In some cases, the first node and the second node may be selectively coupled via a transistor. The first and second transistors may be activated to precharge the first and second nodes. In some examples, a pulse may be applied to a capacitor coupled with the second node to transfer a charge to the digit line. In some cases, the cascode transistor may maintain or control the voltage of the digit line to be at or below an upper operating voltage of the memory cell.

Abstract: A data receiving circuit is provided. The data receiving circuit includes a data input circuit, a latch circuit, and an equalizer. The data input circuit is configured to receive an input signal, and the latch circuit is connected to the data input circuit and configured to output an output signal in response to the input signal. The equalizer includes a first transistor having a source connected to latch circuit; and a second transistor having a source connected to the latch circuit and a gate connected to a gate of the first transistor.

Abstract: The present disclosure relates to an electronic device. A memory device according to the present disclosure includes a memory block coupled to a plurality of local word lines, a peripheral circuit configured to couple the plurality of local word lines to a plurality of global word lines and configured to perform an operation on the memory block, and a control logic configured to control the peripheral circuit to cause or increase a leakage current of the pass switch circuit to discharge potential levels of the plurality of local word lines when the memory device enters a ready state after the operation.

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device.

Abstract: The present invention provides a dynamic comparator including a dynamic amplifier and a latch circuit. The dynamic amplifier includes a first input pair, a current source and a gain boosting circuit. The first input pair is configured to receive an input signal to generate an amplified signal at an output terminal. The current source is coupled between the first input pair and a first reference voltage. The gain-boosting circuit is coupled between the first input pair and a second reference voltage, and is configured to receive the input signal to selectively inject current to the output terminal or sink current from the output terminal. The latch circuit is coupled to the dynamic amplifier, and is configured to receive the amplified signal to generate an output signal.

Abstract: An embodiment method for smoothing consumed current is based on a current copying suite and on a current source supplying a reference current, the currents being transformed into a reference voltage for the regulation of a voltage regulator such that the consumed current viewed by the power supply only depends on the reference current.

Abstract: The present application provides a method for manufacturing a semiconductor die. The method includes forming dielectric layers on a substrate; forming decoupling capacitors in the dielectric layers; forming first and second bonding pads on the dielectric layers, wherein the first bonding pads are coupled to a power supply voltage, the second bonding pads are coupled to a reference voltage, a group of the decoupling capacitors are located under one of the first bonding pads, first terminals of the group of the decoupling capacitors are electrically connected to the one of the first bonding pads, second terminals of the group of the decoupling capacitors are routed to one of the second bonding pads; and forming bond metals on the first and second bonding pads, wherein the decoupling capacitors are overlapped with the first and second bonding pads, and laterally surround portions of the dielectric layers overlapped with the bond metals.

Abstract: Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.

Abstract: Apparatuses, systems, and methods for single-ended global and local input/output architecture. A conventional memory may use local input/output (LIO) and global input/output (GIO) lines which are paired and carry complimentary signals. The present disclosure includes single ended LIO and GIO architecture where a single LIO couples a single GIO between a read/write amplifier and bit line as part of an access operation. This may reduce a footprint of the memory device.

Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.

Abstract: Disclosed herein is an apparatus that includes a driver circuit including a plurality of first transistors arranged in a first direction; a control circuit including a plurality of second transistors arranged in parallel to the plurality of first transistors, each of the plurality of second transistors being coupled to control an associated one of the first transistors; and a power gating circuit arranged between the driver circuit and the control circuit, the power gating circuit being configured to supply a first power potential to each of the plurality of first transistors.

Abstract: A semiconductor device includes a memory mat having: a plurality of memory cells; a sense amplifier connected to a memory cell selected from the plurality of memory cells; a first power supply wiring; a first switch connected between the sense amplifier and the first power supply wiring and made an ON state in operating the sense amplifier; and a second switch connected to the sense amplifier and made an ON state in operating the sense amplifier, a second power supply wiring arranged outside the memory mat and connected to the first power supply wiring, a third power supply wiring arranged outside the memory mat and connected to the sense amplifier via the second switch, and a short switch arranged outside the memory mat and connected between the second and third power supply wirings. Here, in operating the sense amplifier, the short switch is made an ON state.

Abstract: A memory controller configured to control a non-volatile memory device includes: a signal generator configured to generate a plurality of control signals comprising a first signal and a second control signal; a core configured to provide a command for an operation of the non-volatile device; and a controller interface circuit configured to interface with the non-volatile memory device, wherein the controller interface circuit comprises a first transmitter connected to a first signal line and a second signal line; and a first receiver connected to the first signal line, and the first control signal and the second control signal are respectively transmitted to the non-volatile memory device through the first signal line and the second signal line.

Abstract: Receiver circuitry for a communication system includes signal processing circuitry, voltage digital-to-analog converter (DAC) circuitry, and slicer circuitry. The signal processing circuitry receives a data signal and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage. The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage. The CapFF circuit further generates a first data signal. The first CapFF circuit includes a first offset compensation circuit that adjusts a parasitic capacitance of the first CapFF circuit.

Abstract: An amplifier system includes a differential amplifier and a calibration circuit. In response to a calibration operation, the calibration circuit generates a calibration value based on a test output signal generated by the differential amplifier circuit using a test input signal. The calibration value may be used to adjust loading of internal nodes of the differential amplifier circuit to compensate for imbalance in the differential amplifier circuit resulting from variation in manufacturing. By compensating for the imbalance, the offset of the differential amplifier may be reduced, allowing resolution of smaller differential voltages, thereby improving the performance of circuits employing the differential amplifier circuit.

Abstract: In some aspects of the present disclosure, a memory array includes: a plurality of memory cells; and a plurality of logic gates, each of the plurality of logic gates having a first input, a second input, and an output gating a corresponding one of the plurality of memory cells, wherein the first input of each of the plurality of logic gates of a first subset is coupled to a first bit select line.