Differential Sensing Patents (Class 365/207)
  • Patent number: 10754807
    Abstract: A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus that comply with a USB standard on in a first period and off in a second period, and a processing circuit that performs, in the second period, packet transfer processing on a transfer route that includes the first bus, the first and second physical layer circuits, the second bus. The bus switch circuit includes a first switch circuit, a second switch circuit, and a signal line connected between the first switch circuit and the second switch circuit.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 25, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Toshimichi Yamada
  • Patent number: 10726901
    Abstract: A memory cell within an integrated-circuit memory component receives a first control signal that transitions between supply voltage levels of a first voltage domain and a second control signal that transitions between supply voltage levels of a second voltage domain different from the first voltage domain. In response to the transitions of the first and second control signal, output-enable circuitry within the memory cell transitions an output-enable signal between one of the supply voltage levels of the first voltage domain and one of the supply voltage levels of the second voltage domain to enable output signal generation on an output signal line coupled to the memory cell.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 28, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt
  • Patent number: 10726191
    Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes receiving layout data representing mask information for manufacturing a semiconductive substrate with a conductor over the semiconductive substrate. A first capacitor is formed between the conductor and the semiconductive substrate. The method further includes determining a capacitance difference between capacitances of the first capacitor and a neighboring capacitor. The method further includes forming a dummy capacitor to minimize the capacitance difference. A system for manufacturing a semiconductor device is also provided.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsuan-Ming Huang, An Shun Teng, Mingni Chang, Ming-Yih Wang, Yinlung Lu
  • Patent number: 10726898
    Abstract: A sense amplifier circuit for sensing a data state of a data cell during a read cycle is described. The circuit includes a first stage with first circuitry to output a reference voltage and a data voltage relating to the data state of the data cell. The circuit further includes a second stage with circuitry to amplify a difference between the reference voltage and the data voltage. This circuitry includes a plurality of inverters and a plurality of capacitors. The read cycle includes a compensation phase. During the compensation phase the circuitry stores, at the capacitors, a voltage difference caused by a device mismatch of the inverters. After the compensation phase the circuitry amplifies the difference between the reference voltage and the data voltage, and compensates for the device mismatch using the stored voltage difference at the capacitors.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Thomas Martin Maffitt, John Kenneth Debrose
  • Patent number: 10643716
    Abstract: A nonvolatile memory device includes a plurality of memory cells coupled to a single bit line, wherein each of the plurality of memory cells is coupled to a different word line from a plurality of word lines. The nonvolatile memory device includes a decoder configured to sequentially apply a read voltage of a first level to target word lines among the word lines, based on a multi-read command. The nonvolatile memory device includes a read circuit configured to obtain first sensing values of target memory cells coupled to the target word lines, by sensing the bit line each time the read voltage of the first level is applied to each of the target word lines.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventor: Sok Kyu Lee
  • Patent number: 10622035
    Abstract: A sense amplifier includes a first sample and hold circuit, a second sample and hold circuit, a latch-type amplifier. The first sample and hold circuit is coupled to a bit line and configured to sample and hold memory cell data during a pre-charge phase of a sensing operation. The second sample and hold circuit is coupled to a reference bit line and configured to sample and hold data of a reference memory cell data during the pre-charge phase of the sensing operation. The latch-type amplifier, coupled to the first sample and hold circuit and the second sample and hold circuit, and configured to compare the memory cell data and the reference cell data during an evaluation phase of the sensing operation to output a sensing signal. The sense amplifier is isolated from the bit line and the reference bit line during the evaluation phase of the sensing operation. A sensing method adapted to a sense amplifier and a non-volatile memory include a sense amplifier are also introduced.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chang Yu, Ta-Ching Yeh
  • Patent number: 10622066
    Abstract: A resistive memory device according to an example embodiment of the inventive concepts includes: a cell array including a first section and a second section; a first column switch circuit connected to a memory cell and a reference cell of the first section through first bit lines; a second column switch circuit connected to a memory cell and a reference cell of the second section through second bit lines; and a column decoder configured to control the first and second column switch circuits such that one of the first bit lines connected to the memory cell and one of the second bit lines connected to the reference cell are selected according to a first column address, and one of the first bit lines connected to the reference cell and one of the second bit lines connected to the memory cell are selected according to a second column address.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Artur Antonyan
  • Patent number: 10545724
    Abstract: A controller for granting a user input device control of a controllable device including a receiver arranged for receiving a first sound signal recorded within a first time frame by a first sound sensor and receiving a second sound signal recorded within a second time frame by a second sound sensor located at the user input device. The controller further includes a processor arranged for determining a level of similarity between the first sound signal and the second sound signal. The processor is further arranged for granting the user input device control of the controllable device if a sufficient level of similarity has been determined. This enables the controller to determine if the user input device is in the same space as the first sound sensor, and it allows the creation of a control space of the controllable device based on the characteristics of the first sound sensor.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 28, 2020
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Adrianus Johannes Stephanus Maria De Vaan, Jan Van Wijgerden, Johan-Paul Marie Gerard Linnartz
  • Patent number: 10535379
    Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: January 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Darren L. Anand, John A. Fifield, Eric D. Hunt-Schroeder, Mark D. Jacunski
  • Patent number: 10523126
    Abstract: This present invention comprises the multiple power sections and a multi-input operational amplifier, wherein the pilot device places at the different location of the main power MOSFET form multiple individual power section, the multi-input operational amplifier drives a transistor to detect the overall current of each power section furthermore report the overall current to system.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 31, 2019
    Assignee: DONGGUAN CHANGGONG MICROELECTRONICS LTD
    Inventors: Xuening Li, Guanghua Ye
  • Patent number: 10490235
    Abstract: A read-only memory (ROM) device includes a memory cell that is electrically coupled to a bitline (BL) or to a BL which represents a complement of the BL. The ROM device precharges the BL and the BL to a first logical value. The ROM device activates the memory cell which discharges the BL when the memory cell is coupled to the BL or discharges the BL when the memory cell is coupled to the BL. The ROM device reads the first logical value as being stored within the memory cell when the BL is less than the BL. Otherwise, the ROM device reads the second logical value as being stored within the memory cell when the BL is greater than the BL.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuoyuan Hsu, Jacklyn Chang
  • Patent number: 10482962
    Abstract: A ternary content addressable memory (TCAM) device includes a memory cell. The memory cell includes a data storage circuit, a limiter circuit, and a discharge circuit. The data storage circuit includes a first resistor and a second resistor connected in series to divide a voltage corresponding to search data, and configured to store cell data. The limiter circuit is configured to receive the divided voltage through an input terminal and transmit an output voltage through an output terminal based on a level of the divided voltage. The discharge circuit discharges a matching line indicating whether the stored cell data matches with the search data, based on the output voltage of the limiter circuit.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 19, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Research & Business Foundation, Sungkyunkwan Univ.
    Inventors: Cheol Kim, Hyun-Suk Kang, Kee-Won Kwon, Rak-Joo Sung, Sung-Gi Ahn
  • Patent number: 10468371
    Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having comprising a hole and a conductive layer surrounding the hole, the conductive layer including a first connection point and a second connection point that are located so that a straight line between the first connection point and the second connection point crosses over the hole; an external terminal coupled to the first connection point of the conductive layer of the connection wiring; and an internal circuit coupled to the second connection point of the conductive layer of the connection wiring.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Ken Ota
  • Patent number: 10431283
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Patent number: 10388355
    Abstract: A memory cell within an integrated-circuit memory component receives a first control signal that transitions between supply voltage levels of a first voltage domain and a second control signal that transitions between supply voltage levels of a second voltage domain different from the first voltage domain. In response to the transitions of the first and second control signal, output-enable circuitry within the memory cell transitions an output-enable signal between one of the supply voltage levels of the first voltage domain and one of the supply voltage levels of the second voltage domain to enable output signal generation on an output signal line coupled to the memory cell.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 20, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt
  • Patent number: 10361093
    Abstract: A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Eduard A. Cartier, Chandrasekharan Kothandaraman
  • Patent number: 10354705
    Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a plurality of sense amplifier control circuits coupled to a plurality of corresponding sense amplifiers, wherein each sense amplifier control circuit of the plurality of sense amplifier control circuits provides one or more control signals to a corresponding sense amplifier of a plurality of sense amplifiers; and a driver that provides a selection signal to a plurality of word drivers responsive, at least in part, to a first control signal that is responsive to the one or more control signals from the plurality of sense amplifier control circuits.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Takeshi Ohgami
  • Patent number: 10318372
    Abstract: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Jae-Kwan Park
  • Patent number: 10319438
    Abstract: In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: June 11, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Emanuela Calvetti, Marcella Carissimi, Marco Pasotti
  • Patent number: 10311919
    Abstract: Apparatuses and methods for calibrating sense amplifiers in a semiconductor memory are disclosed. An example apparatus includes an amplifier circuit and a calibration circuit. The amplifier circuit is configured to be coupled to a supply voltage and a reference voltage, and when activated the amplifier circuit is configured to provide an output signal at an output that is complementary to an input signal provided to an input. When activated by a calibration signal, the calibration circuit is configured to provide a calibration voltage to the output of the amplifier circuit, wherein the calibration voltage is an equilibration voltage between the supply voltage and the reference voltage provided to the amplifier circuit.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 4, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Stefan Frederik Schippers
  • Patent number: 10297303
    Abstract: A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. The virtual ground circuitry is configured to provide a virtual ground at a first bias voltage potential to a conductive line operably coupled to a selected ferroelectric memory cell, and discharge the conductive line to the sense node responsive to the selected ferroelectric memory cell changing from a first polarization state to a second polarization state. A method includes applying a second bias voltage potential to another conductive line operably coupled to the selected ferroelectric memory cell, and comparing a sense node voltage potential to a reference voltage potential. Electrical systems and computing devices include virtual ground sensing circuits.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Giulio Giuseppe Marotta, Marco Domenico Tiburzi
  • Patent number: 10224086
    Abstract: A memory device includes at least one reference cell and multiple memory cells. A method of operating the memory device may include detecting a temperature of the memory device and controlling a level of a first read signal applied to the at least one reference cell in accordance with a result of the detecting of the temperature. The method may also include comparing a first sensing value sensed by applying the first read signal to the at least one reference cell with a second sensing value sensed by applying a second read signal to a selected memory cell among the multiple memory cells.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Shik Kim, Suk-Soo Pyo, Gwan-Hyeob Koh
  • Patent number: 10211064
    Abstract: A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Eduard A. Cartier, Chandrasekharan Kothandaraman
  • Patent number: 10153007
    Abstract: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Harish N. Venkata, John F. Schreck, Mansour Fardad
  • Patent number: 10109362
    Abstract: A semiconductor device includes a fuse array section suitable for performing program and read operations; a control signal generation section suitable for generating a precharge control signal and a word line control signal; a bit line control section suitable for controlling a precharge operation of a bit line in response to the precharge control signal and a source signal; and a word line control section suitable for controlling activation of a program word line and a read word line for performing the program and read operations in response to the word line control signal, wherein the control signal generation section controls the word line control signal to be activated after a predetermined time from the activation of the precharge control signal.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: October 23, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jeong-Tae Hwang
  • Patent number: 10102913
    Abstract: A controlling method of a semiconductor device provided with a memory array including a plurality of complementary cells, each cell including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, the controlling method comprising: performing a prewrite procedure that writes ‘0’ or ‘1’ to both of the first memory element and the second memory element.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: October 16, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masamichi Fujito, Hiroshi Yoshida, Takanori Takahashi, Yasuhiko Taito
  • Patent number: 10095617
    Abstract: A memory device includes an input/output interface configured to receive and output signals. The input/output interface is configured to receive a memory address to be accessed and data sequence information within a clock cycle or at a rising or falling edge of a clock cycle. The data sequence information specifies an input or output data sequence.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: October 9, 2018
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuen-Long Chang, Su-Chuch Lo, Chao Hsin Lin, Ken-Hui Chen
  • Patent number: 10032415
    Abstract: The present invention provides a pixel circuit and a driving method thereof and a display device. The pixel circuit comprises a driving transistor, a storage capacitor, an organic light emitting device, a reset unit, a data writing unit and a voltage output unit. The reset unit is connected to a reset control signal line, an initialization signal line, the data writing unit, two ends of the storage capacitor, the voltage output unit, and a first electrode and a control electrode of the driving transistor. The control electrode of the driving transistor is connected to the second end of the storage capacitor, the first electrode thereof is connected to the voltage output unit, the second electrode thereof is connected to the organic light emitting device. The data writing unit is connected to a gate line, a data line and the first end of the storage capacitor.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: July 24, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zhanjie Ma
  • Patent number: 10013197
    Abstract: The present disclosure includes apparatuses and methods related to a shift skip. An example apparatus comprises a plurality of sensing circuitries, comprising respective sense amplifiers and respective compute components. A controller is configured to, responsive to a mask data unit associated with a first sensing circuitry having a particular value, cause a data value to be shifted from a second sensing circuitry to a third sensing circuitry without shifting the data value to the first sensing circuitry, wherein the first sensing circuitry is physically located between the second sensing circuitry and the third sensing circuitry.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Gary L. Howe, Harish N. Venkata
  • Patent number: 10008273
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: June 26, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Biswajit Ray, Gerrit Jan Hemink, Mohan Dunga, Bijesh Rajamohanan, Changyuan Chen
  • Patent number: 9838014
    Abstract: A data transmission circuit may include a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal, and a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 5, 2017
    Assignee: SK hynix Inc.
    Inventor: Sang Jin Byeon
  • Patent number: 9825042
    Abstract: In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m_1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 9799408
    Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: October 24, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Stephen Keith Heinrich-Barna, Raviprakash Suryanarayana Rao
  • Patent number: 9721742
    Abstract: A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 1, 2017
    Assignee: Active-Semi, Inc.
    Inventors: John H. Carpenter, Jr., Brett E. Smith, Hiroshi Watanabe
  • Patent number: 9679614
    Abstract: Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: June 13, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Yoshinori Matsui
  • Patent number: 9679927
    Abstract: A liquid crystal display includes a first pixel and a second pixel that extend in a data line direction. The first and second pixels are connected to a same data line, and the first pixel is closer to a data driver than the second pixel. A channel width of a thin film transistor of the first pixel is less than a channel width of a thin film transistor of the second pixel.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 13, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Se Hyoung Cho, Il Gon Kim, Sung Hwan Kim, Mee Hye Jung
  • Patent number: 9654086
    Abstract: Disclosed is an op-amp circuit with current-controlled hysteresis that is insensitive to PVT variations. In the circuit, a digital output signal is output from an output buffer based on the output voltage at an output node of an op-amp. A current source is connected to the input side of the op-amp or one of multiple current sources is selectively connected to the input side and enabled when the digital output signal has a high value to provide falling edge hysteresis. Alternatively, a current source is connected to the reference side of the op-amp or one of multiple current sources is selectively connected to the reference side and enabled when the digital output signal is low to provide rising edge hysteresis. Alternatively, current sources are connected to both the input and reference sides and selectively controlled to provide either falling or rising edge hysteresis.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: May 16, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John A. Fifield, Eric D. Hunt-Schroeder
  • Patent number: 9620197
    Abstract: A circuit for driving a sense amplifier of a semiconductor memory device is provided. The circuit includes a first driving circuit configured to supply a current from a power node to a first driving node of the sense amplifier based on a first driving control signal, a source control circuit configured to generate a control signal based on a second driving control signal and a voltage of the drain node, and a second driving circuit configured to draw current from a second driving node of the sense amplifier to a ground node based on the control signal.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: April 11, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-seok Park, Soo-bong Chang
  • Patent number: 9620214
    Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: April 11, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
  • Patent number: 9595345
    Abstract: Techniques are provided for efficiently performing programming operations in a memory device. In particular, power consumption is reduced in sensing circuitry by avoiding pre-charging of bit lines for certain memory cells at certain times during a programming operation. One approach uses knowledge of the different phases of a programming operation to reduce the number of unnecessary bit line pre-charges. For example, during the lower program loop numbers of a programming operation, bit line pre-charging may occur for lower data states but not for higher data states. Similarly, during the higher program loop numbers, bit line pre-charging may occur for higher data states but not for lower data states. In another approach, which may or may not incorporate knowledge of the different phases of a programming operation, the setting of the bit line pre-charge can be updated at least once after it is initially set in the verify portion.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: March 14, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Man L Mui, Yee Lih Koh, Yenlung Li, Cynthia Hsu
  • Patent number: 9559105
    Abstract: A signal processing circuit includes a memory and a control portion configured to control the memory. The control portion includes a volatile memory circuit including data latch terminals, a first non-volatile memory circuit electrically connected to one of the data latch terminals, a second non-volatile memory circuit electrically connected to the other of the data latch terminals, and a precharge circuit having a function of supplying a potential that is a half of a high power supply potential to the one and the other of the data latch terminals. Each of the first non-volatile memory circuit and the second non-volatile memory circuit includes a transistor having a channel formation region including an oxide semiconductor and a capacitor connected to a node that is brought into a floating state by turning off the transistor.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: January 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro Ohmaru, Hidetomo Kobayashi
  • Patent number: 9530475
    Abstract: Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: December 27, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 9485467
    Abstract: The time in the host device and the time in the client device are synchronized. The host device and the client device download content data from a content distribution server using progressive downloading. The host device controls playback processes in the host device and the client device so as to be synchronized, in accordance with a download status in the host device and the client device.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: November 1, 2016
    Assignees: Sony Corporation, Sony Interactive Entertainment Inc.
    Inventors: Hisayuki Kunigita, Seung-Hyun Lee, Taek-Joo Lee, Ju-Yeong Ji
  • Patent number: 9413351
    Abstract: An integrated circuit device comprises at least one power gating arrangement, including at least one gated power domain, and at least one power gating component operably coupled between at least one node of the at least one gated power domain and at least a first power supply node. The at least one power gating component is arranged to selectively couple the at least one node of the at least one gated power domain to the at least first power supply node.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: August 9, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sergey Sofer, Valery Neiman, Michael Priel
  • Patent number: 9384816
    Abstract: In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m_1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: July 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 9355707
    Abstract: A semiconductor device that includes: a detection circuit suitable for detecting a gapless pattern section of a detection target signal; and an internal circuit suitable for performing a normal operation during a normal section and additionally performing the normal operation during a compensating section corresponding to the gapless pattern section in response to a detection result signal outputted from the detection circuit.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: May 31, 2016
    Assignee: SK Hynix Inc.
    Inventor: Ho-Don Jung
  • Patent number: 9330731
    Abstract: A circuit comprises a first transistor and a second transistor in a strap cell region between a first memory array and a second memory array of a memory device. The first transistor includes a first node connected to a first data line, and a second node connected to a second data line. The first node and the second node of the first transistor are complementary to each other in voltage level. Further, the second transistor includes a first node connected to the second data line, and a second node connected to the first data line. The first node and the second node of the second transistor are complementary to each other in voltage level.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: May 3, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hua-Hsin Yu, Hsiu Fen Peng, Hau-Tai Shieh
  • Patent number: 9324395
    Abstract: A data sensing circuit of a semiconductor apparatus includes a sensing unit configured to drive a pair of output lines based on a voltage level difference between a pair of input/output lines in response to a pair of enable signals, a timing control unit configured to perform an equalizing operation between the pair of output lines while the pair of enable signals are in a deactivated state in response to a control signal, and to interrupt the equalizing operation between the pair of output lines when a predetermined period of time has passed following the activation of the pair of enable signals, and a control signal generation unit configured to generate the control signal in response to the enable signal.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: April 26, 2016
    Assignee: SK hynix Inc.
    Inventor: One Gyun Na
  • Patent number: 9312018
    Abstract: The present disclosure relates to sensing with boost. An apparatus includes boost logic. Boost logic includes a boost source and a plurality of boost interfaces coupled to the boost source. The boost source is configured to provide a boost clamp voltage to each of the plurality of boost interfaces. Each of the plurality of boost interfaces includes a respective buffer configured to buffer the boost source from a respective load. Each boost interface is configured to provide a boost voltage to the respective load. The boost voltage configured to increase a sense window. The boost voltage related to the boost clamp voltage.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: April 12, 2016
    Assignee: Intel Corporation
    Inventor: Shigekazu Yamada
  • Patent number: 9281023
    Abstract: Disclosed are single-ended sensing circuits. Each of the sensing circuits comprises at least a sense amplifier connected to a sense node, an isolation field effect transistor (FET) connected in series between the sense node and a signal line node, and a pre-charged device connected to the sense node. In order to achieve a relatively fast pre-charge of both the sense and signal line nodes and to also achieve a relatively fast and accurate sense of the sense node, the single-ended circuits further incorporate a variable reference voltage generator connected to the gate of the isolation FET for selectively applying different reference voltages to the gate during pre-charging and sensing operations, respectively, and/or a second pre-charge device connected to the signal line node for facilitating pre-charging of that signal line node.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: March 8, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Travis R. Hebig