Differential Sensing Patents (Class 365/207)
  • Patent number: 12260921
    Abstract: Systems and methods are provided for sensing a data state of a memory cell. In an example implementation, systems and methods disclosed herein perform a method that includes connecting a first sensing node and a second sensing node to a bitline of a sensing amplifier to simultaneously discharge first and second capacitors connected to the first and second sensing nodes, respectively, through the memory cell. After a first sensing period, the second sensing node is disconnected from the bitline, which includes a first voltage level based on discharging the second capacitor. After a second sensing period, the first sensing node is disconnected from the bitline, which includes a second voltage level based on discharging the first capacitor. First and second sensing results are latched based on the first and second voltage levels, respectively, and a data state of the memory cell is based on the first and second voltage levels.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: March 25, 2025
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Hiroki Yabe
  • Patent number: 12261520
    Abstract: A switch-mode power supply and a zero current detector for use therein. A zero current detector includes an input stage and an output stage. The output stage is coupled to the input stage. The output stage includes a detector output terminal, a first transistor, and a second transistor. The first transistor includes an input terminal and a control terminal. The input terminal is coupled to the detector output terminal. The control terminal is coupled to the input stage. The second transistor includes an input terminal, a control terminal, and an output terminal. The input terminal is coupled to the control terminal of the first transistor. The control terminal is coupled to the input terminal of the second transistor. The output terminal is coupled to ground.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: March 25, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Venkata Veeramreddi, Subhash Sahni
  • Patent number: 12254939
    Abstract: A memory structure of an integrated circuit includes a plurality of memory arrays arranged in parallel along the first direction and extending along the second direction, a sensitivity amplifier array extending along the second direction is arranged between every two memory arrays, and the sensitivity amplifier array includes an odd-numbered sensitivity amplifier array and an even-numbered sensitivity amplifier array, the odd-numbered sensitivity amplifier array is connected to an odd-numbered global signal line, and the even-numbered sensitivity amplifier array is connected to the even-numbered global signal line; a first sensitivity amplifier array is arranged between the memory arrays at the edge, and the first sensitivity amplifier array is connected to both the odd-numbered global signal line and the even-numbered global signal line. The present disclosure can improve reliability, yield and test success rate of the memory products.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: March 18, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Weibing Shang, Hongwen Li
  • Patent number: 12243614
    Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: March 4, 2025
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Siva Kumar Chinthu, Suresh Pasupula, Devesh Dwivedi, Chunsung Chiang
  • Patent number: 12243599
    Abstract: In some aspects of the present disclosure, a memory array includes: a plurality of memory cells; and a plurality of logic gates, each of the plurality of logic gates having a first input, a second input, and an output gating a corresponding one of the plurality of memory cells, wherein the first input of each of the plurality of logic gates of a first subset is coupled to a first bit select line.
    Type: Grant
    Filed: April 4, 2024
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Perng-Fei Yuh
  • Patent number: 12237007
    Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: February 25, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Kedar Janardan Dhori, Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj Ayodhyawasi
  • Patent number: 12232311
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: February 18, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy
  • Patent number: 12230681
    Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Chun Chung Su, Wen-Hsing Hsieh
  • Patent number: 12230351
    Abstract: A circuitry (30) for on-chip power regulation is provided. The circuitry (30) comprises a memory array (31) comprising a plurality of memory cell blocks (32) arranged in rows and columns, where the memory cell blocks are clustered into a defined number of memory cell blocks (33) along the row, each cluster (33) is connected to a respective local reference line (34). In addition, the circuitry (30) comprises a plurality of sense amplifiers (40) connected to the respective memory cell blocks (32). The circuitry (30) further comprises at least one dummy memory cell block (35) additionally arranged to each cluster of memory cell blocks (33), where the dummy memory cell block (35) is connected to a main reference line (36). Moreover, the circuitry (30) comprises at least one transistor (37) arranged in between the local reference line (34) of each cluster of memory cell blocks (33) and the main reference line (36).
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: February 18, 2025
    Assignee: MICLEDI MICRODISPLAYS BV
    Inventors: Soeren Steudel, Sean Lord
  • Patent number: 12224006
    Abstract: A high-speed and large-current adjustable pulse circuit, an operating circuit and an operating method of a phase-change memory are provided. The high-speed and large-current adjustable pulse circuit is provided with a clamping structure, a current mirror structure and a leakage current shutdown structure. The clamping structure including a clamping operational amplifier and a first MOS transistor is configured to generate a reference current. The current mirror structure is configured to generate an output current proportional to the reference current. The leakage current shutdown structure is configured to turn off the current mirror structure and reduce leakage current when pulse disappear. In this way, a device with an adjustable current and a reduced leakage current is realized.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: February 11, 2025
    Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Xingsheng Wang, Yinghao Ma, Fan Yang, Chengxu Wang, Menghua Huang, Xiangshui Miao
  • Patent number: 12217805
    Abstract: A reference voltage generating circuit according to an embodiment includes: an original reference voltage generating unit that generates an original reference voltage; and a reference voltage correcting unit that decreases the original reference voltage as the temperature rises and outputs the original reference voltage as a reference voltage to a sense amplifier, and thus it is possible to perform highly reliable operation while the influence of the temperature is reduced.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: February 4, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Osamu Hirabayashi
  • Patent number: 12205641
    Abstract: Systems, methods, and apparatus related to dynamically determining read voltages used in memory devices. In one approach, a memory device has a memory array including memory cells. One or more resistors are formed as part of the memory array. A memory controller increments a counter as write operations are performed on the memory cells. When the counter reaches a limit, a write operation is performed on the resistors. The write operation applies voltages to the resistors similarly as applied to the memory cells over time during normal operation. When performing a read operation, a current is applied to one or more of the resistors to determine a boost voltage. When reading the memory cells, a read voltage is adjusted based on the boost voltage. The memory cells are read using the adjusted read voltage.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: January 21, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Nicola Ciocchini, Andrea Gotti
  • Patent number: 12205634
    Abstract: The present disclosure provides an electronic circuit, a memory device, and a method for operating an electronic circuit. An electronic circuit comprises a driver circuit configured to provide a drive voltage to a word line of the electronic circuit, a suppression circuit electrically connected to the driver circuit and the word line, and a control circuit electrically connected to the suppression circuit. The suppression circuit is configured to generate a voltage drop in the drive voltage. The control circuit controls the suppression circuit.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Cheng Wu, Pei-Yuan Li, Kao-Cheng Lin, Chien Hui Huang, Yung-Ning Tu
  • Patent number: 12205635
    Abstract: A memory module with improved timing adaptivity of sensing amplification, comprises at least one sensing amplifier, a tracking word line, a tracking bit line and a pulse-width controller. The tracking word line comprises a front node and an end node. Each said sensing amplifier is enabled/disabled when an enabling signal is activated/deactivated. The pulse-width controller is coupled to the tracking bit line, the front node and the end node. When a voltage of the tracking bit line changes to a predetermined voltage, the pulse-width controller activates the enabling signal, and causes a voltage of the front node to change. When the voltage of the front node changes, the tracking word line causes a voltage of the end node to change after a first delay time. When the voltage of the end node changes, the pulse-width controller deactivates the enabling signal after a second delay time.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: January 21, 2025
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventors: Po-Yu Wu, Hao-I Yang, Nan-Chun Lien
  • Patent number: 12205633
    Abstract: Structures herein include an array of non-volatile memory cells. The non-volatile memory cells include memory bit cells and at least one reference bit cell that is adjacent the memory bit cells. These structures also include at least one reference voltage regulator connected to the reference bit cell, and at least one sense amplifier connected to the memory bit cells and the reference voltage regulator.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: January 21, 2025
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Venkatesh P. Gopinath, Xiaoli Hu, Thomas Melde, Nicki N. Mika
  • Patent number: 12205651
    Abstract: A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: January 21, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gianbattista Lo Giudice, Antonino Conte
  • Patent number: 12205014
    Abstract: A neural network unit is disclosed.
    Type: Grant
    Filed: January 31, 2021
    Date of Patent: January 21, 2025
    Assignee: Anaflash Inc.
    Inventor: Seung-Hwan Song
  • Patent number: 12205628
    Abstract: A sense amplifier includes an amplifying circuit and a voltage equalizing circuit. The amplifying circuit includes: a first P-type transistor, having a first terminal connected to a third node, a second terminal connected to a first node, and a gate connected to a first bit line; a second P-type transistor, having a first terminal connected to the third node, a second terminal connected to a second node, and a gate connected to a second bit line; a first N-type transistor, having a first terminal connected to the first node, a second terminal connected to a fourth node, and a gate connected to the first bit line; a second N-type transistor, having a first terminal connected to the second node, a second terminal connected to the fourth node, a gate connected to the second bit line. The voltage equalizing circuit is connected between the first node and the second node.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: January 21, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Sungsoo Chi
  • Patent number: 12190994
    Abstract: An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: January 7, 2025
    Assignee: XILINX, INC.
    Inventors: Kumar Rahul, Santosh Yachareni, Mahendrakumar Gunasekaran, Mohammad Anees
  • Patent number: 12189954
    Abstract: A computer system based on wafer-on-wafer architecture is provided, comprising a memory device and a logic circuit layer stacked in a wafer on wafer structural configuration. The memory device comprises a memory array and a circuit driver. The memory array comprises a shared circuit path and a plurality of memory cells, wherein the shared circuit path is connected to the memory cells. The circuit driver is connected to the shared circuit path, driving the memory cells. The logic circuit layer comprises a plurality of bonding pads for signal transmission, and a latency controller, connected to the memory array through the bonding pads, adjusting the number of memory cells connecting the shared circuit path, thereby dynamically adjusting the latency characteristics of the memory array. Embodiments of the memory device and the memory control method are also provided.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: January 7, 2025
    Assignee: WHALECHIP CO., LTD.
    Inventors: Kun-Hua Tsai, Yi-Wei Yan
  • Patent number: 12183416
    Abstract: Systems, methods, and apparatuses for temperature-compensated operation of electronic devices are described. For example, an apparatus for performing voltage compensation on a sense amplifier based on temperature may include a sense amplifier control circuit coupled to the sense amplifier to provide a compensation pulse to the sense amplifier, wherein the sense amplifier operates in a voltage compensation phase during the compensation pulse. The apparatus may determine the compensation pulse responsive to a voltage compensation duration signal that is based on the operating temperature of the apparatus. The voltage compensation occurs when there is no activate command immediately before or immediately after so that compensation duration change do not happen during an activate command from the command decoder.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: December 31, 2024
    Inventors: Boon Hor Lam, Karl L. Major, Jonathan Hawkins, Galaly Ahmad
  • Patent number: 12183408
    Abstract: Operating a memory unit using a low-power DC source. The low-power DC source provides lesser power than that required to operate the memory unit. In an embodiment, charge from the low-power source is stored on a charge storage device in a first time interval. The memory unit is operated using the charge storage device as a second power source in a second time interval. A portion of one of the first time interval and the second time interval does not overlap with the other one of the first time interval and the second time interval.
    Type: Grant
    Filed: December 11, 2021
    Date of Patent: December 31, 2024
    Assignee: Ningbo Aura Semiconductor Co., Ltd.
    Inventors: Arnold J D'Souza, Shyam Somayajula
  • Patent number: 12183415
    Abstract: A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: December 31, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Shuhei Nagatsuka
  • Patent number: 12165732
    Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
  • Patent number: 12148467
    Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memory array. The first vertical n-type transistor may be configured to selectively couple an access line with a source node and the second n-type transistor may be configured to selectively couple the access line with a ground node. To activate the access line coupled with the first and second vertical n-type transistors, the first vertical n-type transistor may be activated, the second vertical n-type transistor may be deactivated, and the source node coupled with the first vertical n-type transistor may have a voltage applied that differs from a ground voltage.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: November 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Lorenzo Fratin, Fabio Pellizzer
  • Patent number: 12125533
    Abstract: In an embodiment a non-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processing device configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: October 22, 2024
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics International N. V.
    Inventors: Francesco La Rosa, Marco Bildgen
  • Patent number: 12119047
    Abstract: A readout circuit structure is provided, which includes: a first sense amplification circuit and a second sense amplification circuit, disposed adjacent to each other along an extension direction of a bit line, here the first sense amplification circuit is coupled to one memory array in the adjacent memory arrays by a first bit line, and is coupled to the other memory array by a first complementary bit line, and the second sense amplification circuit is coupled to one memory array in the adjacent memory arrays by a second bit line, and is coupled to the other memory array by a second complementary bit line; a first equalization pipe, connected to the first bit line; a second equalization pipe, connected to the first complementary bit line; a third equalization pipe, connected to the second bit line; and a fourth equalization pipe, connected to the second complementary bit line.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: October 15, 2024
    Assignee: CHANXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Sungsoo Chi, Shuyan Jin, Fengqin Zhang
  • Patent number: 12112830
    Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: October 8, 2024
    Inventors: Eric J. Stave, George E. Pax, Yogesh Sharma, Gregory A. King, Chan H. Yoo, Randon K. Richards, Timothy M. Hollis
  • Patent number: 12100439
    Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can include an array of memory cells; and a controller coupled to the array configured to sense a first memory cell based upon a first input associated with the memory cell and a second input and a third input associated with a second memory cell.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: September 24, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Takamasa Suzuki
  • Patent number: 12094516
    Abstract: A method and apparatus for intensifying current leakage between adjacent memory cells includes that: a write operation is performed on a memory array, to form a column strip test pattern, the column strip test pattern being formed by arranging low-level memory cells and high-level memory cells in columns, and N columns of high-level memory cells being present between two adjacent columns of low-level memory cells, N?2; and voltage adjustment is performed on the low-level memory cells and the high-level memory cells, to increase potential differences between the low-level memory cells and the high-level memory cells.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: September 17, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Huanhuan Liu, Wei-Chou Wang
  • Patent number: 12094563
    Abstract: The present disclosure provides a signal line structure, a signal line driving method, and a signal line circuit. The signal line structure includes a plurality of parallel signal lines, where each of the signal lines is maintained in a drive state at any time.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: September 17, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kangling Ji
  • Patent number: 12095751
    Abstract: Low power devices are able to utilize encryption in communication. Low power devices typically cannot send/receive large amounts of data since sending/receiving more data uses more power. Implementing a key exchange with a small encrypted payload enables secure communication between the devices. A one-way data stream is implemented. The one-way data stream is able to be encrypted.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: September 17, 2024
    Assignee: Winkk, Inc.
    Inventor: Robert O. Keith, Jr.
  • Patent number: 12087368
    Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: September 10, 2024
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Arpit Vijayvergia, Vikas Rana
  • Patent number: 12087387
    Abstract: A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: September 10, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Lava Kumar Pulluru, Poornima Venkatasubramanian, Manish Chandra Joshi, Ved Prakash, Pushp Khatter
  • Patent number: 12080344
    Abstract: A multi-bit, asynchronous e-fuse macro, the macro comprising: the following inputs: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock; a plurality of e-fuse bits; a supply voltage configured to allow programming at least one of the e-fuse bits; at least one fuse output; and self-timing and control circuitry configured to perform signaling, wherein each of the inputs is in electrical communication with said e-fuse macro.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: September 3, 2024
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Jason F. Ross
  • Patent number: 12073874
    Abstract: A memory read-write circuit includes a sense amplifier and a control signal generation module. A power voltage of the sense amplifier is controlled and supplied by a first control signal or a second control signal, and a first power voltage controlled and supplied by the first control signal is greater than a second power voltage controlled and supplied by the second control signal. A control signal generation module is configured to control, in a normal read-write mode, a pulse duration for generating the first control signal to be a first duration, and control, in a refresh mode, the pulse duration for generating the first control signal to be a second duration, the second duration being less than the first duration.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: August 27, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yinchuan Gu
  • Patent number: 12073869
    Abstract: A computing device in some examples includes an array of memory cells, such as 8-transisor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Mahmut Sinangil
  • Patent number: 12073876
    Abstract: A level shifter circuit includes a level shifter configured to receive a first clock signal associated with a first power level and generate a second clock signal associated with a second power level, wherein the second power level is greater than the first power level. The level shifter circuit further includes an input clock buffer having a first input, wherein the first input comprises the second clock signal from the level shifter, and a second input coupled in parallel to the first input, wherein the second input includes the first clock signal.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: August 27, 2024
    Assignee: Synopsys, Inc.
    Inventor: Harold Pilo
  • Patent number: 12068691
    Abstract: In an embodiment, an apparatus is disclosed that comprises a voltage regulator and a regulator booster. The voltage regulator is supplied by an input and is configured to generate a regulated output. The regulated output has a voltage corresponding to an operating point of the voltage regulator. The regulator booster is connected to the voltage regulator and, when activated, is configured to boost the voltage of the regulated output by a target amount. The target amount is at least a portion of a magnitude of a voltage droop relative to the operating point that is caused by a change in a current load on the regulated output.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: August 20, 2024
    Assignee: Renesas Electronics America Inc.
    Inventors: Steven Ernest Finn, Ajinkya Manohar Munge
  • Patent number: 12057155
    Abstract: An electronic system includes a controller configured to detect a bank in a standby state for a write operation between a first bank and a second bank during a refresh operation period and output data for performing a post-write operation to the bank in the standby state for the write operation. The electronic system also includes an electronic device including the first and second banks. The electronic device is configured to latch the data in an input/output control circuit connected to the bank in the standby state for the write operation.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: August 6, 2024
    Assignee: SK hynix inc.
    Inventor: Choung Ki Song
  • Patent number: 12057186
    Abstract: A semiconductor integrated circuit has a plurality of memory cells arranged in a first direction and each storing first data, a plurality of first wirings provided to correspond to the plurality of memory cells arranged in the first direction and supplying second data to be multiplied by the first data, and a second wiring pair provided to correspond to the plurality of memory cells arranged in the first direction and that includes one second wiring which is discharged when multiplication data of the first data, stored in each of the plurality of memory cells, and the second data, supplied by the first wiring corresponding to the memory cell, is a first logic; and another second wiring which is discharged when the multiplication data is a second logic.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: August 6, 2024
    Assignee: Kioxia Corporation
    Inventor: Atsushi Kawasumi
  • Patent number: 12051460
    Abstract: Apparatuses, systems, and methods for single-ended sense amplifiers. A memory device may include a number of sense amplifiers used to read the voltage of memory cells along digit lines. Double-ended sense amplifiers are coupled to two digit lines. Single-ended sense amplifiers are coupled to a single digit line. The memory cells of an edge word line of a memory array may alternately be coupled to a single-ended sense amplifier or a double-ended sense amplifier. The use of single-ended sense amplifiers may reduce a footprint for a given number of memory cells in the array.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: July 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Tae H. Kim, Christopher J. Kawamura, Jiyun Li
  • Patent number: 12046553
    Abstract: An Integrated Circuit (IC) includes electronic circuitry, an electronic fuse (eFuse) and a protection circuit. The eFuse is configured to be selectably programmed to a logical state. The electronic circuitry is configured to read the eFuse and to operate in accordance with the logical state read from the eFuse. The eFuse has a first range of operational voltages, and the electronic circuitry has a second range of operational voltages that is broader than the first range of operational voltages. The protection circuit is configured to prevent the electronic circuitry from misreading the logical state of the eFuse due to a voltage supply to the IC falling within the second operational voltage range but outside the first operational voltage range.
    Type: Grant
    Filed: October 23, 2022
    Date of Patent: July 23, 2024
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Runzi Chang, Chon In Kou, Minda Zhang
  • Patent number: 12045674
    Abstract: A neural processing device is provided, which includes a first block that operates at a first operating frequency and at a second operating frequency different from the first operating frequency, a second block operates at the first operating frequency, and a data communication mode determiner that controls data communication between the first block and the second block, and determines a first data communication mode for a first interface between the first block and the second block.
    Type: Grant
    Filed: December 19, 2023
    Date of Patent: July 23, 2024
    Assignee: REBELLIONS INC.
    Inventors: Wongyu Shin, Juyeong Yoon, Sangeun Je
  • Patent number: 12038862
    Abstract: Apparatuses and methods for selective communication through a memory connector via switching circuitry. An apparatus includes a memory connector, a memory bus corresponding to a memory protocol, one or more communication buses corresponding to one or more communication protocols, and switching circuitry operably coupled between the memory connector and the memory bus and the one or more communication buses. The one or more communication protocols are different from the memory protocol. The switching circuitry is configured to selectively operably couple any one of the memory bus and the one or more communication buses to the memory connector to enable communication through the memory connector using any one of the memory protocol or the one or more communication protocols.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: July 16, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 12027220
    Abstract: Various one-time-programmable (OTP) memory cells are disclosed. An OTP memory cell includes an additional dopant region that extends at least partially under the gate of a transistor, such as an anti-fuse transistor. The additional dopant region provides an additional current path for a read current. Alternatively, an OTP memory cell includes three transistors; an anti-fuse transistor and two select transistors. The two select transistors can be configured as a cascaded select transistor or as two separate select transistors.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yih Wang, Hiroki Noguchi
  • Patent number: 12009025
    Abstract: A method for accessing a memory cell includes enabling precharging of a bit line of the memory cell before a next access of the memory cell. The method includes disabling the precharging after a first interval if the next access is a write. The method includes disabling the precharging after a second interval if the next access is a read. The first interval is shorter than the second interval.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: June 11, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tawfik Ahmed, Andrew J. Robison, Russell J. Schreiber
  • Patent number: 12002504
    Abstract: Components of sense amplifiers may share contacts that couple the components to a global line via a local line. In some examples, the components may be pull-down circuits of a same sense amplifier or pull-down circuits of adjacent sense amplifiers. The shared contact may include a transistor or a resistance between the local line and the global line. In some examples, the global line may be an RNL line. The transistor or resistance may reduce the impact of voltage across the components from affecting the global line and/or reduce the impact of voltage changes on the global line on the individual components.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: June 4, 2024
    Assignee: Micron Technology, Inc.
    Inventor: John Schreck
  • Patent number: 12002509
    Abstract: A data readout circuit of a RRAM includes: an adaptive current sense amplifier (CSA) and a reference current generator, the adaptive CSA is configured to electrically connect to the RRAM, and the adaptive CSA is electrically connected to the reference current generator; the reference current generator is configured to generate a basic reference current; the adaptive CSA is configured to obtain a reference current according to the basic reference current and a bit-line current of the RRAM; and the adaptive CSA is configured to compare the size of the reference current and that of the bit-line current so as to read out stored data. The present disclosure can improve the problem of data readout error due to the degradation of high resistance state of the RRAM.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: June 4, 2024
    Assignee: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES
    Inventors: Feng Zhang, Qirui Ren
  • Patent number: 11996137
    Abstract: A memory device for CIM has a memory array including a plurality of memory cells arranged in an array of rows and columns. The memory cells have a first group of memory cells and a second group of memory cells. Each row of the array has a corresponding word line, with each memory cell of a row of the array coupled to the corresponding word line. Each column of the array has a corresponding bit line, with each memory cell of a column of the array coupled to the corresponding bit line. A control circuit is configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-An Chang, Yu-Lin Chen, Chia-Fu Lee