Differential Sensing Patents (Class 365/207)
  • Patent number: 11087819
    Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, Dean D. Gans, Jiyun Li, Nathaniel J. Meier, Randall J. Rooney
  • Patent number: 11068639
    Abstract: Various implementations described herein refer to a method. The method may include providing a metal layout for an integrated circuit, wherein the metal layout includes multiple lines associated with bitlines. The method may include inserting at least one additional line between the multiple lines and the bitlines. The method may include arranging the at least one additional line with respect to the multiple lines and the bitlines so as to reduce capacitance associated with the bitlines.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: July 20, 2021
    Assignee: Arm Limited
    Inventors: Marlin Wayne Frederick, Jr., Ettore Amirante, Ronald Paxton Preston, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong
  • Patent number: 11069411
    Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: July 20, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Patent number: 11017843
    Abstract: In memory devices where a memory cell includes a thin film cell select transistor, selection between layers of such memory cells may further comprise another thin film select transistor. Bitline and wordline encoding suitable for a memory device having a single layer of memory cells may be scaled up to a 3D memory device having two or more memory cell layers. In a DRAM device one layer of (1TFT-1C) cells may include a 2D array of metal-insulator-metal capacitors over an array of TFTs. Additional layers of such 1TFT-1C cells may be stacked monolithically to form a 3D array. Memory cells in each layer may be accessed through a wordline and local bitline. A local bitline of one cell layer may be coupled to global bitline applicable to all cell layers through a layer-selected TFT according to a voltage applied to a layer-select gate voltage.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Sharma, Gilbert Dewey, Willy Rachmady, Van Le, Matthew Metz, Jack Kavalieros
  • Patent number: 11018687
    Abstract: A time-multiplexed group of MAC circuits for a machine learning application is provided in which at least one MAC circuit in the time-multiplexed group also functions as a capacitive-digital-to-analog converter (CDAC) within a successive approximation analog-to-digital converter (ADC). A comparator in the ADC is shared by the time-multiplexed group of MAC circuits.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: May 25, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Ankit Srivastava, Seyed Arash Mirhaj
  • Patent number: 10998031
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Patent number: 10990725
    Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Gabor Drasny, Gavin B. Meil
  • Patent number: 10984874
    Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
  • Patent number: 10969416
    Abstract: An integrated circuit including at least one circuit node, multiple duplicate circuit blocks integrated on the integrated circuit in close proximity with each other, each including at least one device that is susceptible to random telegraph noise (RTN), and a switch circuit that swaps electrical coupling of the duplicate circuit blocks, one at a time, to the at least one circuit node in sequential cycles of a clock signal. The duplicate circuit blocks may be large functional blocks, such as an oscillator or a comparator or the like, or limited to circuits including RTN susceptible devices, such as differential pairs or the like. Each duplicate circuit block may include any number of connections for coupling to corresponding circuit nodes. The swapping may further include chopping in which multiple inputs are swapped with each other while multiple outputs are swapped with each other in consecutive clock cycles.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 6, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: Vitor Pereira, Arup Mukherji
  • Patent number: 10965301
    Abstract: Included are a loop filter, a quantization circuit section, and a current steering digital-analog conversion section. The quantization circuit section converts a loop filter output into a digital value. The current steering digital-analog conversion section is provided in a feedback loop that feeds back the output of the quantization circuit section to the loop filter. Then, each of the analog-digital converters includes a first input signal current path, a second input signal current path, a first feedback current path, and a second feedback current path. The first input signal current path feeds a first input signal current to an input end of a first stage integrator of the loop filter. The second input signal current path feeds a second input signal current, a current opposite in sign to the first input signal current, to an input end of a second stage integrator of the loop filter.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: March 30, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takashi Moue, Takashi Matsumoto
  • Patent number: 10957382
    Abstract: Some embodiments include an integrated assembly having a base with sense-amplifier-circuitry. A first deck is over the base, and includes a first array of first memory cells. A second deck over the first deck, and includes a second array of second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 10937496
    Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chung H. Lam, Scott C. Lewis, Thomas M. Maffitt, Jack Morrish
  • Patent number: 10937655
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and peripheral circuits configured to sequentially program the pages. The memory device may include control logic configured to control the peripheral circuits such that a program voltage is applied to a word line coupled to a page selected from among the pages such that different pass voltages are applied to all or some word lines coupled to pages on which a program operation has been performed among unselected pages other than the selected page, and to word lines coupled to pages on which a program operation has not been performed among the unselected pages.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 10923194
    Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 16, 2021
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
  • Patent number: 10867652
    Abstract: In some embodiments, the present application provides a memory device. The memory device includes a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The MTJ memory cell includes an MTJ memory element and a first access transistor. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first current mirror transistor. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gaurav Gupta, Zhiqiang Wu
  • Patent number: 10868234
    Abstract: A storage device includes: a plurality of first magnetic tunnel junction (MTJ) cells disposed on a first portion of a substrate; and a plurality of second MTJ cells disposed on a second portion different from the first portion of the substrate; wherein each of the plurality of first MTJ cells has a first cross-sectional surface area viewing from a top of the substrate, each of the plurality of second MTJ cells has a second cross-sectional surface area viewing from the top of the substrate, and the second cross-sectional surface area is greater than the first cross-sectional surface area.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Chang-Hung Chen, Kuei-Hung Shen, Wen-Chun You, Tien-Wei Chiang
  • Patent number: 10847238
    Abstract: An analog content addressable memory cell includes a high side and a low side. The high side encodes a high bound on a range of values and includes a first voltage divider formed of a first programmable resistor and a first electronically controlled variable resistor. The low side encodes a low bound on the range of values and includes a second voltage divider formed of a second programmable resistor and a second electronically controlled variable resistor.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 24, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Patent number: 10754807
    Abstract: A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus that comply with a USB standard on in a first period and off in a second period, and a processing circuit that performs, in the second period, packet transfer processing on a transfer route that includes the first bus, the first and second physical layer circuits, the second bus. The bus switch circuit includes a first switch circuit, a second switch circuit, and a signal line connected between the first switch circuit and the second switch circuit.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 25, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Toshimichi Yamada
  • Patent number: 10726191
    Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes receiving layout data representing mask information for manufacturing a semiconductive substrate with a conductor over the semiconductive substrate. A first capacitor is formed between the conductor and the semiconductive substrate. The method further includes determining a capacitance difference between capacitances of the first capacitor and a neighboring capacitor. The method further includes forming a dummy capacitor to minimize the capacitance difference. A system for manufacturing a semiconductor device is also provided.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsuan-Ming Huang, An Shun Teng, Mingni Chang, Ming-Yih Wang, Yinlung Lu
  • Patent number: 10726901
    Abstract: A memory cell within an integrated-circuit memory component receives a first control signal that transitions between supply voltage levels of a first voltage domain and a second control signal that transitions between supply voltage levels of a second voltage domain different from the first voltage domain. In response to the transitions of the first and second control signal, output-enable circuitry within the memory cell transitions an output-enable signal between one of the supply voltage levels of the first voltage domain and one of the supply voltage levels of the second voltage domain to enable output signal generation on an output signal line coupled to the memory cell.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 28, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt
  • Patent number: 10726898
    Abstract: A sense amplifier circuit for sensing a data state of a data cell during a read cycle is described. The circuit includes a first stage with first circuitry to output a reference voltage and a data voltage relating to the data state of the data cell. The circuit further includes a second stage with circuitry to amplify a difference between the reference voltage and the data voltage. This circuitry includes a plurality of inverters and a plurality of capacitors. The read cycle includes a compensation phase. During the compensation phase the circuitry stores, at the capacitors, a voltage difference caused by a device mismatch of the inverters. After the compensation phase the circuitry amplifies the difference between the reference voltage and the data voltage, and compensates for the device mismatch using the stored voltage difference at the capacitors.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Thomas Martin Maffitt, John Kenneth Debrose
  • Patent number: 10643716
    Abstract: A nonvolatile memory device includes a plurality of memory cells coupled to a single bit line, wherein each of the plurality of memory cells is coupled to a different word line from a plurality of word lines. The nonvolatile memory device includes a decoder configured to sequentially apply a read voltage of a first level to target word lines among the word lines, based on a multi-read command. The nonvolatile memory device includes a read circuit configured to obtain first sensing values of target memory cells coupled to the target word lines, by sensing the bit line each time the read voltage of the first level is applied to each of the target word lines.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventor: Sok Kyu Lee
  • Patent number: 10622035
    Abstract: A sense amplifier includes a first sample and hold circuit, a second sample and hold circuit, a latch-type amplifier. The first sample and hold circuit is coupled to a bit line and configured to sample and hold memory cell data during a pre-charge phase of a sensing operation. The second sample and hold circuit is coupled to a reference bit line and configured to sample and hold data of a reference memory cell data during the pre-charge phase of the sensing operation. The latch-type amplifier, coupled to the first sample and hold circuit and the second sample and hold circuit, and configured to compare the memory cell data and the reference cell data during an evaluation phase of the sensing operation to output a sensing signal. The sense amplifier is isolated from the bit line and the reference bit line during the evaluation phase of the sensing operation. A sensing method adapted to a sense amplifier and a non-volatile memory include a sense amplifier are also introduced.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chang Yu, Ta-Ching Yeh
  • Patent number: 10622066
    Abstract: A resistive memory device according to an example embodiment of the inventive concepts includes: a cell array including a first section and a second section; a first column switch circuit connected to a memory cell and a reference cell of the first section through first bit lines; a second column switch circuit connected to a memory cell and a reference cell of the second section through second bit lines; and a column decoder configured to control the first and second column switch circuits such that one of the first bit lines connected to the memory cell and one of the second bit lines connected to the reference cell are selected according to a first column address, and one of the first bit lines connected to the reference cell and one of the second bit lines connected to the memory cell are selected according to a second column address.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Artur Antonyan
  • Patent number: 10545724
    Abstract: A controller for granting a user input device control of a controllable device including a receiver arranged for receiving a first sound signal recorded within a first time frame by a first sound sensor and receiving a second sound signal recorded within a second time frame by a second sound sensor located at the user input device. The controller further includes a processor arranged for determining a level of similarity between the first sound signal and the second sound signal. The processor is further arranged for granting the user input device control of the controllable device if a sufficient level of similarity has been determined. This enables the controller to determine if the user input device is in the same space as the first sound sensor, and it allows the creation of a control space of the controllable device based on the characteristics of the first sound sensor.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 28, 2020
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Adrianus Johannes Stephanus Maria De Vaan, Jan Van Wijgerden, Johan-Paul Marie Gerard Linnartz
  • Patent number: 10535379
    Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: January 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Darren L. Anand, John A. Fifield, Eric D. Hunt-Schroeder, Mark D. Jacunski
  • Patent number: 10523126
    Abstract: This present invention comprises the multiple power sections and a multi-input operational amplifier, wherein the pilot device places at the different location of the main power MOSFET form multiple individual power section, the multi-input operational amplifier drives a transistor to detect the overall current of each power section furthermore report the overall current to system.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 31, 2019
    Assignee: DONGGUAN CHANGGONG MICROELECTRONICS LTD
    Inventors: Xuening Li, Guanghua Ye
  • Patent number: 10490235
    Abstract: A read-only memory (ROM) device includes a memory cell that is electrically coupled to a bitline (BL) or to a BL which represents a complement of the BL. The ROM device precharges the BL and the BL to a first logical value. The ROM device activates the memory cell which discharges the BL when the memory cell is coupled to the BL or discharges the BL when the memory cell is coupled to the BL. The ROM device reads the first logical value as being stored within the memory cell when the BL is less than the BL. Otherwise, the ROM device reads the second logical value as being stored within the memory cell when the BL is greater than the BL.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuoyuan Hsu, Jacklyn Chang
  • Patent number: 10482962
    Abstract: A ternary content addressable memory (TCAM) device includes a memory cell. The memory cell includes a data storage circuit, a limiter circuit, and a discharge circuit. The data storage circuit includes a first resistor and a second resistor connected in series to divide a voltage corresponding to search data, and configured to store cell data. The limiter circuit is configured to receive the divided voltage through an input terminal and transmit an output voltage through an output terminal based on a level of the divided voltage. The discharge circuit discharges a matching line indicating whether the stored cell data matches with the search data, based on the output voltage of the limiter circuit.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 19, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Research & Business Foundation, Sungkyunkwan Univ.
    Inventors: Cheol Kim, Hyun-Suk Kang, Kee-Won Kwon, Rak-Joo Sung, Sung-Gi Ahn
  • Patent number: 10468371
    Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having comprising a hole and a conductive layer surrounding the hole, the conductive layer including a first connection point and a second connection point that are located so that a straight line between the first connection point and the second connection point crosses over the hole; an external terminal coupled to the first connection point of the conductive layer of the connection wiring; and an internal circuit coupled to the second connection point of the conductive layer of the connection wiring.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Ken Ota
  • Patent number: 10431283
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Patent number: 10388355
    Abstract: A memory cell within an integrated-circuit memory component receives a first control signal that transitions between supply voltage levels of a first voltage domain and a second control signal that transitions between supply voltage levels of a second voltage domain different from the first voltage domain. In response to the transitions of the first and second control signal, output-enable circuitry within the memory cell transitions an output-enable signal between one of the supply voltage levels of the first voltage domain and one of the supply voltage levels of the second voltage domain to enable output signal generation on an output signal line coupled to the memory cell.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 20, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt
  • Patent number: 10361093
    Abstract: A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Eduard A. Cartier, Chandrasekharan Kothandaraman
  • Patent number: 10354705
    Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a plurality of sense amplifier control circuits coupled to a plurality of corresponding sense amplifiers, wherein each sense amplifier control circuit of the plurality of sense amplifier control circuits provides one or more control signals to a corresponding sense amplifier of a plurality of sense amplifiers; and a driver that provides a selection signal to a plurality of word drivers responsive, at least in part, to a first control signal that is responsive to the one or more control signals from the plurality of sense amplifier control circuits.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Takeshi Ohgami
  • Patent number: 10319438
    Abstract: In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: June 11, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Emanuela Calvetti, Marcella Carissimi, Marco Pasotti
  • Patent number: 10318372
    Abstract: Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Jae-Kwan Park
  • Patent number: 10311919
    Abstract: Apparatuses and methods for calibrating sense amplifiers in a semiconductor memory are disclosed. An example apparatus includes an amplifier circuit and a calibration circuit. The amplifier circuit is configured to be coupled to a supply voltage and a reference voltage, and when activated the amplifier circuit is configured to provide an output signal at an output that is complementary to an input signal provided to an input. When activated by a calibration signal, the calibration circuit is configured to provide a calibration voltage to the output of the amplifier circuit, wherein the calibration voltage is an equilibration voltage between the supply voltage and the reference voltage provided to the amplifier circuit.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 4, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Stefan Frederik Schippers
  • Patent number: 10297303
    Abstract: A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. The virtual ground circuitry is configured to provide a virtual ground at a first bias voltage potential to a conductive line operably coupled to a selected ferroelectric memory cell, and discharge the conductive line to the sense node responsive to the selected ferroelectric memory cell changing from a first polarization state to a second polarization state. A method includes applying a second bias voltage potential to another conductive line operably coupled to the selected ferroelectric memory cell, and comparing a sense node voltage potential to a reference voltage potential. Electrical systems and computing devices include virtual ground sensing circuits.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Giulio Giuseppe Marotta, Marco Domenico Tiburzi
  • Patent number: 10224086
    Abstract: A memory device includes at least one reference cell and multiple memory cells. A method of operating the memory device may include detecting a temperature of the memory device and controlling a level of a first read signal applied to the at least one reference cell in accordance with a result of the detecting of the temperature. The method may also include comparing a first sensing value sensed by applying the first read signal to the at least one reference cell with a second sensing value sensed by applying a second read signal to a selected memory cell among the multiple memory cells.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Shik Kim, Suk-Soo Pyo, Gwan-Hyeob Koh
  • Patent number: 10211064
    Abstract: A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Eduard A. Cartier, Chandrasekharan Kothandaraman
  • Patent number: 10153007
    Abstract: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Harish N. Venkata, John F. Schreck, Mansour Fardad
  • Patent number: 10109362
    Abstract: A semiconductor device includes a fuse array section suitable for performing program and read operations; a control signal generation section suitable for generating a precharge control signal and a word line control signal; a bit line control section suitable for controlling a precharge operation of a bit line in response to the precharge control signal and a source signal; and a word line control section suitable for controlling activation of a program word line and a read word line for performing the program and read operations in response to the word line control signal, wherein the control signal generation section controls the word line control signal to be activated after a predetermined time from the activation of the precharge control signal.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: October 23, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jeong-Tae Hwang
  • Patent number: 10102913
    Abstract: A controlling method of a semiconductor device provided with a memory array including a plurality of complementary cells, each cell including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, the controlling method comprising: performing a prewrite procedure that writes ‘0’ or ‘1’ to both of the first memory element and the second memory element.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: October 16, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masamichi Fujito, Hiroshi Yoshida, Takanori Takahashi, Yasuhiko Taito
  • Patent number: 10095617
    Abstract: A memory device includes an input/output interface configured to receive and output signals. The input/output interface is configured to receive a memory address to be accessed and data sequence information within a clock cycle or at a rising or falling edge of a clock cycle. The data sequence information specifies an input or output data sequence.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: October 9, 2018
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuen-Long Chang, Su-Chuch Lo, Chao Hsin Lin, Ken-Hui Chen
  • Patent number: 10032415
    Abstract: The present invention provides a pixel circuit and a driving method thereof and a display device. The pixel circuit comprises a driving transistor, a storage capacitor, an organic light emitting device, a reset unit, a data writing unit and a voltage output unit. The reset unit is connected to a reset control signal line, an initialization signal line, the data writing unit, two ends of the storage capacitor, the voltage output unit, and a first electrode and a control electrode of the driving transistor. The control electrode of the driving transistor is connected to the second end of the storage capacitor, the first electrode thereof is connected to the voltage output unit, the second electrode thereof is connected to the organic light emitting device. The data writing unit is connected to a gate line, a data line and the first end of the storage capacitor.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: July 24, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zhanjie Ma
  • Patent number: 10013197
    Abstract: The present disclosure includes apparatuses and methods related to a shift skip. An example apparatus comprises a plurality of sensing circuitries, comprising respective sense amplifiers and respective compute components. A controller is configured to, responsive to a mask data unit associated with a first sensing circuitry having a particular value, cause a data value to be shifted from a second sensing circuitry to a third sensing circuitry without shifting the data value to the first sensing circuitry, wherein the first sensing circuitry is physically located between the second sensing circuitry and the third sensing circuitry.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Gary L. Howe, Harish N. Venkata
  • Patent number: 10008273
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: June 26, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Biswajit Ray, Gerrit Jan Hemink, Mohan Dunga, Bijesh Rajamohanan, Changyuan Chen
  • Patent number: 9838014
    Abstract: A data transmission circuit may include a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal, and a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 5, 2017
    Assignee: SK hynix Inc.
    Inventor: Sang Jin Byeon
  • Patent number: 9825042
    Abstract: In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m_1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 9799408
    Abstract: A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: October 24, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Stephen Keith Heinrich-Barna, Raviprakash Suryanarayana Rao