Sipo/piso Patents (Class 365/219)
  • Patent number: 9870725
    Abstract: The present invention relates to a transmission interface. A display device comprises a driving circuit and a transmission interface. The transmission method of the transmission interface is that a first input is used for receiving a first data string; a second input is used for receiving a second data string; and the processing unit receives the first and second data strings. The first data string has a first identification bit and a plurality of first information bits. The second data string has a plurality of second information bits. The processing unit identifies either to write a plurality of parameters or a plurality of data to a storage circuit or to read the stored content from the storage circuit according to the first identification bit and the plurality of first information bits. The processing circuit further writes or reads the storage circuit according to the plurality of second information bits.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: January 16, 2018
    Assignee: Sitronix Technology Corp.
    Inventors: Tsun-Sen Lin, Min-Nan Liao
  • Patent number: 9705620
    Abstract: A memory controller is provided to increment a source timestamp count responsive to a clock signal. Further, the memory controller associates the source timestamp count to a respective word for each endpoint in a plurality of endpoints. The memory controller transmits the received clock signal, a respective data word, and an associated source count to each endpoint. Each endpoint increments a destination count responsive to the clock signal. Each endpoint further transmits its respective word to an external memory responsive to the destination count being greater than or equal to the associated source count by a threshold margin.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: July 11, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Philip Michael Clovis, Michael Drop, Isaac Berk
  • Patent number: 9269421
    Abstract: A semiconductor memory may include: a storage unit suitable for storing a minimum operation interval between row command operations, a detection unit suitable for detecting whether row command signals inputted for the row command operations are activated at the minimum operation interval, a latching unit suitable for generating flag signals by latching the row command signals, and a shifting unit suitable for shifting the flag signals based on the minimum operation interval in response to an output signal of the detection unit, and generating an internal row command signals.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: February 23, 2016
    Assignee: SK Hynix Inc.
    Inventor: Kyong-Ha Lee
  • Patent number: 9159444
    Abstract: A semiconductor device includes at least one first row selection line, at least one column selection line that intersects with the first row selection line, and a first fuse circuit including a first fuse array, and suitable for outputting a first fuse signal programmed in the first fuse array by using an external voltage as a source voltage in a power-up mode, wherein the first fuse array includes at least one first fuse cell coupled with the first row selection line and the column selection line.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: October 13, 2015
    Assignee: SK Hynix Inc.
    Inventor: Yeon-Uk Kim
  • Patent number: 9153292
    Abstract: An integrated circuit device having memory is disclosed. The integrated circuit device comprises programmable resources; programmable interconnect elements coupled to the programmable resources, the programmable interconnect elements enabling a communication of signals with the programmable resources; a plurality of memory blocks; and dedicated interconnect elements coupled to the plurality of memory blocks, the dedicated interconnect elements enabling access to the plurality of memory blocks. A method of implementing memory in an integrated circuit device is also disclosed.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: October 6, 2015
    Assignee: XILINX, INC.
    Inventor: Ephrem C. Wu
  • Publication number: 20150117130
    Abstract: Serial input devices (e.g., pin electronics modules) are coupled to an interface via data lines, clock lines, and select lines. A first subset and a second subset of the devices are each arrayed in columns, rows, and layers. Each data line is coupled to a respective row in the first subset and a respective row in the second subset; each clock line is coupled to a respective column in the first subset and a respective column in the second subset; and each layer in each subset is coupled to a respective select line. The interface can program a device by concurrently activating one of the data lines, one of the clock lines, and one of the select lines.
    Type: Application
    Filed: October 29, 2013
    Publication date: April 30, 2015
    Inventors: Michael JONES, David ESKELDSON, Darrin ALBERS
  • Patent number: 9001607
    Abstract: A non-volatile memory (NVM) system compatible with double data rate, single data rate, or other high speed serial burst operation. The NVM system includes input and output circuits adapted to synchronously send or receive back-to-back continuous bursts of serial data at twice the frequency of any clock input. Each burst is J bits in length. The NVM system includes read and write circuits that are adapted to read or write J bits of data at a time and in parallel, for each of a multitude of parallel data paths. Data is latched such that write time is similar for each bit and is extended to the time it takes to transmit an entire burst. Consequently, the need for small and fast sensing circuits on every column of a memory array, and fast write time at twice the frequency of the fastest clock input, are relieved.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: April 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Adrian E. Ong
  • Patent number: 8934316
    Abstract: A parallel-serial conversion circuit includes an adjustment circuit that receives a parallel input signal having a plurality of bits and generates and outputs a parallel output signal having a plurality of bits. A conversion circuit coupled to the adjustment circuit generates a plurality of clock signals having mutually different phases with respect to a reference clock signal on the basis of the reference clock signal and serially selects the plurality of bits of the parallel output signal in accordance with the generated plurality of clock signals to convert the parallel output signal to serial 1-bit output signals. The adjustment circuit adjusts the output timing of each of the plurality of bits of the parallel output signal in time unit of half of one cycle of the reference clock signal.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichiro Ikeda, Kazumi Kojima, Hiroyuki Sano
  • Patent number: 8908452
    Abstract: A semiconductor memory apparatus includes a data alignment control signal generation unit configured to output a data alignment control signal by generating a pulse when a tuning mode signal is enabled, and generate the data alignment control signal as a count pulse is inputted after the data alignment control signal generated by the tuning mode signal is outputted; a timing control block configured to determine a delay amount according to delay codes, generate a delay control signal by delaying the data alignment control signal, and output a timing control signal by latching the delay control signal at an enable timing of a data output control signal; a delay time control block configured to generate the delay codes; and a data alignment unit configured to convert parallel data into serial data, and change a data sequence of the serial data in response to the timing control signal.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jin Youp Cha, Jae Il Kim
  • Patent number: 8780645
    Abstract: The data input circuit of a nonvolatile memory device includes a redundancy multiplexer configured to selectively output normal data and redundancy data to an internal global data line in response to a redundancy signal, a plurality of pipe registers coupled to the internal global data line and configured to latch normal data or redundancy data received through the internal global data line in response to a plurality of respective latch signals, and an output multiplexer configured to sequentially output the latched data in response to a plurality of selection signals.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: July 15, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jong Tai Park, Won Sub Song
  • Publication number: 20140192601
    Abstract: A multi-port memory device includes a plurality of serial I/O data pads for providing a serial input/output (I/O) data communication; a plurality of ports for performing the serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data communication with the ports; a plurality of first data buses for transferring first signals from the ports to the banks; a plurality of second data buses for transferring second signals from the banks to the ports; and a switching unit for connecting the first data buses with the second data buses in response to a control signal.
    Type: Application
    Filed: January 9, 2013
    Publication date: July 10, 2014
    Inventor: Chang-Ho Do
  • Patent number: 8755236
    Abstract: A latch system applied to a plurality of banks of a memory circuit includes a front latch circuit and a plurality of rear latch circuit. The front latch circuit is used for receiving a datum and a front latch enabling signal, and generating and outputting an intermediate signal according to the datum and the front latch enabling signal. Each rear latch circuit of the plurality of rear latch circuits is coupled to an output terminal of the front latch circuit for receiving the intermediate signal, and generating and outputting a rear latch datum to a corresponding bank of the plurality of banks according to the intermediate signal and a corresponding rear latch enabling signal, where only one rear latch enabling signal is enabled at any time.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: June 17, 2014
    Assignee: Etron Technology, Inc.
    Inventors: Chun Shiah, Shi-Huei Liu, Cheng-Nan Chang
  • Patent number: 8743642
    Abstract: Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals having phases that are equally phased apart from each other. Such a data serializer may use the clock signals to generate data sample signals having a value corresponding to the value of a respective one of the parallel data digits and a timing corresponding to a respective one of the clock signals. The data sample signals may be applied to a switching circuit that includes a plurality of switches, such as respective transistors, coupled to each other in parallel between an output node and a first voltage.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Seong-Hoon Lee
  • Patent number: 8687449
    Abstract: A semiconductor device according to the present invention includes plural core chips CC0 to CC7 to which mutually different pieces of chip identification information LID are allocated, and an interface chip IF that controls the core chips CC0 to CC7. The interface chip IF receives address information ADD for specifying a memory cell, and supplies in common a part of the address information to the core chips CC0 to CC7 as chip selection information SEL to be compared with the chip identification information LID. With this configuration, it appears from a controller that an address space is simply enlarged. Therefore, an interface that is same as that for a conventional semiconductor memory device can be used.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: April 1, 2014
    Assignee: Elpida Memory, Inc.
    Inventor: Hideyuki Yoko
  • Patent number: 8654601
    Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: February 18, 2014
    Assignee: MOSAID Technologies Incorporated
    Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
  • Patent number: 8582383
    Abstract: A semiconductor memory device includes a memory cell array having plural memory cells that require a refresh operation when retaining data; a read/write control unit that performs read-access or write-access of memory cell address specified for the memory cell array based on instructions from the outside; a refresh control unit that performs hidden-refresh of memory cells without control from the outside; and a schedule control unit that makes the refresh control unit perform hidden-refresh after the read/write control unit read-accesses the memory cell array, and that also makes the refresh control unit perform hidden-refresh before the read/write access control unit performs write-access.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: November 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyuki Takahashi
  • Patent number: 8582382
    Abstract: A semiconductor memory device and system are disclosed. The memory device includes a memory, a plurality of inputs, and a device identification register for storing register bits that distinguish the memory device from other possible memory devices. Circuitry for comparing identification bits in the information signal with the register bits provides positive or negative indication as to whether the identification bits match the register bits. If the indication is positive, then the memory device is configured to respond as having been selected by a controller. If the indication is negative, then the memory device is configured to respond as having not been selected by the controller. A plurality of outputs release a set of output signals towards a next device.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: November 12, 2013
    Assignee: MOSAID Technologies Incorporated
    Inventor: HakJune Oh
  • Patent number: 8547775
    Abstract: The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip selection information for comparison with the chip identification information to the plural core chips. As a result, since the controller recognizes that an address space is simply enlarged, the same interface as that in the semiconductor memory device according to the related art can be used.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: October 1, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hideyuki Yoko
  • Patent number: 8514640
    Abstract: A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and t
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: August 20, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Miakashi, Katsuaki Isobe, Noboru Shibata
  • Patent number: 8509020
    Abstract: A data processing system includes a first semiconductor device that has a plurality of blocks each including plural data, and a second semiconductor device that has a first control circuit controlling the first semiconductor device, and the first control circuit issues a plurality of commands to communicate with the first semiconductor device in units of access units including a plurality of first definitions that define a plurality of burst lengths indicating numbers of different data, respectively, and a plurality of second definitions that define correspondences between certain elements of data among the plural data included in the blocks, respectively, and arrangement orders in the numbers of different data that constitute the burst lengths, respectively, and communicates with the first semiconductor device through the plural data in the numbers of different data according to the first and second definitions.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: August 13, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 8493808
    Abstract: A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: July 23, 2013
    Assignee: Mosaid Technologies Incorporated
    Inventor: Hong Beom Pyeon
  • Publication number: 20130155792
    Abstract: Disclosed herein is a semiconductor device that includes: a frequency dividing circuit dividing a frequency of a first clock signal to generate second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal; a data input/output terminal; data buses; and a data input/output circuit coupled between the data input/output terminal and the data buses. The data input/output circuit includes a data output circuit and a data input circuit. The data output circuit outputs read data supplied in parallel from the data buses to the data input/output terminal in serial in synchronism with the third clock signal. The data input circuit outputs write data supplied in serial from the data input/output terminal to the data buses in parallel in synchronism with a predetermined one of the second clock signals.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 20, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: ELPIDA MEMORY, INC.
  • Patent number: 8446793
    Abstract: A clock control circuit includes a first clock buffer configured to toggle a first clock signal when a self-refresh exit command signal is inputted during a self-refresh operation; and a second clock buffer configured to toggle a second clock signal when the self-refresh operation is finished, the second clock being provided to internal circuits.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: May 21, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Choung-Ki Song
  • Patent number: 8427897
    Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: April 23, 2013
    Assignee: MOSAID Technologies Incorporated
    Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
  • Publication number: 20130094302
    Abstract: An integrated circuit chip includes an internal circuit configured to generate output data, an inversion determination unit configured to activate/deactivate an inversion signal according to state information regarding a state of the integrate circuit chip, and a signal output circuit configured to invert or not to invert the output data in response to the inversion signal and output the inverted or non-inverted output data.
    Type: Application
    Filed: December 19, 2011
    Publication date: April 18, 2013
    Inventor: Chang-Ho Do
  • Patent number: 8358553
    Abstract: An integrated circuit can include an input/output (I/O) bank. The I/O bank can include a plurality of byte clock groups. Each byte clock group can include at least one phaser configured to clock circuit elements of the byte clock group at a frequency at which a source synchronous device coupled to the byte clock group communicates data.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: January 22, 2013
    Assignee: Xilinx, Inc.
    Inventors: David P. Schultz, Sanford L. Helton, Richard W. Swanson
  • Patent number: 8331122
    Abstract: A semiconductor device includes plural core chips and an interface chip that controls the plural core chips. Each of the plural core chips includes a layer address generating circuit that generates a second chip address by incrementing a value of a first chip address and a layer address comparing circuit that compares a third chip address supplied from the interface chip and the second chip address, and activates a chip selection signal when the third chip address and the second chip address are matched with each other. When a non-used chip signal is in an inactivated state, the layer address generating circuit supplies the second chip address to another core chip, and when the non-used chip signal is in an activated state, the layer address generating circuit supplies the first chip address to another core chip without a change.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: December 11, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Homare Sato, Junichi Hayashi
  • Patent number: 8325537
    Abstract: To provide a semiconductor memory device including a mode register in which a mode signal is set, a data amplifier that amplifies read data read from a memory cell array, a data bus onto which the read data amplified by the data amplifier is transmitted, a data input/output circuit that outputs a signal on the data bus to outside, and a mode signal output circuit that outputs the mode signal set in the mode register onto the data bus. Because the mode signal is not caused to interrupt halfway along the data input/output circuit, but supplied onto the data bus that connects the data amplifier to the data input/output circuit, no collision of the read data with the mode signal occurs in the data input/output circuit.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: December 4, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Atsushi Shimizu, Takahiko Fukiage
  • Patent number: 8300487
    Abstract: A semiconductor device comprises a plurality of terminals, a plurality of drive units corresponding to the plurality of terminals, and a data control unit. The data control unit outputs parallel data applied to the plurality of terminals to the plurality of drive unit in a normal operation mode, and converts serial data applied to a particular terminal, which is one of the plurality of terminals, to parallel data, and outputs the parallel data to which the serial data applied to the particular terminal is converted to the plurality of drive units in a test mode.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: October 30, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Tomonori Hayashi
  • Patent number: 8295100
    Abstract: A pipe latch circuit includes a division unit configured to output a division signal, a multiplexing unit configured to multiplex a plurality of source signals according to periods determined by the division signal and generate a plurality of pipe input control signals, and a pipe latch unit configured to sequentially latch a plurality of data signals in response to the pipe input control signals, wherein the source signals are sequentially activated in response to an input/output (I/O) strobe signal.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: October 23, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyeng-Ouk Lee
  • Publication number: 20120243361
    Abstract: Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals having phases that are equally phased apart from each other. Such a data serializer may use the clock signals to generate data sample signals having a value corresponding to the value of a respective one of the parallel data digits and a timing corresponding to a respective one of the clock signals. The data sample signals may be applied to a switching circuit that includes a plurality of switches, such as respective transistors, coupled to each other in parallel between an output node and a first voltage.
    Type: Application
    Filed: June 7, 2012
    Publication date: September 27, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Seong-Hoon Lee
  • Patent number: 8274857
    Abstract: A semiconductor memory device capable of reducing off-current in a standby mode is provided. The semiconductor memory device includes an enable signal generating unit configured to receive a plurality of address decoding signals and generate a first enable signal to select a first cell block and a second enable signal to select a second cell block, and an internal voltage generating unit for generating an internal voltage by controlling a supply of a first voltage in accordance with the first or second enable signals.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 25, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Il Park
  • Publication number: 20120230137
    Abstract: A memory device includes a first bank, a second bank, a plurality of interface pads, and a data output unit configured to output compressed data of the first bank through at least one interface pad among the plurality of interface pads and subsequently output compressed data of the second bank through the one interface pad.
    Type: Application
    Filed: August 9, 2011
    Publication date: September 13, 2012
    Inventor: Kang-Youl LEE
  • Patent number: 8243543
    Abstract: Semiconductor memory device for high-speed data input/output includes a first serializer configured to partially serialize input 8-bit parallel data to output first to fourth serial data, a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data and a third serializer configured to serialize the fifth and sixth serial data to output seventh serial data.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: August 14, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Beom-Ju Shin, Sang-Sic Yoon
  • Patent number: 8238186
    Abstract: A semiconductor memory device is capable of performing a stable high-speed operation while inputting/outputting data. The semiconductor memory device includes an inversion output circuit configured to output a clocking pattern in a clocking mode, and an inversion pin to which the inversion output circuit is connected.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: August 7, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ji-Hyae Bae, Sang-Sie Yoon
  • Publication number: 20120195134
    Abstract: A data alignment circuit includes: a select transmission unit configured to selectively transmit a first pulse or ground voltage as a first control pulse and selectively transmit a second pulse or ground voltage as a second control pulse, in response to a control signal; and a data latch unit configured to latch data in response to the first and second pulses and the first and second control pulses, and generate first to fourth data.
    Type: Application
    Filed: January 24, 2012
    Publication date: August 2, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Tae Jin KANG
  • Publication number: 20120195148
    Abstract: A semiconductor device according to the present invention includes plural core chips CC0 to CC7 to which mutually different pieces of chip identification information LID are allocated, and an interface chip IF that controls the core chips CC0 to CC7. The interface chip IF receives address information ADD for specifying a memory cell, and supplies in common a part of the address information to the core chips CC0 to CC7 as chip selection information SEL to be compared with the chip identification information LID. With this configuration, it appears from a controller that an address space is simply enlarged. Therefore, an interface that is same as that for a conventional semiconductor memory device can be used.
    Type: Application
    Filed: February 7, 2011
    Publication date: August 2, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hideyuki Yoko
  • Patent number: 8233344
    Abstract: A semiconductor device includes a plural number of sense amplifiers that sense at least two data in parallel and that operate under a first frequency, and a multiplexer that operates under a second frequency higher than the first frequency and that sequentially serially outputs the data sensed in parallel. The semiconductor device also includes a driver circuit having a latch circuit connected to an output of the multiplexer, and an output driver circuit connected to the latch circuit and operating under the second frequency. The voltage of a power supply of the sense amplifiers is the same as the voltage of a power supply of the output driver circuit. The power supply of the sense amplifiers and the power supply of the output driver circuit are connected to respective different power supply lines.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: July 31, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Noriaki Mochida
  • Patent number: 8218388
    Abstract: Provided is a read circuit for a semiconductor memory device which may have a reduced circuit scale, and a semiconductor memory device. In a plurality of sense amplifiers of the read circuit of the semiconductor memory device, for serially reading data from a serial output terminal, if a number of byte selectors which may be selected to determine an address at a predetermined time before determination of the address is four, only four sense amplifiers are required in total, and hence the read circuit and the semiconductor memory device are reduced in circuit scale.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: July 10, 2012
    Assignee: Seiko Instruments Inc.
    Inventor: Tetsuya Kaneko
  • Patent number: 8203900
    Abstract: Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals having phases that are equally phased apart from each other. Such a data serializer may use the clock signals to generate data sample signals having a value corresponding to the value of a respective one of the parallel data digits and a timing corresponding to a respective one of the clock signals. The data sample signals may be applied to a switching circuit that includes a plurality of switches, such as respective transistors, coupled to each other in parallel between an output node and a first voltage.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: June 19, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Seong-Hoon Lee
  • Patent number: 8199598
    Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: June 12, 2012
    Assignee: MOSAID Technologies Incorporated
    Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
  • Publication number: 20120106279
    Abstract: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus includes a core block configured to receive and store external input data, a control unit configured to activate a control signal in response to a test mode signal and a command, when the external input data has a predetermined value, and a fuse circuit configured to perform fuse programming when the control signal is activated.
    Type: Application
    Filed: December 14, 2010
    Publication date: May 3, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Kie Bong KU
  • Patent number: 8159893
    Abstract: A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: April 17, 2012
    Assignee: MOSAID Technologies Incorporated
    Inventor: Hong Beom Pyeon
  • Publication number: 20110299351
    Abstract: An integrated circuit can include an input/output (I/O) bank. The I/O bank can include a plurality of byte clock groups. Each byte clock group can include at least one phaser configured to clock circuit elements of the byte clock group at a frequency at which a source synchronous device coupled to the byte clock group communicates data.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 8, 2011
    Applicant: XILINX, INC.
    Inventors: David P. Schultz, Sanford L. Helton, Richard W. Swanson
  • Patent number: 8068377
    Abstract: A semiconductor memory device capable of reducing off-current in a standby mode is provided. The semiconductor memory device includes an enable signal generating unit configured to receive a plurality of address decoding signals and generate a first enable signal to select a first cell block and a second enable signal to select a second cell block, and an internal voltage generating unit for generating an internal voltage by controlling a supply of a first voltage in accordance with the first or second enable signals.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: November 29, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Il Park
  • Patent number: 8045412
    Abstract: Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 25, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu, Hai Li, Andrew John Carter, Daniel Reed
  • Publication number: 20110255360
    Abstract: A semiconductor memory device includes a memory cell array having plural memory cells that require a refresh operation when retaining data; a read/write control unit that performs read-access or write-access of memory cell address specified for the memory cell array based on instructions from the outside; a refresh control unit that performs hidden-refresh of memory cells without control from the outside; and a schedule control unit that makes the refresh control unit perform hidden-refresh after the read/write control unit read-accesses the memory cell array, and that also makes the refresh control unit perform hidden-refresh before the read/write access control unit performs write-access.
    Type: Application
    Filed: March 23, 2011
    Publication date: October 20, 2011
    Inventor: Hiroyuki TAKAHASHI
  • Patent number: 8040740
    Abstract: A semiconductor device includes a data compression circuit that performs sequential processes based on timings of an external clock signal. The sequential processes include compressing data input in parallel, latching the compressed data, and outputting the latched data.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: October 18, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Atsuko Momma
  • Publication number: 20110242922
    Abstract: A semiconductor memory apparatus includes a first data selection section inputted with the first data and second data and output one of the first data and the second data as first selection data in response to an address signal, a second data selection section inputted with the second data and the first selection data and output one of the second data and the first selection data as second selection data depending upon an input and output mode, and a data output section configured to be inputted with the first and second selection data and output first and second output data.
    Type: Application
    Filed: June 13, 2011
    Publication date: October 6, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kyung Hoon KIM, Sang Sic YOON, Hong Bae KIM
  • Publication number: 20110216606
    Abstract: A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values.
    Type: Application
    Filed: March 31, 2010
    Publication date: September 8, 2011
    Inventors: Kwang-Hyun KIM, Kang-Youl Lee