Sipo/piso Patents (Class 365/219)
  • Publication number: 20110211411
    Abstract: To improve the access efficiency of a semiconductor memory that includes a plurality of memory chips. Based on a layer address, a bank address, and a row address received in synchronization with a row command, and a layer address, a bank address, and a column address received in synchronization with a column command, a memory cell selected by the row address and column address in a bank selected by the bank address included in a core chip selected by the chip address is accessed. This can increase the number of banks recognizable to a controller, thereby improving the memory access efficiency of the semiconductor device which includes the plurality of memory chips.
    Type: Application
    Filed: February 28, 2011
    Publication date: September 1, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Akira Ide
  • Publication number: 20110205824
    Abstract: A data processing system includes a first semiconductor device that has a plurality of blocks each including plural data, and a second semiconductor device that has a first control circuit controlling the first semiconductor device, and the first control circuit issues a plurality of commands to communicate with the first semiconductor device in units of access units including a plurality of first definitions that define a plurality of burst lengths indicating numbers of different data, respectively, and a plurality of second definitions that define correspondences between certain elements of data among the plural data included in the blocks, respectively, and arrangement orders in the numbers of different data that constitute the burst lengths, respectively, and communicates with the first semiconductor device through the plural data in the numbers of different data according to the first and second definitions.
    Type: Application
    Filed: February 23, 2011
    Publication date: August 25, 2011
    Applicant: ELPIDA MEMORY, INC
    Inventor: Kazuhiko Kajigaya
  • Patent number: 8000162
    Abstract: A voltage-controlled oscillator comprises a first oscillator and a second oscillator. The first oscillator may generate a plurality of intermediate clock signals at a plurality of first nodes, multiply connected to a plurality of first ring shape circuits, in response to a control voltage. The plurality of intermediate clock signals may have a different phase from each other and a same phase difference with each other. The second oscillator may generate a plurality of output clock signals at a plurality of second nodes, multiply connected to a plurality of second ring shape circuits, by changing a voltage level of the intermediate clock signals. The plurality of second ring shape circuits may pass the plurality of first nodes.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-Kyung Kim
  • Patent number: 7986584
    Abstract: A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: July 26, 2011
    Assignee: Rambus Inc.
    Inventors: Ely K. Tsern, Richard M. Barth, Craig E. Hampel, Donald C. Stark
  • Patent number: 7975162
    Abstract: An apparatus for aligning input data in a semiconductor device includes at least one alignment block and a decision block. The at least one alignment block is for aligning serial input data into groups of parallel data synchronized to at least one divided data strobe signal for increasing margin between the maximum and minimum tDQSS values. The decision block is for selecting one of the groups of parallel data as valid data in response to synchronization information generated for removing any invalid data in the serial input data resulting from a write gap.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Ho Kim, Kwang-Il Park
  • Publication number: 20110141828
    Abstract: To provide a semiconductor system including a plurality of core chips and an interface chip that controls the core chips. Each of the core chips includes an internal voltage generating circuit. The interface chip includes an unused chip information holding circuit that stores therein unused chip information of the core chips. The core chips respectively receive the unused chip information from the unused chip information holding circuit. When the unused chip information indicates an unused state, the internal voltage generating circuits are inactivated, and when the unused chip information indicates a used state, the internal voltage generating circuits are activated. With this configuration, unnecessary power consumption by the unused chips is reduced.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 16, 2011
    Applicant: Elpida Memory, Inc.
    Inventor: Hideyuki YOKO
  • Patent number: 7944767
    Abstract: Control information needed for executing data transmission/reception through a data terminal is received via its own control terminal in a first operation mode, and the control information is received by using the own control terminal and also a control terminal of at least one of the other ports in a second operation mode.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: May 17, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Toru Ishikawa, Sachiko Kamisaki
  • Publication number: 20110103164
    Abstract: A semiconductor memory device includes a plurality of data transmission lines, a plurality of parallel-to-serial conversion sections configured to receive, serially align, and output data from at least two of the plurality of data transmission lines, a plurality of data compression circuits configured to receive, compress, and output outputs of at least two of the plurality of parallel-to-serial conversion sections, and a plurality of data output circuits configured to output respective compression results of the plurality of data compression circuits to an outside of a chip.
    Type: Application
    Filed: December 24, 2009
    Publication date: May 5, 2011
    Inventors: Jae-Woong YUN, Jong-Chern Lee, Hee-Jin Byun
  • Patent number: 7929358
    Abstract: A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: April 19, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jun-Woo Lee, Dae-Han Kwon, Taek-Sang Song
  • Publication number: 20110085397
    Abstract: A semiconductor device includes plural core chips and an interface chip that controls the plural core chips. Each of the plural core chips includes a layer address generating circuit that generates a second chip address by incrementing a value of a first chip address and a layer address comparing circuit that compares a third chip address supplied from the interface chip and the second chip address, and activates a chip selection signal when the third chip address and the second chip address are matched with each other. When a non-used chip signal is in an inactivated state, the layer address generating circuit supplies the second chip address to another core chip, and when the non-used chip signal is in an activated state, the layer address generating circuit supplies the first chip address to another core chip without a change.
    Type: Application
    Filed: October 6, 2010
    Publication date: April 14, 2011
    Applicant: Elpida Memory, Inc.
    Inventors: Homare Sato, Junichi Hayashi
  • Patent number: 7885123
    Abstract: An integrated circuit for storing data, and for application in a memory card that operates in cooperation with at least one of an external acquisition system and an external processing system includes input/output terminals for receiving the data to be stored, and an electrically programmable non-volatile memory for storing the data in digital format. The memory includes a first terminal for receiving a programming signal for enabling storage of the data, and a second terminal for receiving a reading signal for enabling output of the stored data via the input/output terminals. A memory control circuit is connected to the first and second terminals of the electrically programmable non-volatile memory, and to the input/output terminals for generating programming and reading signals based upon the command signal. The electrically programmable non-volatile memory is erasable by electromagnetic radiation for permitting a non-electrical erasure of the stored data.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: February 8, 2011
    Assignee: STMicroelectronics S.R.L.
    Inventor: Paolo Rolandi
  • Publication number: 20110019475
    Abstract: A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and initiates data transfers for asynchronously writing the data portions into storage blocks interleaved among the flash storage devices. Additionally, the flash storage system may asynchronously read data portions of a data block interleaved among the storage blocks, store the data portions in the data buffer, and access the data portions from the data buffer.
    Type: Application
    Filed: July 23, 2009
    Publication date: January 27, 2011
    Applicant: STEC, INC.
    Inventor: Mark Moshayedi
  • Publication number: 20110013455
    Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.
    Type: Application
    Filed: September 10, 2010
    Publication date: January 20, 2011
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Jin-Ki KIM
  • Publication number: 20110007591
    Abstract: Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals having phases that are equally phased apart from each other. Such a data serializer may use the clock signals to generate data sample signals having a value corresponding to the value of a respective one of the parallel data digits and a timing corresponding to a respective one of the clock signals. The data sample signals may be applied to a switching circuit that includes a plurality of switches, such as respective transistors, coupled to each other in parallel between an output node and a first voltage. A bias element may bias the output node to a second voltage. Each of the switches may be controlled by a respective one of the sample signals.
    Type: Application
    Filed: July 9, 2009
    Publication date: January 13, 2011
    Applicant: Micron Technology, Inc.
    Inventor: Seong-Hoon Lee
  • Publication number: 20100309732
    Abstract: A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group.
    Type: Application
    Filed: December 24, 2009
    Publication date: December 9, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Hyung Soo Kim, Yong Ju Kim, Sung Woo Han, Hee Woong Song, Ic Su Oh, Tae Jin Hwang, Hae Rang Choi, Ji Wang Lee, Jae Min Jang, Chang Kun Park
  • Patent number: 7843743
    Abstract: A data output circuit for a semiconductor memory apparatus includes a data output control unit that generates a selection signal, an output timing signal, and an input control signal in response to a read command and a clock, and a signal-responsive data output unit that receives parallel data in response to the input control signal, arranges the parallel data in response to the selection signal, and sequentially outputs the arranged parallel data as serial data in synchronization with the output timing signal.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: November 30, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ji-Hyae Bae
  • Publication number: 20100296355
    Abstract: A semiconductor device includes a plural number of sense amplifiers that sense at least two data in parallel and that operate under a first frequency, and a multiplexer that operates under a second frequency higher than the first frequency and that sequentially serially outputs the data sensed in parallel. The semiconductor device also includes a driver circuit having a latch circuit connected to an output of the multiplexer, and an output driver circuit connected to the latch circuit and operating under the second frequency. The voltage of a power supply of the sense amplifiers is the same as the voltage of a power supply of the output driver circuit. The power supply of the sense amplifiers and the power supply of the output driver circuit are connected to respective different power supply lines.
    Type: Application
    Filed: May 20, 2010
    Publication date: November 25, 2010
    Applicant: Elpida Memory, Inc.
    Inventor: Noriaki MOCHIDA
  • Patent number: 7826294
    Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: November 2, 2010
    Assignee: Mosaid Technologies Incorporated
    Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
  • Patent number: 7817470
    Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.
    Type: Grant
    Filed: November 23, 2007
    Date of Patent: October 19, 2010
    Assignee: MOSAID Technologies Incorporated
    Inventor: Jin-Ki Kim
  • Patent number: 7804723
    Abstract: A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals in synchronization with a second clock signal of the internal clock; a second transferring unit for transferring the first signals in synchronization with the second clock signal of the internal clock; and an aligning unit for aligning the first and second signals transferred from the first and second transferring units and outputting the aligned signal as output signals.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 28, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hwang Hur, Chang-Ho Do
  • Patent number: 7782648
    Abstract: Correction data is written in fuse circuits of q bits. A reading circuit sequentially reads information of the fuse circuits through a selector and writes the information in a storage circuit. Therefore, read data is output from the storage circuit in parallel.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: August 24, 2010
    Assignees: Sanyo Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventors: Yuichi Matsuo, Takahisa Nakai
  • Patent number: 7782682
    Abstract: A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: August 24, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yasurou Matsuzaki, Masao Taguchi
  • Patent number: 7773453
    Abstract: Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the incrementing of the pointers in the peek address logic, so that after a read enable signal is asserted, the same data block can be accessed again on the next read enable signal.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: August 10, 2010
    Assignee: LSI Corporation
    Inventors: Jerzy Szwagrzyk, Jeffrey K. Whitt
  • Publication number: 20100195413
    Abstract: To provide a semiconductor memory device including a mode register in which a mode signal is set, a data amplifier that amplifies read data read from a memory cell array, a data bus onto which the read data amplified by the data amplifier is transmitted, a data input/output circuit that outputs a signal on the data bus to outside, and a mode signal output circuit that outputs the mode signal set in the mode register onto the data bus. Because the mode signal is not caused to interrupt halfway along the data input/output circuit, but supplied onto the data bus that connects the data amplifier to the data input/output circuit, no collision of the read data with the mode signal occurs in the data input/output circuit.
    Type: Application
    Filed: February 4, 2010
    Publication date: August 5, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Atsushi SHIMIZU, Takahiko Fukiage
  • Publication number: 20100195428
    Abstract: A semiconductor device comprises a plurality of terminals, a plurality of drive units corresponding to the plurality of terminals, and a data control unit. The data control unit outputs parallel data applied to the plurality of terminals to the plurality of drive unit in a normal operation mode, and converts serial data applied to a particular terminal, which is one of the plurality of terminals, to parallel data, and outputs the parallel data to which the serial data applied to the particular terminal is converted to the plurality of drive units in a test mode.
    Type: Application
    Filed: January 28, 2010
    Publication date: August 5, 2010
    Applicant: Elpida Memory, Inc.
    Inventor: Tomonori HAYASHI
  • Patent number: 7751269
    Abstract: Embodiments of the invention relate generally to a coupling device, to a processor arrangement, to a data processing arrangement, and to methods for transmitting data. In an embodiment of the invention, a coupling device for coupling a memory, which has a serial data output, with a processor, which has a parallel data input, is provided. The coupling device may include a serial data interface configured to receive data, a parallel data interface configured to transmit data, and a cache memory coupled to the serial data interface and to the parallel data interface, wherein the cache memory is configured to receive and store data, which have been received in a serial data format via the serial data interface, and to transmit data stored in the cache memory to the parallel data interface.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: July 6, 2010
    Assignee: Infineon Technologies AG
    Inventors: Daniel Bergmann, Christian Erben, Eric Labarre
  • Publication number: 20100157644
    Abstract: The invention relates to an interface for providing multiple modes of accessing data, including serial and parallel modes. Controllable non-volatile memory interfaces are described, including a serial module configured to provide a serial connection between a non-volatile memory array and another non-volatile memory array. The serial module can provide access to the non-volatile memory array. A mode module can be configured to determine which type of interface operation (i.e., serial mode or parallel mode) will be used for the non-volatile memory array and the another non-volatile memory array. In some cases, a controller can be configured to select the serial module independent of the mode module. Circuitry for performing data operations on the non-volatile memories can be fabricated FEOL on a substrate and the non-volatile memories can be fabricated BEOL directly on top of the substrate in one or more layers of memory.
    Type: Application
    Filed: October 13, 2009
    Publication date: June 24, 2010
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventor: Robert Norman
  • Publication number: 20100124137
    Abstract: A voltage-controlled oscillator comprises a first oscillator and a second oscillator. The first oscillator may generate a plurality of intermediate clock signals at a plurality of first nodes, multiply connected to a plurality of first ring shape circuits, in response to a control voltage. The plurality of intermediate clock signals may have a different phase from each other and a same phase difference with each other. The second oscillator may generate a plurality of output clock signals at a plurality of second nodes, multiply connected to a plurality of second ring shape circuits, by changing a voltage level of the intermediate clock signals. The plurality of second ring shape circuits may pass the plurality of first nodes.
    Type: Application
    Filed: November 9, 2009
    Publication date: May 20, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Chan-Kyung Kim
  • Patent number: 7719904
    Abstract: A data input circuit for a semiconductor memory apparatus includes a data latch block that, according to a data strobe signal, latches data and outputs the latched data; a data output controlling unit that determines a phase difference between the data strobe signal and a clock signal, and activates a data output control signal; and a data delay block that, when the data output control signal is activated, delays the data output from the data latch block for a predetermined time, and outputs the delayed data.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: May 18, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kang-Youl Lee
  • Patent number: 7719922
    Abstract: An address counter includes FIFO units and first to third command counters that controls the groups. In the FIFO units, latch circuits including input gates and output gates are connected in parallel. The first command counter conducts any one of the input gates in response to a first internal command; the second command counter conducts any one of the output gates in response to a second internal command; and the third command counter conducts any one of the output gates in response to a third internal command. Thereby, the same address signals can be outputted successively at a plurality of timings, and thus, a circuit scale of the address counter can be reduced.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: May 18, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroki Fujisawa
  • Publication number: 20100118635
    Abstract: A semiconductor memory device is capable of performing a stable high-speed operation while inputting/outputting data. The semiconductor memory device includes an inversion output circuit configured to output a clocking pattern in a clocking mode, and an inversion pin to which the inversion output circuit is connected.
    Type: Application
    Filed: November 5, 2009
    Publication date: May 13, 2010
    Inventors: Ji-Hyae BAE, Sang-Sie Yoon
  • Patent number: 7715261
    Abstract: Embodiments of the invention provide a layout for a semiconductor memory device that splits each memory bank into two blocks. Embodiments of the invention dispose input/output sense amplifiers between the two memory blocks to achieve relatively short global input/output lines to all areas of the memory bank. Shorter global input/output lines have less loading and therefore enable higher-speed data transfer rates. Some embodiments of the invention include column selection line repeaters between the two memory blocks. The column selection line repeaters reduce loading in the column selection lines, and increase column selection speed. Embodiments of the invention include both input/output sense amplifiers and column selection line repeaters disposed between the two memory blocks to increase data transfer rates on the global input/output lines and also increase column selection speed.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: May 11, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Young Kim, Byung-Chul Kim
  • Publication number: 20100110800
    Abstract: A data output circuit includes a strobe signal controlling block configured to generate a first delayed strobe signal by delaying a first strobe signal by a certain delay amount, an input/output sense amplifying block configured to amplify first parallel data signals to generate second parallel data signals having the same number of bits as that of the first parallel data signals in response to the first strobe signal and the first delayed strobe signal, a storing block configured to latch the second parallel data signals in response to a second strobe signal and a second delayed strobe signal, and a parallel-to-serial converting block configured to sequentially output the second parallel data signals latched in the storing block, wherein the first strobe signal is used to generate a data signal that is outputted first among the second parallel data signals.
    Type: Application
    Filed: December 24, 2008
    Publication date: May 6, 2010
    Inventor: Kang-Youl LEE
  • Publication number: 20100110802
    Abstract: A semiconductor device includes a data compression circuit that performs sequential processes based on timings of an external clock signal. The sequential processes include compressing data input in parallel, latching the compressed data, and outputting the latched data.
    Type: Application
    Filed: October 27, 2009
    Publication date: May 6, 2010
    Applicant: Elpida Memory, Inc.
    Inventor: Atsuko Momma
  • Publication number: 20100110747
    Abstract: The semiconductor memory device proposed in the present invention comprises memory cells disposed in the row direction and the column direction, a plurality of first lines by which supply voltages are supplied in order to select memory cells disposed in the row direction among the plurality of cells, a plurality of second lines by which supply voltages are supplied in order to select memory cells disposed in the column direction among the plurality of cells, the data lines which input and output the data to the selected memory cells, the first power voltage supply circuit which supplies the predetermined supply voltages to the first lines corresponding with the externally input row address synchronizing with an act command, and the second power voltage supply circuit which supplies the predetermined supply voltages to the second lines corresponding with the externally input column address synchronizing with an act command.
    Type: Application
    Filed: January 31, 2007
    Publication date: May 6, 2010
    Applicant: LIQUID DESIGN SYSTEMS, INC.
    Inventors: Yuji Nakaoka, Shin-ichi Iwashita
  • Patent number: 7697363
    Abstract: A memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device includes at least one data input port and at least one data output port for communicating data along the daisy-chain between the memory devices and the memory controller. The memory device is adapted to selectively enable/disable at least one of the data input or data output ports in response to whether a command received from the memory controller is intended for the memory device, or for one of the other memory devices.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: April 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hoe-Ju Chung
  • Publication number: 20100074039
    Abstract: A semiconductor memory device includes a memory cell array, a data input/output terminal, a data input/output circuit, and a test circuit. The data input/output circuit is provided between the memory cell array and the data input/output terminal. The data input/output circuit includes a main amplifier that amplifies data written into selected memory cells in the memory cell array during data write operation and that amplifies data read from the selected memory cells during read operation, and a memory element provided accompanying the main amplifier in order to repair a defective memory cell in the memory cell array. The test circuit starts up in test mode, writes data into the memory element through the data input/output terminal, and read data from the memory element into the data input/output terminal regardless of access address information to the memory cell.
    Type: Application
    Filed: September 22, 2009
    Publication date: March 25, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Chikara Kondo
  • Publication number: 20100061157
    Abstract: A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data.
    Type: Application
    Filed: December 3, 2008
    Publication date: March 11, 2010
    Inventors: Jun-woo Lee, Dae-Han Kwon, Taek-Sang Song
  • Publication number: 20100054059
    Abstract: A circuit which can reduce time taken by a clock alignment training operation in a semiconductor memory device is provided. The semiconductor memory device, which includes: a clock inputting unit configured to receive a system clock and a data clock; a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock, wherein the clock dividing unit determines a phase of the data division clock in response to an inversion division control signal; a phase dividing unit configured to generate a plurality of multiple phase data division clocks having respective predetermined phase differences in response to the data division clock; a data serializing unit configured to serialize predetermined parallel pattern data in correspondence with the multiple phase data division clocks; and a signal transmitting unit configured to transmit an output signal of the data serializing unit to the outside.
    Type: Application
    Filed: December 3, 2008
    Publication date: March 4, 2010
    Inventors: Sang-Sic Yoon, Kyung-Hoon Kim
  • Publication number: 20100054046
    Abstract: A semiconductor memory device capable of reducing a whole area thereof includes a plurality of data input circuits configured to reflect inversion information on data inputted thereto, a plurality of global lines for transferring data outputted from the plurality of data input circuits, and a plurality of memory banks for storing data transferred from the plurality of global lines.
    Type: Application
    Filed: December 3, 2008
    Publication date: March 4, 2010
    Inventor: Ki-Chon PARK
  • Patent number: 7668039
    Abstract: An address counter includes FIFO units and first and second command counters that control the groups. The first command counter has a first mode in which any one of input gates is conducted in response to a first internal command and a second mode in which a plurality of input gates are conducted in response to an internal command. The second command counter has a first mode in which any one of output gates is conducted in response to one of second and third internal commands and second mode in which corresponding output gates are each conducted in response to one of the second and third internal commands. Thereby, when tCCD is small, the first mode can be selected, and when the tCCD is large, the second mode can be selected.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: February 23, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroki Fujisawa
  • Patent number: 7661010
    Abstract: A delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: February 9, 2010
    Assignee: Mosaid Technologies Incorporated
    Inventors: Jody DeFazio, Oswald Becca, Peter Nyasulu
  • Patent number: 7649795
    Abstract: A memory system with a flexible serial interface and a memory accessing method thereof are provided. The memory system includes at least one of memories and a memory controller. The memory controller flexibly sets up serial link connection with each of the memories through serial ports regardless of a physical location and an order of the serial ports. The memory controller also transmits and receives memory data in a serial mode through the serial link connection.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: January 19, 2010
    Assignee: Electronics & Telecommunications Research Institute
    Inventors: Bup Joong Kim, Yong Wook Ra, Woo Young Choi, Byung Jun Ahn
  • Publication number: 20090316510
    Abstract: Control information needed for executing data transmission/reception through a data terminal is received via its own control terminal in a first operation mode, and the control information is received by using the own control terminal and also a control terminal of at least one of the other ports in a second operation mode.
    Type: Application
    Filed: June 19, 2009
    Publication date: December 24, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Toru ISHIKAWA, Sachiko KAMISAKI
  • Publication number: 20090303806
    Abstract: A semiconductor memory device may include,.but is not limited to, a storing unit and a selecting unit. The storing unit stores serial input data at at least one of a first type edge and a second type edge of a clock signal. The selecting unit receives the input data from the storing unit. The selecting unit selects the input data. The selecting unit outputs the selected input data in parallel.
    Type: Application
    Filed: October 30, 2008
    Publication date: December 10, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Sachiko EDO, Toru ISHIKAWA
  • Publication number: 20090296495
    Abstract: A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to capture respective bits of data corresponding to the data signal. A decoder receives a memory command signal and generates a data start signal after a delay period from receiving the memory command signal if the command signal corresponds to a read or a write command. The receipt of read or write command signals is used by a control circuit to identify the start of valid read or write data signals. The control circuit then outputs the captured data signals responsive to the data start signal, thereby ignoring the transitions in the preamble of the data strobe signal.
    Type: Application
    Filed: June 22, 2009
    Publication date: December 3, 2009
    Inventors: Joo S. Choi, James B. Johnson
  • Patent number: 7616518
    Abstract: A multi-port memory device includes a plurality of ports located at a center region of the multi-port memory device, each for performing a data communication with a corresponding external device; a plurality of banks arranged at upper and lower regions of the multi-port memory device in a row direction on the basis of the plurality of ports; and first and second global I/O data buses arranged in the row direction between the banks and the ports, each for independently performing a data transmission between the banks and the ports.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: November 10, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Hyuk Im, Chang-Ho Do
  • Patent number: 7596046
    Abstract: A data conversion circuit for a semiconductor memory apparatus includes a data conversion unit that has a plurality of latches for storing input data and outputting stored data as output data in response to a clock, and an operation mode selection unit that selects either a first operation mode to convert serial data to parallel data during a write operation or a second operation mode to convert parallel data to serial data during a read operation, to thereby drive the data conversion unit.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: September 29, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae-Heung Kim
  • Publication number: 20090219764
    Abstract: Semiconductor memory device for high-speed data input/output includes a first serializer configured to partially serialize input 8-bit parallel data to output first to fourth serial data, a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data and a third serializer configured to serialize the fifth and sixth serial data to output seventh serial data.
    Type: Application
    Filed: June 30, 2008
    Publication date: September 3, 2009
    Inventors: Beom-Ju Shin, Sang-Sic Yoon
  • Patent number: 7577039
    Abstract: A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect an advanced memory buffer (AMB) interface and one or more non-fully buffered memory modules.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: August 18, 2009
    Assignee: Montage Technology Group, Ltd.
    Inventors: Howard Yang, Stephen Tai, Gang Shan, Larry Wu