Abstract: A pseudo static RAM having a function which enables high-speed serial read and write operations with a relatively simple circuit configuration. In the stage subsequent to an amplifier for amplifying read signals from memory cells which are output to complementary common data lines, there are provided a first flip-flop for transmitting the output signal from the amplifier to an output buffer in an ordinary read operation, a second flip-flop connected between the amplifier and the first flip-flop in a serial read operation so as to transmit the output signal from the amplifier to the output buffer in cooperation with the first flip-flop, and an address counter for successively selecting a plurality of data lines.

Abstract: A dual port memory controller is operative to interface a pair of processors to a common multiple bank organized memory. A dedicated logic array provides arbitration between conflicting processor requests for memory access. Refresh means are operative upon the memory banks in a staggered fashion to minimize noise created within the system during refresh and to permit simultaneous refresh of an access to the memory.

Abstract: A serial-to-parallel converter has a number of memory cells connected in series for successively shifting input data in synchronism with a shift clock. The content of each memory cell is transferred by a latch circuit. The memory cells are provided with input terminals so that they can be set to "1" or "0" simultaneously before the entry of input data. This resetting, or presetting, reduces the number of reversals of the output polarity of the memory cells and hence the power consumed by the circuit can be diminished.

Abstract: A semiconductor memory device including a RAM portion and a shift register for enabling parallel transfer of a one word line amount of data of the RAM portion between the RAM portion and the shift register. The shift register is divided into a plurality of shift register portions with serial input data being distributed alternately between the shift register portions by the operation of a multiplexer and serial output data being obtained by picking up data alternately from the shift register portions by the operation of another multiplexer. A transfer gate portion is inserted between the RAM portion and the shift register for carrying out parallel transfer, the transfer gate portion includes a plurality of groups of transfer gates for enabling selective connections of input and output terminals of each of the stages of the shift register portions with either of the adjacent odd numbered bit line and even numbered bit line of the RAM portion.

Abstract: A dual-port type semiconductor memory device having a serial data input and output circuit (200) provided outside of a memory cell array (1) and operable for high-speed serial data input and output of data in addition to random data access. The semiconductor memory device includes a single decoding circuit (5) triggering at least one gate for transferring data to be stored into or read from the memory cell array in a random data access mode and setting a single bit into a corresponding shift register (24) in the serial data input and output circuit in a serial data input and output operation mode. Preferably, the decoding circuit is operated only during a time for operatively connecting bit lines and latch circuits in the serial data input and output circuit in the serial data input and output operation mode.

Abstract: In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, column address to the RAM unit is also used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the shift register containing only the data bits of interest.

Abstract: A charge coupled device (CCD) analog shift register in a two-channel serial-parallel-serial (SPS) structure operating in a fast-in/slow-out (FISO) mode for high speed signal acquisition and temporary storage of a plurality of samples. The two CCD arrays are clocked simultaneously, and the input analog signal is demultiplexed to the two arrays. Additional transfer electrodes are provided at the input of one of the arrays, and the other array is provided with a sampling clock which is 180.degree. out of phase with the sampling clock of the first array; two consecutive samples of the input signal are taken during each transfer clock cycle. All signal samples are clocked through the arrays simultaneously and appear at the output at the same time.

Abstract: In a video computer system and the like having a bit-mapped RAM component including a shift register, an improved method is provided for rapidly clearing the RAM in order to prepare the system to receive new input data. More particularly, a preselected number of predetermined data bits corresponding to the number of columns in the RAM is serially shifted into the register. Thereafter, the contents of the shift register are progressively shifted into each of the rows in the RAM until all rows are filled.

Abstract: A dual ported buffer memory for a hierarchical memory, cmprising an addressable memory array for multi-bit words and a multi-bit register. Data is transferred a word at a time between the memory array and a multi-bit bus to a higher level in the memory system and between the memory array and the register. Data is transferred a bit at a time between the register and a single serial line. Concurrent operations are possible for transfers between the memory array and the parallel bus and between the register and the serial line.

Abstract: An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.

Abstract: In a monolithic storage device having bit lines to which a plurality of memory cells are connected, and I/O lines which connect an external data input/output terminal and the bit lines and which exchange data between the input/output terminal and the bit lines; the improvement wherein said bit lines are divided into a plurality of groups each having the I/O lines, and a deserializer circuit is disposed between said each I/O line and an input terminal.

Abstract: A multi-purpose register formed of various cells of a customized integrated circuit gate array chip having input gate cells, multiplexor cells, flip-flop cells and output gate cells. The flip-flop cells may be segmented into registers of different widths or may be employed as individual flip-flop cells depending upon the mode in which the register array is to be employed.

Abstract: A semiconductor memory device used, for example, for a video RAM device which stores picture data and which is used in a video display device, etc. The semiconductor memory device includes an internal address generating circuit which sequentially generates row addresses, an address switching circuit which switches between the row address output from the internal address generating circuit and an external address, and a plurality of internal shift registers each of which stores a plurality of bit data which is read out in parallel from a memory cell array in accordance with the internal row address and/or a plurality bit data which is written-in parallel to the memory cell array in accordance with the internal row address. A serial input/output control circuit for controlling the shift registers is also provided. The input/output control circuit controls each of the shift registers so that each of the shift registers effects a shift operation to serially and continuously input or output data.

Abstract: A high speed M-stack fall-through FIFO memory system is disclosed which reduces fall-through delay and which permits at least a doubling of the maximum shift rates at input and output ports. Input port data may be entered in one of M physical memory locations and output port data may be read from one of M physical memory locations.

Abstract: Dual port memory which enables consecutive access operations from an arbitrary address. The memory includes a memory array, a random access peripheral circuit for effecting random access to the array, a counter, a setting circuit for setting the counting state of the counter at an optional value, a selection circuit for consecutively selecting the array in response to the output of the counter, and a control circuit for advancing the state of the counter in response to a shift pulse.

Abstract: A semiconductor memory device including a random access memory cell array, a series/parallel data transfer circuit, transfer gate, an active pull-up circuit, and an active pull-down circuit. The transfer gate is inserted between bit lines of the random access memory cell array and the series/parallel data transfer circuit to carry out parallel transfer of data. Output data of the series/parallel data transfer circuit is simultaneously written in a group of memory cells of selected work lines by turning on the transfer gate and selection of a word line. When data of each output of steps of the series/parallel data transfer circuit is logic "1", the active pull-up circuit charges up a selected bit line of the random access memory cell array. When data of each output of steps of the series/parallel data transfer circuit is logic "0", the active pull-down circuit discharges a selected bit line of the random access memory cell array.

Abstract: In a monolithic storage device having bit lines to which a plurality of memory cells are connected, and I/O lines which connect an external data input/output terminal and the bit lines and which exchange data between the input/output terminal and the bit lines; the improvement wherein said bit lines are divided into a plurality of groups each having the I/O lines, and a deserializer circuit is disposed between said each I/O line and an input terminal.

Abstract: A series/parallel/series shift register memory system having storage positions provided on a substrate. In addition to the single parallel-connected storage registers required to achieve the nominal storage capacity, there are provided groups of first and second nominally redundant single storage registers. The first redundant registers are used as substitutes for faulty single storage registers, so that the nominal storage capacity can be maintained. The second redundant registers are used for the transport of redundant code data. Also provided is a multi-state sequencer for indicating, in each state, the information to be carried by a particular group of storage registers and for forming, on the basis of this information, an error-detecting or error correction code which is carried by the second redundant storage registers.

Abstract: A semiconductor random access memory is provided having a second asynchronous input/output port. Block transfers of data can be effected to and from the memory using the second input/output port. Memory throughput efficiency is improved permitting functions such as display refresh in a mapped memory display to be accomplished through the second input/output port. Memory bus contention on the primary port is also relieved. The main input/output port is thereby free to receive new data for a higher percentage of available transfer time since refresh data is available at the second input/output port.

Abstract: Disclosed is a solid state imaging device which comprises an imaging unit having a plurality of picture cells arranged in at least one line for producing electrical information in response to incident radiation; a read-out unit for reading out said electrical information from said imaging unit, said read-out unit including m separate read-out channels, where m is an integer no smaller than three; and an input unit for dividing the electrical information in one line of said imaging unit into m groups, parallel-to-serial converting the respective groups of electrical information and supplying the serial information to said read-out unit.

Abstract: A semiconductor memory comprising a memory array having a plurality of memory cells, such as floating gate type MOS transistors, arranged in a matrix form with column lines and row lines, and a plurality of bit outputs. The plurality of column lines are associated with each bit output. A circuit is provided which applies a program voltage to a plurality of column lines corresponding to each bit output in response to address signals or control signals. A plurality of memory cells corresponding to each bit output are programmed simultaneously by the circuit.

Abstract: A memory device is provided with first and second memories. Two groups of data are loaded into the first and second memories, through a data buffer register. The same address information is applied to the first and second memories and the information is read out from the first and second memories. The two groups of the data read out in parallel are applied to a data multiplexer which in turn converts the parallel information into the serial one.

Abstract: Generally speaking, in accordance with the invention, a semiconductor memory device comprises a static RAM cell having a serial-parallel data conversion function, formed of seven transistors. The RAM can read/write and includes bit lines exclusively for reading and bit lines which are exclusively for writing the data. Data is read through the bit lines for exclusive reading by means of a single gate transistor. The semiconductor memory device provides a memory whose area is small in spite of including therein a serial-parallel conversion function. Further, access to the memory cell is freely available from the system side.

Abstract: A bidirectional serially controlled programmable read-only memory has a serial input/output (I/O) port and a parallel I/O port. By selecting the appropriate control inputs, the instant invention can receive serial address or data information and output data to either the parallel or serial I/O ports. In a like manner, an address at the parallel I/O port can be utilized to generate output data in either a serial or parallel form. In general, the parallel I/O port will be utilized to transfer data to and from a microprocessor, whereas the serial I/O port will be utilized to transfer data to and from an external interface. By proper utilization of the control circuits and appropriate use of the control signals, data may be read from the bidirectional PROM in parallel form from the parallel I/O port or in serial form from the serial I/O port. In addition, data may be transferred from the serial I/O port to the parallel I/O port or from the parallel I/O port to the serial I/O port.

Abstract: A sense amplifier for use with a charge coupled device in which capacitive coupled charge is employed with a flip-flop circuit to accelerate sense and readout. Operation of the amplifier is effected with two external clocks and two internally generated clocks.

Abstract: An SPS CCD memory system is provided wherein a single tap, preferably a storage node, on an input serial or shift register is connected to the input of a plurality of parallel shift registers through a fan out circuit and the output of the plurality of parallel shift registers is connected to a single tap, preferably a storage node, on an output serial or shift register through a fan in circuit.

Abstract: Disclosed is an electronic data storage of the type wherein data is entered and read out serially. In a conventional serial-parallel-serial configuration, data is serially entered into an input register and then transferred and stored in parallel through the main section of the storage until data is transferred in parallel to the output register from which the data is read serially. In a conventional line-addressable configuration, data is entered into and read from columns of shift registers where each column is addressable. The disclosed array combines the conventional serial-parallel-serial and the line-addressable structures into one array. This permits serial data to be read one row at a time as well as one column at a time.

Abstract: A bidirectional serial-parallel-serial charge-coupled device wherein each serial section is both an input register and an output register, and serial streams of charge packets flow simultaneously in opposite directions in the parallel section. Odd data bits of a serial input stream flow into a first serial register and then through the parallel section in one direction and then out of the second serial register, while concurrently the even data bits flow into the second serial register and then through the parallel section in the opposite direction and then out of the first serial register. The data transfer rate is thereby substantially doubled.

Abstract: A CCD memory is comprised of an array of serial-parallel-serial memory blocks. Each block is comprised of an N-stage serial-parallel register, an M-stage stack, and an N-stage parallel-serial register. The serial-parallel register has N outputs which couple in parallel to N inputs of the stack. The parallel-serial register has N inputs which couple in parallel to N outputs of the stack. Both registers have a zig-zag shaped charge transfer path which reduces their linear dimension, and also reduces the width of the stack.

Abstract: Memory system having contiguous storage locations with sequential addresses is partitioned into units to permit separate unit write-in and parallel unit read-out, operations. Each unit is responsive to common word address signals and unique combinations of block address signals. In response to a control signal in a first of two possible states, the memory system operates in a conventional manner, i.e., data is read from or written to a particular location in the memory to or from a data bus, the address of the particular location being supplied over an address bus and having a block select portion and a word select portion. When the control signal is in its second state, each unit is responsive only to the word address signals to read data from or write data to common word locations in each unit simultaneously.

Abstract: A memory system for analogue data includes a plurality of semiconductor charge device shift registers integrated on a semiconducor substrate. In one embodiment analogue data is serially inputed into a charge-coupled device (CCD) shift register. The serial data is converted to parallel and propagates at a substantially slower speed through a plurality of shift registers. A parallel-to-serial conversion provides a serial readout of the data. The serial-parallel-serial arrangement of the memory significantly reduces the number of transfers required to propagate one bit of data through the memory and provides correspondingly improved outputs. In a different aspect of the invention, a plurality of bits of digital data are transformed into a single analogue signal effecting a reduction in size of the memory for equal storage capability.