Abstract: A FIFO memory device includes a storage device and an address translator. The storage device contains a plurality of FIFO storage units cells connected in parallel, wherein data is input to and output from each of the FIFO storage unit cells one word at a time, and data is input to the storage device one word at a time and output from the storage device in units of a plurality of words. The address translator is disposed between a central processing unit and an input side of the storage device for translating an address specified by the central processing unit into an address specifying one of the storage unit cells of the storage device. The address translator includes a count enable signal output element responsive to addressing from the central processing unit for outputting a count enable signal, a counter responsive to the count enable signal from the count enable signal output element for counting up, and a selector responsive to a count value of the counter for selecting one of the storage unit cells.

Abstract: A FIFO memory device includes a storage device and an address translator. The storage device contains a plurality of FIFO storage unit cells connected in parallel, wherein data is input to and output from each of the FIFO storage unit cells one word at a time, and data is input to the storage device one word at a time and output from the storage device in units of a plurality of words. The address translator is disposed between a central processing unit and an input side of the storage device for translating an address specified by the central processing unit into an address specifying one of the storage unit cells of the storage device. The address translator includes a count enable signal output element responsive to addressing from the central processing unit for outputting a count enable signal, a counter responsive to the count enable signal from the count enable signal output element for counting up, and a selector responsive to a count value of the counter for selecting one of the storage unit cells.

Abstract: A serial/parallel converter has a function of forwarding data of remainder bits of p in number (e.g., 3) less than the serial/parallel number, which are positioned at the end of serial data, from the head from latches to p parallel output terminals via selectors. Accordingly, parallel data in which the data of remainder bit number are arranged correctly can be serially developed even though a simple delay amount is an arbitrary bit width. Thus, contemplated is a line memory of simple delay type which can set the simple delay amount to an arbitrary bit width, while performing serial/parallel conversion.

Abstract: A semiconductor memory device having a memory cell array (MCA) composed of a plurality of memory cells arranged in a matrix pattern including a plurality of columns, a data register section provided with two first and second registers each having "a"-units of one-bit data register; a control section for selecting two sets of "a"-units of the column from a plurality of the columns for each "a"-cycles in accordance with inputted and read addresses, and for storing the "a"-units of data of the selected 2 "a"-units of column in either one of the first and second registers alternately on the basis of a sequence of the read addresses; and a data output section for scanning and outputting data of the 2 "a"-units of the one-bit data register in sequence. Data of column bits more than the number of the registers can be accessed continuously in spite of the minimum register configuration. Further, the head column address can be selected freely.

Abstract: A plurality of delay time data can easily be obtained. A data input unit 32 successively writes data into a memory 30. A data output unit 36 outputs data from six areas a-f in the memory 30 in the parallel manner. Selection units SW1 and SW2 successively select and output data read out from the six areas a-f in the memory 30. Locations to be read are shifted from one another by the selection units SW1 and SW2 to output data from different memory locations. Thus, a plurality of data which are different in time between write and readout operations (i.e., different delay times) can be obtained simultaneously.

Abstract: In a first-in-first out memory, at least one data item is stored, and a write counter is incremented in response to the storing of each data item as it is stored into the memory. A full condition counter is also incremented in response to the writing of each data item. The at least one data item is also read from the memory, and a read counter is incremented in response to the reading of each data item from the memory. An empty condition counter is also incremented in response to the reading of each data item from the memory. In order to assure that the empty and full flag signals are not generated simultaneously, the full flag signal is generated in response to a count within the full condition counter that leads a count within the empty condition counter by a first prescribed difference. The empty flag signal is generated in response to the count within the full condition counter lagging the count within the empty condition counter by a second prescribed difference.

Abstract: An elastic memory determines an amount of delay of input data relative to other input data according to a phase difference between synchronous pulses each indicating a header of a frame of the associated input data. The elastic memory thus synchronizes both input data in the channel level. Both input data are time-division multiplied by a first multiplier. On the other hand, each counter receives synchronous pulses and thereby counting up to make a ROM produce address value of which order is determined previously according to the counted value. These address values are multiplied by a second multiplier. A decoder controls a RAM, a high-impedance control unit and a flip-flop to write in and read out of the RAM the input data. The read data are divided by a signal restoring device.

Abstract: A semiconductor memory device in which a plurality of data lines of a memory array comprising storage transistors arranged in a matrix form as those having a high or low threshold voltage according to stored data are divided into a plurality of blocks, and sense amplifiers for performing amplification operations dispersedly in time are used to amplify signals. Moreover, a first and a second group of sense amplifiers corresponding to odd- and even-numbered adjoining data lines are arranged so that while the output signals of one group of sense amplifiers are output, word lines are switched, and the other group of sense amplifiers are caused to perform the operation of amplifying the signals read from the memory cells corresponding to the word lines thus switched, respectively.

Abstract: A memory 200 is provided which includes a plurality of self-contained memory units 201 for storing data. A plurality of shift registers 211 are provided, each including a first parallel port coupled to a data port of a corresponding one of the self-contained memory units 201. Interconnection circuitry 212 is coupled to a parallel data port of each of the shift registers. Control circuitry 208, 213 is provided which is operable to control the exchange of data between a selected one of the memory units and the interconnection circuitry 212 via the shift register 211 coupled to the selected memory unit 201.

Abstract: A cascadable peripheral (10) has at least two registers (51, 52, 53) of different sizes. Input data is shifted serially through a shift register (40) synchronously with a clock signal. A serial output of the shift register (40) is provided to a data output terminal (18) of the peripheral (10) for cascading. A counter (20) increments a state in response to the clock signal. A decode portion (30, 31, 32, 33, 35) activates one of a group of load signals, corresponding to one of the registers (51, 52, 53), in response to a state of the counter (20), when an enable signal becomes inactive. The active load signal causes the corresponding register to load a value presented from a parallel data output of the shift register (40). The counter (20) is reset in response to either the enable signal becoming inactive or the counter (20) reaching a maximum count corresponding to a size of the shift register (40).

Abstract: A multiport memory having a serial input port receives serial data into a pipeline. The pipeline is emptied in response to a transfer signal at a time before the parallel transfer of data from a serial to parallel conversion register into memory. The pipeline in one embodiment includes in serial connection an input latch, a first isolation gate, a write register, a second isolation gate, an I/O bus, and means for equilibrating the I/O bus. The pipeline is controlled by write control logic so that the pipeline is emptied while equilibration of digit lines is being disabled. In a video random access memory (VRAM) embodiment, a tap counter and hold register specify the next position for serial access to the serial access register. These elements are controlled by write control logic in response to a transfer signal and a serial clock signal to allow the tap counter to increment while emptying the pipeline. When the pipeline is already empty, no increment takes place.

Abstract: A shift register 10 receives serial data and outputs parallel data in synchronism with the timing of the serial data received. A shift register group 20, 21 receives bit outputs of the parallel data from the shift register 10. The number of bits of shift registers 20, 21 in the shift register group is set in a certain condition that corresponds to the bit outputs of the parallel data from the shift register 10. A plurality of coincidence circuits 107, 108 are provided, which detects agreement between a preset data starting pattern and the bit arrangement of the data in the shift register group. A selector 306 selects a set of parallel outputs from the shift register group according to the output signal from the coincidence circuits 107, 108.

Abstract: A serial data transfer device has a FIFO memory for storing plural parallel data, a status register for indicating the actual number of residual data in the FIFO memory, a set register for arbitrarily setting the number of residual data in the FIFO memory, and a comparison circuit for comparing the indication value of the status register with the value of the set register. The indication value of the status register which indicates the actual number of residual transmit data (or residual receive data) in the FIFO memory is compared with the value of the set register in which a specific number of residual transmit data (or residual receive data) in the FIFO memory is set. Only when the number of residual transmit data (or residual receive data) in the FIFO memory is decreased (or increased) to the predetermined number of data, an interrupt signal is issued to a CPU.

Abstract: A semiconductor memory device having a memory cell array (MCA) composed of a plurality of memory cells arranged in a matrix pattern including a plurality of columns, a data register section provided with two first and second registers each having "a"-units of one-bit data register; a control section for selecting two sets of "a"-units of the column from a plurality of the columns for each "a"-cycles in accordance with inputted and read addresses, and for storing the "a" units of data of the selected 2 "a"-units of column in either one of the first and second registers alternately on the basis of a sequence of the read addresses; and a data output section for scanning and outputting data of the 2 "a"-units of the one-bit data register in sequence. Data of column bits more than the number of the registers can be accessed continuously in spite of the minimum register configuration. Further, the head column address can be selected freely.

Abstract: Programmable non-volatile analog voltage source devices and methods wherein analog voltages may be sampled and stored in a non-volatile manner for output, typically through parallel output buffers. In one form and in a single integrated circuit, an input provided to the circuit may be stored at any analog storage location as determined by an address also provided to the circuit, the storage location determining at which of the outputs of the circuit the stored value will appear. While the storage, achieved by way of storage of differential voltages in floating gate MOSFET devices, is non-volatile, the same is also electrically alterable as desired. Various alternate embodiments and methods including the ability to address multiple pages of analog storage locations for storage of analog signals and selective parallel output of each page of the storage, output enable capabilities, parallel inputs and digital inputs are disclosed.

Abstract: An improved video RAM having two data registers for holding data of each row in a memory cell array 1. A transfer gate circuit transfers alternately data of each row of the memory cell array 1 to the two data registers. On the other hand, since a switching circuit selects data held in the two data registers alternately and provide the same serially. In addition, length of data to be provided can be controlled externally. When a special high speed data reading such as oblique reading is required, timing control of externally applied control signals can be simplified.

Abstract: The present invention provides a memory device for preventing data circulating on a plural number of linear CCD array from being corrupted, for accessing data at a high speed, and for reducing the device's electric power consumption.A memory device according to this invention downsizes a block of a memory cell by circulating data on a plural number of linear CCD arrays which are for storing data by an electric charge on a cell and keeping analog data, which sets a clock generation means for circulating data on all arrays and another clock generation means for circulating at a high speed only the array loops having necessary data.

Abstract: A high speed memory interface, contained within a video teleconferencing system, couples a capture first-in first-out (FIFO) device, a host FIFO, a PB FIFO, and a display FIFO to a high speed memory. The interface includes a high speed channel interface, including an arbiter, that allocates bandwidth for the high speed memory for a display service, a capture service, a host service and a refresh service. The capture FIFO receives raw capture video data, buffers the raw capture video data at a capture rate, and transfers the raw capture video data to the high speed memory. The host FIFO receives display video data from a remote source, buffers the display video data, and transfers the input display video data to the high speed memory. The PB FIFO reads capture video data and display video data, during the PB service, from the high speed memory to provide an input queue for video compression and video decompression.

Abstract: A multiport memory having a plurality of serial output ports includes a semiconductor memory for storing data in a plurality of memory elements arrayed in rows and columns and coupled by respective row and column connecting lines. A first register stores data read in parallel from the semiconductor memory via the connecting lines of one of the rows and columns of the arrayed memory elements and serves to supply the data stored therein in serial form to a first one of the serial output ports. The first register is also operative to supply the data stored therein in parallel to a second register for storage therein. The second register is operative to supply the data stored therein to a second one of the serial output ports.

Abstract: Disclosed is a flash EEPROM including a voltage lowering circuit therein for lowering an externally applied high voltage serving as a source of an erase pulse to a predetermined voltage in a range in which a tunnel phenomenon sufficiently occurs in memory cells. The voltage lowered by the voltage lowering circuit is converted into a pulse of a small width, and the converted pulse is then applied as an erase pulse to the memory cells. A flash EEPROM including a memory cell array divided into first and second blocks is also disclosed. An erase pulse applying circuit for applying the voltage lowered by the voltage lowering circuit as an erase pulse to the memory cells, and an erase verify circuit for erase verifying are provided for each of the first and second blocks. The erase pulse applying circuit and the erase verify circuit corresponding to the first block and the ones corresponding to the second block are configured to operate independently.

Abstract: A first in, first out memory (FIFO) includes a multi-port memory array, which is accessed for read/write operations by activating a selected read or write word line. The read word line is controlled by a read shift register, and the write word line is controlled by a write shift register. In order to generate "full" and "empty" flags, the voltage state of read and write word lines are determined in "match circuits", which compare the locations of the read and write pointers. This eliminates the use of counters, and allows the shift registers and word line match circuits to be an integral part of a single-block regular structure. Furthermore, it allows the FIFO to be readily expanded to multiple numbers of words and bits per word.

Abstract: A memory apparatus includes a memory cell array for storing a data, a shift register for receiving an input serial data to be stored in the memory cell array and supplying an output serial data to be read from the memory cell array, and a transfer gate for transferring a data in parallel between the shift register and the memory cell array. In the shift register, the input serial data is shifted to an output side thereof until the first bit reaches to the final step thereof. Then, the input serial data is transferred to be stored in the memory cell array by the transfer gate. Thus, when the stored data is read therefrom, no invalid bit is supplied even at the beginning time even if the shift register is longer than the input serial data.

Abstract: In an elastic store supplied with a sequence of reception data, a sequence of reception clock pulses, a sequence of reception frame pulses, a sequence of system clock pulses, and a sequence of system frame pulses comprising successive system frames each of which has a system frame phase, a first signal generating circuit alternately controls write-in operation of first and second data memory blocks in response to the reception clock pulses and the reception frame pulses. The first and the second data memory blocks thereby memorize the reception data as first and second memorized data, respectively. A second signal generating circuit alternately controls read-out operation of the first and the second data memory blocks in response to the system clock pulses and the system frame pulses. The first and the second data memory blocks thereby deliver the first and the second memorized data as first and second read-out data, respectively.

Abstract: A method for accessing a clock-synchronous semiconductor memory device including memory cells arranged in matrix. The cells are divided into at least two blocks, access to the cells in these blocks is designated from address data provided from an external device, and access to the memory cell is executed synchronously with an externally-supplied clock signal, which comprises setting the other blocks in an access preparation state or in an access operation standby state while one block is in an access operating state, setting a certain block in the access operating state via the access preparation state when the certain block is designated for the access operation by the address data and if the certain block is in the access operating state, and setting a certain block in the access operating state immediately when the certain block is designated for the access operation by the address data and if the certain block is in the access preparation state or in the access operation standby state.

Abstract: A programmable integrated circuit of the present invention can change the input system of serial/parallel input-parallel output circuit for program data from serial to parallel or vice versa in response to a control signal from control signal input. Therefore, a program can be written at a relatively low speed through the parallel output of serial input, and a program can be written at a relatively high speed by inputting data in parallel and outputting the input data in parallel. Moreover, the bit width of the aforementioned serial/parallel input-parallel output circuit can be changed in response to a control signal from control signal input, whereby bit width for data input, shift and the like can be optimized according to the quantity of programs to be written with the result of improved freedom of users and the reduced time required for writing a large quantity of programs.

Abstract: Method and apparatus for writing and reading data into/from a first-in-first-out (FIFO) memory having memory areas arranged in a matrix are disclosed in which data of a series of first words each represented by a predetermined first number of bits are stored such that the first words are sequentially stored in selected memory areas of the memory and the stored data is read out of the memory such that the stored words are read out as a series of second words each represented by a predetermined second number, different from said first number, of bits, and in the same order as that in which the words have been stored.

Abstract: To reduce the access time of a FIFO, a storage device is provided for storing pre-loaded data to be read from the memory array of the FIFO. Thus during each read operation, the pre-loaded data in the storage device is read and the next unit of data to be read during the next read operation is pre-loaded from the array into the storage device. A second storage device is provided for storing the first unit of data written into the array after the array is empty. Thus during the first read operation after the array is rendered non-empty by one or more consecutive write operations, the first unit of data stored in the second storage device is read during the first read operation. This avoids reading garbage from the first storage device which is pre-loaded during the last read operation before the FIFO is empty.

Abstract: A signal-generating circuit receives a program signal and generates an output enable signal, a control signal, and a latch signal. In response to the output enable signal, a programmable read-only memory outputs data onto a data bus. In response to the control signal, a three-state buffer outputs data from a first register to the data bus; the data can then be stored in the programmable read-only memory by input of a chip enable signal. In response to the latch signal, a second register latches data output from the programmable read-only memory onto the data bus. An equality checker compares the contents of the first and second registers and generates an equal signal indicating whether they are equal.

Abstract: A look-ahead method and apparatus for monitoring the number of bytes in a FIFO memory. The apparatus uses look-ahead techniques to determine all possible results and then selects the appropriate result from all of the possible results to update a byte count register. The selection is based on the number of bytes READ and the number of bytes WRITTEN during a FIFO memory cycle. This look-ahead method and apparatus provides a definite time advantage over known FIFO monitoring systems that perform an addition or subtraction with the READs and WRITEs at the end of each FIFO cycle, and then use the arithmetic result to update a byte count register.

Abstract: A LIFO device includes a plurality of memory circuits (1), a write address pointer (2) and a read-out address pointer (3). The write address pointer (2) selects the memory circuit (1) in which data are to be written, while the read-out address pointer (3) selects the memory circuit (1) from which data are to be read out. Each of the write address pointer (2) and the read-out address pointer (3) alternately and repeatedly performs the count-up operation for selecting the memory circuits in a predetermined sequence and the count-down operation of selecting the memory circuits in a sequence which is the reverse of the predetermined sequence. Control is also so made that the selection by the read-out address pointer (3) precedes the selection by the write address pointer (2).

Abstract: A serially accessible memory device includes a plurality of memory cell array blocks, a plurality of input buffers each separately provided for each cell array block for receiving different data in a data stream, a plurality of output buffers each separately provided for each memory cell array block, and a plurality of registers each separately provided for each memory cell array block for effectuating data transfer collectively to and from corresponding memory cell array blocks at the same time. All of the registers shift data received from corresponding input buffer to latch the data therein in response to a single clock signal in a data writing operation and also shift latched data received from corresponding array block to provide the data to corresponding output buffer in response to another single clock signal in data reading operation. Both the shifting clock signals are derived from an external clock defining the device operation rate.

Abstract: In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a serial shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, a row of data is transferred into the serial shift register. Then the column address applied to the RAM unit is used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the serial shift register containing the data bits of interest.

Abstract: A semiconductor memory includes a writing circuit for dividing data continuously supplied to a serial data input circuit into a plurality of bits, a serial data output circuit for continuously providing data read out a plurality of bits a a time by a reading circuit, a memory cell array including a column decoder and a row decoder, column and row address buffers for instructing addresses for a plurality of bits at a time to the respective column and row decoders, an address generator, and a circuit provided between the address generator and column decoder and including a read column address generator, a write column address generator and a column address control circuit for switching read and write column address generated from the read and write column address generators, wherein address identity data are simultaneously inputted and outputted through switching of internal column addresses for reading and writing.

Abstract: An integrated circuit with a serial data port includes a counter for counting clock pulses and generating a binary signal, a decoder for converting the binary signal to a load signal to access an appropriately sized register, a serial-in, parallel-out shift register for receiving serial data and outputting the data in parallel, and a plurality of registers. The registers receive the load signal from the decoder and have a multi-bit data input for receiving the parallel data from the shift register. The circuit can access an appropriately sized register by using the counter and the decoder instead of address bits, and therefore reduce the total bit stream length. The circuit can randomly select any register out of several registers having different bit lengths.

Abstract: A data stream smoothing circuit wherein a FIFO memory receives data from the DRAM, and a memory status circuit provides a memory-full status signal when the FIFO memory contains a selected amount of data from the DRAM. A refresh timer generates a refresh request signal whenever DRAM refresh should be performed. When the refresh request signal is generated, a refresh control circuit refreshes a row of data in the DRAM upon occurrence of the next memory-full status signal.

Abstract: A serializer/deserializer for a flow of n-bits of data shifted according to the rate of a clock includes an n-rows and n-columns matrix of 1-bit registers (00-77). Each 1-bit register is connected through its input to a first switch connected to the output of the register in the same row and lower rank column and to a second switch connected to the output of the register in the same column and upper rank row. Input terminals (E0-E7) are connected to the registers of the lower rank column and of the upper rank row. Output terminals (S0-S7) are connected to the registers of the upper rank column and of the lower rank row. The matrix cells are arranged according to a triangle, the cells being arranged one with respect to the other according to the structural corresponding to folding a square matrix along its diagonal.

Abstract: A semiconductor file memory has a semiconductor memory connected to an information processor and operated to store data transferred from the information processor and read out stored data, the file memory comprising a serial/parallel conversion circuit which receives, in a serial manner, data to be stored in the semiconductor memory and converts the data line parallel data, a parallel/serial conversion circuit which receives data read out of the semiconductor memory and converts the data into serial data, and an address data holding circuit which holds address data transferred from the information processor, the serial data transferred from the information processor being converted into parallel data by the serial/parallel conversion circuit and the converted data stored in the semiconductor memory in accordance with addresse data held in the address data holding circuit, and parallel data stored in the semiconductor memory is read out in accordance with address data held in the address data holding circuit,

Abstract: Data selector circuit including a plurality of data registers connected in parallel via corresponding output buffers to a plurality of output drivers, wherein a decoder and selector portion is interposed between the output buffers and the output drivers for selectively providing one of a plurality of serial data output sequences from the data registers to the output drivers rather than a parallel data output format from the plurality of data registers which would otherwise occur. The decoder and selector portion is controlled by a partial address buffer which is provided with serial sequence selection data.

Abstract: A semiconductor memory includes an input buffer means for storing inputted data, an output buffer means for storing the data and for outputting the data and a storage means for storing the data outputted from the input buffer means and for transferring the data to the output buffer means. The input buffer means includes a plurality of memories having equal capacity. The output buffer means also includes a plurality of memories having equal capacity. The memory means have memory capacity of a divisor of memory capacity per line of the storage means. In addition, the semiconductor memory can also include a dividing means for dividing image data outputted from said input buffer into smaller data units to be written on said storage means and a recombining means for said smaller data units outputted from said storage means to supply to said output buffer means.

Abstract: An integrated memory circuit in which memory cells are arranged in rows and columns, each column having a separate sense amplifier. The memory columns can be coupled to neighboring memory columns by additional transistors and the gain of the sense amplifiers in the even and the odd columns is adjustable. Consequently, information can also be serially shifted from one column to another, so that the information can be written and read not only in parallel but also serially.

Abstract: A memory cell and array of memory cells specially adapted for support of bit serial math for low cost CAD workstations. The memory cell is comprised of a multiplexer which selects between several inputs for application of data to a bit storage cell of a dynamic RAM nature. Each cell multiplexer has a serial data input, a parallel data input, a parallel format pipeline data input and a recirculation data input. Each cell also has a first output which serves both as a serial data output and a pipeline data output, and a second data output which is tri-state and which is coupled to a parallel format data bus which runs through the array. A plurality of such cells are arranged in rows and columns where rows of such cells are coupled so that data may passed between the rows in either parallel format or serial format for pipeline operations and such each row can independently load data in either serial or parallel format and output data in either parallel or serial format.

Abstract: A two phase shift register comprises four serial registers each having an input section, a transfer section, and a lead-in section disposed between the input section and the transfer section. The input sections provide respective sequences of charge samples, the four sequences being offset in phase relative to each other by 90.degree. within the cycle of a clock signal. At least one of the serial registers comprises a first lead-in gate pair and a second lead-in gate pair over the lead-in section, the second lead-in gate pair being between the first lead-in gate pair and the transfer section. The first lead-in gate pair and the second lead-in gate pair are each driven at the frequency of the clock signal, the drive signal applied to the second lead-in gate pair being retarded in phase relative to that applied to the first lead-in gate pair by 90.degree. within the cycle of the clock signal.

Abstract: A line memory for speed conversion, whose data rates of write into and read from a memory cell (1) differ from each other, has a write circuit (2, 3, 4) for writing input data (D.sub.in) into the cell (1) at a predetermined rate and resetting the write address of the cell (1) at a predetermined period, a read circuit (5, 6, 7) for reading data (D.sub.out) from cell (1) at a rate different from the write rate and resetting the read address of the cell (1) at the predetermined period, the first shift circuit (8) for shifting reset timing of the write address, and the second shift circuit (9) for shifting reset timing of the read address, the first and second shift circuits enabling respective setting quantities at the same value. This memory can shift both the write address reset timing and the read address reset timing while keeping both in the same condition.

Abstract: A microcomputer is disclosed having a LIFO memory employed as a stack, and a shift register employed as a stack pointer for controlling access to the stack. There is no need to decode the contents of a stack pointer. Thus, high speed of operation is possible.

Abstract: A FIFO memory is provided with individual arrays of dynamic memory cells and includes a dedicated write line buffer memory and a dedicated read line buffer memory operably connected thereto. First and second line buffer memories are also provided in conjunction with the write line buffer memory and the read line buffer memory so as to permit a faster response to the input and output of data with respect to the FIFO memory. Data may be alternately written into either one of the line buffer memories as a lead-in to the subsequent writing of data in the dynamic memory arrays via the write line buffer memory. Data read out from the other line buffer memory may occur simultaneously. The FIFO memory may serve as a video data frame memory for storing a frame of a video screen image.

Abstract: A dual port memory which enables consecutive access operations from an arbitrary column address and is fabricated on a reduced area of a semiconductor chip. The memory includes a memory array, a random access peripheral circuit for effecting random access to the array and having a column decoder, and a serial access peripheral circuit having a shift register for serially selecting the columns of the array and a control circuit for determining the state of the shift register in accordance with the output of the column register.

Abstract: A digital computer can write a block of data to a RAM, or read a block therefrom, via a serial/parallel converter which is word serial, bit parallel on the computer side and bit serial on the RAM side. The RAM is addressed by a free-running address counter clocked by clock pulses WCK. A fault masking circuit enables faulty cells in the RAM to be masked out. Data specific to the RAM causes the clock pulses WCK to be selectively gated for providing bit rate clock pulses GCK to the converter. These pulses are divided down to produce pulses BCK at word rate. The invention is particularly useful in a wafer scale integrated circuit comprising a large number of RAMs served by a single fault masking circuit with tabulated data defining the memory cells to be masked out on a memory by memory basis.

Abstract: A gated shift register includes a first set of 16 storage devices and a second set of 16 storage devices with interconnection circuitry for configuring the first set of 16 storage devices as a 16 bit shift register. The second set of storage devices is coupled between the outputs of the first set of storage devices and 16 output terminals of the gated shift register and transfers the outputs from the first storage devices to the output terminals when a transfer input terminal is at a first logic state, and isolates the first storage devices from the output terminals and retains the data at the output terminals when the transfer input signal switches to a second logic state. The gated shift register also includes power monitor and control circuitry for supplying standby battery voltage to the circuit when the primary power source becomes unavailable.

Abstract: A dual-port memory includes a memory array comprising a plurality of memory elements one of which is accessed at random by a row and column address input so as to enable writing in or reading out of data; at least two serial access memories capable of receiving parallel input of all or a portion of the data of a selected row or column of said memory array; and a switching circuit for switching the respective serial access memories to be in operational states of receiving parallel inputs independently or to be in operational states of outputting their serial outputs successively.

Abstract: A semiconductor memory for serially reading data of memory cells connected to the selected one word line based on the clock signal which defines a picture element and for writing the write data serially input to the latch circuit based on such clock signal to the memory cells, during the horizontal blanking time of a CRT monitor.