Including Particular Address Buffer Or Latch Circuit Arrangement Patents (Class 365/230.08)
  • Patent number: 10419574
    Abstract: A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Matthew D. Rowley, Mark Bauer
  • Patent number: 10318726
    Abstract: A method includes: reading a plurality of words from a one-time program (OTP) memory of a processing chip, wherein each of the words includes secure data for the chip and bits corresponding to a check pattern; comparing the bits corresponding to the check pattern to a preprogrammed check pattern; detecting an error based on comparing the bits corresponding to the check pattern to the preprogrammed check pattern; and performing an action by the processing chip in response to detecting the error.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: June 11, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Anil Kota, Sei Seung Yoon, Bhadri Kubendran
  • Patent number: 10147477
    Abstract: One controller for controlling operation of a memory device includes an output circuit configured to supply a chip select signal, an address signal, a command signal, and a clock signal to the memory device, and a data processing circuit configured to process read data and write data through a data terminal based on the chip select signal, the address signal, the command signal, and the clock signal supplied by the output circuit. The controller is configured to supply the address signal and the command signal to the memory device a predetermined duration after the output circuit supplies the chip select signal.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 4, 2018
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Chikara Kondo
  • Patent number: 9977485
    Abstract: Embodiments of the disclosure include a cache array having a plurality of cache sets grouped into a plurality of subsets. The cache array also includes a read line configured to receive a read signal for the cache array and a set selection line configured to receive a set selection signal. The set selection signal indicates that the read signal corresponds to one of the plurality subsets of the cache array. The read line and the set selection line are operatively coupled to the plurality of cache sets and based on the set selection signal the subset that corresponds to the set selection signal is switched.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: May 22, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul A. Bunce, John D. Davis, Diana M. Henderson, Jigar J. Vora
  • Patent number: 9892165
    Abstract: Embodiments of the invention relate to processing queries. A query operation to be performed on a table of data is translated into a series of bit level logical operations using expansion and/or saturation operations. A mask is created from the series of bit level logical operations. This mask is then simultaneously applied to multiple rows from the table of data.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ronald J. Barber, Vijayshankar Raman
  • Patent number: 9804978
    Abstract: A memory device and memory system using the memory device. The memory system includes a memory controller having a memory bus with a plurality of lanes, and a plurality of memory devices. Each memory device has a plurality of data pins and a plurality of detection circuits, wherein each detection circuit is coupled to one of the data pins to detect whether the data pin is coupled to one of the lanes of the memory bus. Each lane of the memory bus provides a point-to-point connection between the memory controller and exactly one of the device data lanes, wherein a subset of the data lanes of each memory device are coupled to one of the lanes of the memory bus. The memory capacity of a memory system may be increased by using more of the memory devices limited only by the width of the memory bus.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: October 31, 2017
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventor: Jonathan R. Hinkle
  • Patent number: 9685207
    Abstract: A synchronous sequential latch array generated by an automated system for generating master-slave latch structures is disclosed. A master-slave latch structure includes N/2 rows of master-slave latch pairs, an N/2-to-1 multiplexer and control logic. N is equal to the number of latches that are included in the latch array.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: June 20, 2017
    Assignee: Nvidia Corporation
    Inventor: Robert A. Alfieri
  • Patent number: 9665506
    Abstract: A data processing device includes a controller. The controller includes a compression circuit configured to compare a plurality of data groups, each of which has a first burst length and is transmitted in units of an input/output width, with a predetermined pattern, and perform data compression on the data groups based on a result of comparison. The controller further includes a compression data restructuring circuit configured to generate a transmission data group by restructuring the compressed data group to have a second burst length.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 30, 2017
    Assignee: SK HYNIX INC.
    Inventors: Sang Eun Lee, Chang il Kim, Oung Sic Cho
  • Patent number: 9628055
    Abstract: An SR latch circuit with single gate delay is provided. The circuit has an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: April 18, 2017
    Assignee: INPHI CORPORATION
    Inventor: Travis William Lovitt
  • Patent number: 9628090
    Abstract: While transmission of data to be transmitted and gap data to be transmitted by the same transmission path as that data is controlled so that a frequency of a data signal may become equal to or more than a certain frequency, a data output driver selects and outputs the data or the gap data as the data signal, a valid signal generation circuit outputs a valid signal that indicates whether or not the data is effective, and a reception circuit that is formed in a different die receives the data signal and the valid signal transmitted via the transmission path that includes a through silicon via and acquires the data from the data signal based on the valid signal.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: April 18, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Koichi Yoshimi
  • Patent number: 9594566
    Abstract: Technical solutions are described for dynamically managing an operand-store-compare (OSC) prediction table for load and store operations executed out-of-order. One general aspect includes a method that includes receiving a request to retire a queue entry corresponding to an instruction. The method also includes identifying an OSC prediction for the instruction based on an OSC prediction table entry, where the OSC prediction indicates if the instruction is predicted to hit an OSC hazard. The method also includes determining if the instruction hit the OSC hazard. The method also includes in response to the OSC prediction indicating that the instruction is predicted to hit the OSC hazard and the instruction not hitting the OSC hazard, invalidating the OSC prediction table entry corresponding to the instruction. The present document further describes examples of other aspects such as methods, computer products.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Khary J. Alexander, Jane H. Bartik, Jatin Bhartia, James J. Bonanno, Adam B. Collura, Jang-Soo Lee, James R. Mitchell, Anthony Saporito
  • Patent number: 9588840
    Abstract: A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoi-ju Chung, Chul-sung Park, Tae-young Oh, Jang-woo Ryu, Chan-yong Lee, Tae-seong Jang, Gong-heum Han
  • Patent number: 9552889
    Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: January 24, 2017
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Peter B. Gillingham, Graham Allan
  • Patent number: 9424953
    Abstract: A data transfer unit includes a page buffer to latch data of a normal bit line connected to a normal memory cell, a second page buffer to latch data of a parity bit line connected to a parity memory cell, and a third page buffer that is first replaced when the first page buffer is defective or when the second page buffer is defective. ECC Bus_1 is connected to the first, second, and third page buffers, respectively, and Data Bus_1 is connected to the first and third page buffers.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: August 23, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Makoto Hirano
  • Patent number: 9384808
    Abstract: An address input circuit of a semiconductor device includes: an address latch unit configured to generate latch addresses, by latching addresses sequentially provided by an external, according to a command decoding signal, wherein latch timings of each of the addresses are adjusted differently from one another; and a command decoder configured to decode a command provided from the external and generate the command decoding signal.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: July 5, 2016
    Assignee: SK hynix Inc.
    Inventors: Young Ju Kim, Kwan Weon Kim, Dong Uk Lee
  • Patent number: 9362923
    Abstract: A delay circuit includes units each of which includes a first delay element having a first input node and a first output node, a second delay element having a second input node and a second output node, and a third delay element between the first and second delay elements. The first output node of a first unit of the units is connected to the first input node of a second unit of the units. The second input node of the first unit is connected to the second output node of the second unit. A signal on the first input node of the first delay element of the first unit is output from the second output node of the second delay element of the first unit through the third delay element of the second unit.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: June 7, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Mizogami, Masayuki Koizumi
  • Patent number: 9362007
    Abstract: A data transfer unit includes a first page buffer to latch data of a normal bit line connected to a normal memory cell, a second page buffer to latch data of a parity bit line connected to a parity memory cell, and a third page buffer to be first replaced when the first page buffer is defective or when the second page buffer 102c is defective. An error code correction bus is connected to the first and second page buffers, and a data bus is connected to the first, second and third page buffers.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: June 7, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Makoto Hirano
  • Patent number: 9323614
    Abstract: A memory structure is provided that controls the activation of error handling bits as a function of operating voltage. In this way, error correction can be used to offset errors when the memory structure is run at low voltage (and frequency). However, negative performance impacts for such error correction, such as additional access latencies, can be avoided when the memory structure is run at higher voltage (and frequency) and memory errors are less likely. In addition, increased latencies due to evaluating error handling bits may be hidden by reading digital data bits from the memory structures speculatively and assuming no errors. Also, certain portions of memory structures may have larger cells, and therefore larger areas, than other portions, which may provide not only higher reliability at low operating voltages, but also faster operation with reduced latency.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: April 26, 2016
    Assignee: Wisconsin Alumni Research Foundation
    Inventor: Nam Sung Kim
  • Patent number: 9183091
    Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Ning Wu, Robert E. Frickey, Hanmant P. Belgal, Xin Guo
  • Patent number: 9171645
    Abstract: Integrated circuits with memory built-in self-test (BIST) logic and methods of testing using the same are disclosed. The method includes setting an address window for locating defects in a memory array. The method further includes comparing output data of the memory array to expected data to determine that a defect exists at location “M” in the memory array within the address window. The method further includes storing, in registers, the address M and a resultant bit fail vector associated with the location “M” of the defect found in the memory array. The method further includes resetting the registers to a null value and resetting the address window with a new minimum and maximum address pair, to compare the output data of the memory array to the expected data within the reset address window which excludes address M.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Geovanny Rodriguez, Brian J. Vincent, Timothy J. Vonreyn
  • Patent number: 9054578
    Abstract: A hybrid output driver includes a voltage mode main driver and a current mode emphasis driver that provides an adjustable differential output voltage swing. The current mode emphasis driver provides: push-pull swing control currents in response to a cursor data value, push-pull precursor currents in response to a precursor data value, and push-pull postcursor currents in response to a postcursor data value. In a normal operating mode, the swing control currents oppose voltages imposed by the voltage mode main driver on the differential output terminals. In a turbo operating mode, the swing control currents enhance voltages imposed by the voltage mode main driver on the differential output terminals.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: June 9, 2015
    Assignee: MoSys, Inc.
    Inventor: Kuo-Chiang Hsieh
  • Patent number: 9042198
    Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: May 26, 2015
    Inventors: Yutaka Shirai, Naoki Shimizu, Kenji Tsuchida, Yoji Watanabe, Ji Hyae Bae, Yong Ho Kim
  • Patent number: 9036446
    Abstract: A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: May 19, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Esin Terzioglu, Changho Jung, Shahzad Nazar, Balachander Ganesan, Alex Dongkyu Park
  • Patent number: 9030888
    Abstract: A device that includes first and second buffer circuits electrically connected to a terminal and an output control circuit activating the first buffer circuit and deactivating the second buffer circuit in a first state and activating one of the first and second buffer circuits and deactivating the other of the first and second buffer circuits based on input data in a second state. The output control circuit is brought into one of the first and second states.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 12, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Chiaki Dono, Shinya Miyazaki
  • Patent number: 9030898
    Abstract: An embodiment of the present invention provides a semiconductor, including a non-volatile storage unit suitable for storing one or more first addresses; an address storage unit suitable for storing the first addresses sequentially received from the non-volatile storage unit as second addresses while deleting previously stored second addresses identical to an input address of the first addresses, in a reset operation; and a cell array suitable for replacing one or more normal cells with one or more redundancy cells based on the second addresses in an access operation.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: May 12, 2015
    Assignee: SK Hynix Inc.
    Inventor: Choung-Ki Song
  • Patent number: 9019780
    Abstract: A non-volatile memory apparatus and a data verification method thereof are provided. The non-volatile memory apparatus includes a plurality of memory cells, a page buffer, a write circuit, a sense amplifier, and a sense and compare circuit. The page buffer stores a plurality of buffered data and programs the plurality of memory cells according to the plurality of buffered data. The write circuit receives a program data or a rewrite-in data and writes the program data or the rewrite-in data to the page buffer. The sense amplifier senses data read from the memory cells for generating a read-out data. The sense and compare circuit reads the buffered data, and compares the read-out data and a compared buffered data to generate a rewrite-in data. The sense and compare circuit determines the rewrite-in data to be the buffered data or an inhibiting data according to the compared result.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 28, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Yih-Lang Lin, Chen-Hao Po
  • Patent number: 9013921
    Abstract: A semiconductor memory device includes a first data bus having a first width, and a second data bus which is separate from the first data bus and which has a second width which is different from the first width. The semiconductor memory device further includes a data transfer unit configured for transferring data from memory cells connected to a plurality of bit lines. In a first operational mode, the data transfer unit connects a first number of bit lines from among the plurality of bit lines to the first data bus to transfer the data, the first number being equal to the first width. In a second operational mode, the data transfer unit connects a second number of bit lines from among the plurality of bit lines to the second data bus to transfer the data, the second number being equal to the second width.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tomohisa Miyamoto, Makoto Hirano
  • Publication number: 20150103479
    Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 16, 2015
    Inventors: Frederick A. Ware, Suresh Rajan
  • Patent number: 9007852
    Abstract: A semiconductor integrated circuit includes: a latch unit configured to latch data in response to an input control signal; and a latch control unit configured to determine whether or not any one of first and second memory areas is successively accessed, and adjust timing of the input control signal.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jae Il Kim
  • Publication number: 20150098295
    Abstract: Apparatus and methods are disclosed herein, including those that operate to initialize registers of a first memory device and a second memory device of a single-rank memory module by providing separate chip select signals to separately select a first memory device and a second memory device. A method may further include, subsequent to sensing that the initializing is completed, for example, providing a single chip select signal to simultaneously select the first memory device and the second memory device.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 9, 2015
    Applicant: Micron Technology, Inc.
    Inventor: William A. Lendvay
  • Patent number: 9003255
    Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics International N.V.
    Inventor: Nishu Kohli
  • Patent number: 8982661
    Abstract: A shared-signaling multi-device memory system is capable of changing between addressing modes without the multi-device memory being required to undergo a power cycle. First and second registers of a memory device are set to both contain first address-identification information in response a first address-assignment command that is received a power cycle. The first register is set to contain second address-identification information in response a second address-assignment command that is received subsequently to the first address assignment command. Depending on the value of the second address-identification information, the memory device is configured in an individual-device-addressing mode or a parallel addressing mode without a power cycle. The first register can be reset to the first address-identification information contained in the second register in response to an address-restore command without a power cycle. A corresponding method is also disclosed.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Julie M. Walker, Doyle Rivers
  • Patent number: 8982608
    Abstract: A semiconductor device having a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell, so that the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: March 17, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 8976618
    Abstract: Decoded 2n-bit bitcells in memory for storing decoded bits, and related systems and methods are disclosed. In one embodiment, a decoded 2n-bit bitcell containing 2n state nodes is provided. Each state node includes storage node to store decoded bit. Storage node provides bit to read bitline, coupled to decoded word output. Each state node includes active decoded bit input coupled to storage node that receives decoded bit from decoded word to store in storage node in response to write wordline. State node comprised of 2n?1 passive decoded bit inputs, each coupled to one of 2n?1 remaining storage nodes. 2n?1 passive decoded bit inputs receive 2n?1 decoded bits not received by active decoded bit input. State node includes logic that receives 2n?1 decoded bits. Logic retains decoded bit, provides it to passive decoded bit output. Passive decoded word output is coupled to storage node to store decoded bit in storage node.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: March 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Manish Garg, Rajesh Kumar
  • Patent number: 8971133
    Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: March 3, 2015
    Assignee: ARM Limited
    Inventors: Bo Zheng, Jungtae Kwon, Gus Yeung, Yew Keong Chong
  • Patent number: 8964484
    Abstract: A memory operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: February 24, 2015
    Assignee: Spansion LLC
    Inventors: Mee-Choo Ong, Sheau-Yang Ch'ng, Boon-Weng Teoh, Sie Wei Henry Lau, Jih Hong Beh, Wei-Kent Ong
  • Patent number: 8953410
    Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: February 10, 2015
    Assignee: SK Hynix Inc.
    Inventor: Kyong Ha Lee
  • Publication number: 20150009773
    Abstract: Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory device, the select command indicating a targeted memory volume of the plurality of memory volumes. In response to the select command, the method can include selecting the targeted memory volume of the memory volumes and putting at least a portion of a non-selected memory volume of the memory volumes in a particular state based, at least in part, on a previous state of the non-selected memory volume and/or a portion of an address associated with the select command.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 8, 2015
    Inventor: Terry M. Grunzke
  • Publication number: 20150009774
    Abstract: The semiconductor device includes an internal command generator and an internal address generator. The internal command generator generates first and second command latch signals from first and second internal clock signals in response to an external control signal and latches a command signal in response to the first and second command latch signals to generate a synthesized internal command signal. The internal address generator generates first and second address latch signals from the first and second internal clock signals in response to the external control signal and latches an address signal in response to the first and second address latch signals to generate a synthesized internal address signal.
    Type: Application
    Filed: December 16, 2013
    Publication date: January 8, 2015
    Applicant: SK hynix Inc.
    Inventor: Bok Rim KO
  • Patent number: 8929155
    Abstract: A semiconductor memory device includes memory cells for storing data, page buffers each configured to comprise a dynamic latch and a static latch on which data to be programmed in to the memory cells or data read from the memory cells are latched, and a control logic configured to store a plurality of refresh mode select codes corresponding to various refresh cycles, and refresh the dynamic latch by exchanging data between the static latch and the dynamic latch according to a refresh cycle corresponding to a selected refresh mode select code.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: January 6, 2015
    Assignee: SK Hynix Inc.
    Inventors: Byoung Sung Yoo, Chang Won Yang
  • Patent number: 8929172
    Abstract: A pipe register circuit includes an address storage section configured to temporarily and sequentially store address signals input from an external in correspondence with a read command signal input together with the address signals, and an address output control section configured to generate an address output control signal for allowing the address signals stored in the address storage section to be output in correspondence with CAS latency, and output the address output control signal to the address storage section.
    Type: Grant
    Filed: September 3, 2012
    Date of Patent: January 6, 2015
    Assignee: SK Hynix Inc.
    Inventor: Hyun Su Yoon
  • Patent number: 8923090
    Abstract: A decoder circuit to decode an address for accessing a memory cell in a memory array includes address latch circuitry, inverter circuitry, and first address pre-decode circuitry. The address latch circuitry receives an address signal and generates address holding signals during a setup period. The address latch circuitry latches the address holding signals during an address hold period following the setup period. The inverter circuitry receives the address signal and generates a complementary address signal. The first address pre-decode circuitry decodes the address signal and the address holding signals during the setup period to generate a first pre-decode address signal at an output of the first address pre-decode circuitry. In addition, the first address pre-decode circuitry decodes the address holding signals during the address hold period to maintain the first pre-decode address signal at the output of the first address pre-decode circuitry.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: December 30, 2014
    Assignee: LSI Corporation
    Inventors: Donald A. Evans, Rasoju V. Chary, Jeffrey C. Herbert, Rahul Sahu, Rajiv K. Roy
  • Patent number: 8917570
    Abstract: A memory device includes a plurality of banks, a plurality of address buffers configured to receive addresses, and a buffer control unit configured to deactivate one or more of the plurality of address buffers when the number of activated banks among the plurality of banks is a prescribed number.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 23, 2014
    Assignee: SK Hyinx Inc.
    Inventor: Choung-Ki Song
  • Patent number: 8917561
    Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: December 23, 2014
    Assignee: STMicroelectronics International N.V.
    Inventor: Vivek Asthana
  • Patent number: 8913443
    Abstract: Structures and related processes for effectively regulating power among slave chips in a 3D memory multichip package that employs TSVs for interlevel chip connections. Individual voltage regulators are employed on one or more of the slave chips for accurate level control of internal voltages, for example, word line driver voltage (VPP), back bias voltage (VBB), data line voltage (VDL), and bit line pre-charge voltage/cell plate voltage (VBLP/VPL). Employing regulators on one or more of the slave chips not only allows for precise regulation of power levels during typical memory stack operation, but also provides tolerance in small variations in power levels caused, for example, by manufacturing process variations. Moreover, less chip real estate is used as compared to techniques that provide complete power generators on each chip of a multichip stack.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: December 16, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hong Boem Pyeon
  • Publication number: 20140334242
    Abstract: A semiconductor memory apparatus includes a reset pad configured to receive and transfer an external reset signal and an external control signal; a first input buffer configured to buffer the external reset signal in response to a buffer control signal and output an internal reset signal; a second input buffer configured to buffer the external control signal in response to the buffer control signal and output an internal control signal; and an input buffer control unit configured to generate the buffer control signal in response to an external command.
    Type: Application
    Filed: July 24, 2014
    Publication date: November 13, 2014
    Inventor: Jin Hee CHO
  • Patent number: 8885433
    Abstract: A semiconductor device includes a pulse generation circuit configured to generate an enable pulse signal, which is activated in response to an active command signal and deactivated in response to a column command signal, and a plurality of fuse circuits configured to store repair addresses for a column repair and to output stored repair addresses in response to the enable pulse signal.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: November 11, 2014
    Assignee: SK Hynix Inc.
    Inventor: Kwi-Dong Kim
  • Patent number: 8879351
    Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. Each half of the memory bank is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 4, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Jin-Ki Kim
  • Patent number: 8873331
    Abstract: Command decoders are provided. The command decoder includes an input buffer configured for buffering and receiving command address signals having address information and command information at first, second, third, and fourth edges of a clock pulse signal according to a reference voltage, a latch circuit configured for latching the command address signals output from the input buffer at the first and third edges of the clock pulse signal to generate and output latched signals, a first command generator configured for decoding the latched signals output from the latch circuit at the first edge of the clock pulse signal to generate and output a first internal command, and a second command generator configured for decoding the latched signals output from the latch circuit at the third edge of the clock pulse signal to generate and output a second internal command.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Yong Deok Cho
  • Publication number: 20140313845
    Abstract: A semiconductor system including a semiconductor integrated circuit or a semiconductor chip, and a method of driving the semiconductor system are described. The semiconductor integrated circuit includes a plurality of semiconductor chips, at least one first chip through via suitable for penetrating through the plurality of semiconductor chips and interfacing a source ID code between the plurality of semiconductor chips, a plurality of second chip through vias suitable for penetrating through the plurality of semiconductor chips and interfacing a plurality of chip selection signals between the plurality of semiconductor chips, wherein the semiconductor chip uses one of chip selection signals as an internal chip selection signal in response to a chip ID code by selecting one of a unique ID code for the semiconductor chip and an alternative ID code for a preset semiconductor chip when the semiconductor chip fails.
    Type: Application
    Filed: September 5, 2013
    Publication date: October 23, 2014
    Applicant: SK hynix Inc.
    Inventor: Jae-Bum KO