Abstract: A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.

Abstract: A state detection circuit for an anti-fuse memory cell includes: amplifier, having first input terminal connected with first reference voltage, second input terminal connected with first node and output terminal connected with second node; anti-fuse memory cell array, including anti-fuse memory cell sub-arrays, bit lines of sub-arrays are connected with first node, word lines of sub-arrays are connected with controller and each sub-array includes anti-fuse memory cells; first switch element, having first terminal connected with power supply, second terminal connected with first node and control terminal connected with second node; second switch element, having first terminal connected with power supply, second terminal connected with third node and control terminal connected with second node; third switch element, having first terminal connected with third node, grounded second terminal and control terminal connected with controller; and comparator, having first and second input terminals connected with third

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: Disclosed is a latch architecture comprising an input circuit receiving input data and; a combinational network providing first intermediate data, first intermediate control signal and second intermediate control signal, based on latched input data from the input circuit; one or more first latches providing latched first intermediate data; a second latch providing a latched first intermediate control signal; a third latch providing a latched second intermediate control signal; and at least one fourth latch providing the output data; a decoder connected to the first latch and receiving the latched first intermediate data and providing second intermediate data. The at least one fourth latch receives input signals modified based on the latched first intermediate control signal, the latched second intermediate control signal and the second intermediate data. The first to third latches operate at an inverted clock signal and the at least one fourth latch operates at a non-inverted clock signal.

Abstract: A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.

Abstract: A clocked driver circuit can include a master-slave level shifter latch and a driver. The master-slave level shifter latch can be configured to receive an input signal upon a first state of a clock signal, latch the input signal upon a second state of the clock signal and generate a level shifted output signal corresponding to the latched input signal. The driver can be configured to receive the level shifted output signal from the master-slave level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.

Abstract: A semiconductor device includes a first command pulse generation circuit configured to generate a first command pulse from an internal command address based on a first blocking signal; and a second command pulse generation circuit configured to generate a second command pulse from the internal command address based on a second blocking signal.

Abstract: Provided are a graphics processor that performs warping, a rendering system including the graphics process, and a method of operating the graphics processor. The graphics processor may include an internal command generator and a graphics computing device. The internal command generator may be configured to receive timing information and generate, based on the timing information, a warping command for periodically performing warping. The graphic computing device may be configured to, in response to the warping command, periodically perform the warping, without a context switch by a host, by using sensing information provided from an external source and frame data that have already been rendered.

Abstract: An electronic device includes a memory device including first and second ranks, and a system-on-chip that exchanges data with the memory device. The system-on-chip loads a first training code to the first rank and performs a first training operation on the second rank using the first training code loaded to the first rank, and loads the first training code to the second rank and performs a second training operation on the first rank using the first training code loaded to the second rank. The system-on-chip generates a first reference voltage for sampling output data of the first rank, and generates a second reference voltage for sampling output data of the second rank. The first and second reference voltages are generated based on a first result of performing the first training operation on the second rank, and a second result of performing the second training operation on the first rank.

Abstract: A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.

Abstract: A method includes: reading a plurality of words from a one-time program (OTP) memory of a processing chip, wherein each of the words includes secure data for the chip and bits corresponding to a check pattern; comparing the bits corresponding to the check pattern to a preprogrammed check pattern; detecting an error based on comparing the bits corresponding to the check pattern to the preprogrammed check pattern; and performing an action by the processing chip in response to detecting the error.

Abstract: One controller for controlling operation of a memory device includes an output circuit configured to supply a chip select signal, an address signal, a command signal, and a clock signal to the memory device, and a data processing circuit configured to process read data and write data through a data terminal based on the chip select signal, the address signal, the command signal, and the clock signal supplied by the output circuit. The controller is configured to supply the address signal and the command signal to the memory device a predetermined duration after the output circuit supplies the chip select signal.

Abstract: Embodiments of the disclosure include a cache array having a plurality of cache sets grouped into a plurality of subsets. The cache array also includes a read line configured to receive a read signal for the cache array and a set selection line configured to receive a set selection signal. The set selection signal indicates that the read signal corresponds to one of the plurality subsets of the cache array. The read line and the set selection line are operatively coupled to the plurality of cache sets and based on the set selection signal the subset that corresponds to the set selection signal is switched.

Abstract: Embodiments of the invention relate to processing queries. A query operation to be performed on a table of data is translated into a series of bit level logical operations using expansion and/or saturation operations. A mask is created from the series of bit level logical operations. This mask is then simultaneously applied to multiple rows from the table of data.

Abstract: A memory device and memory system using the memory device. The memory system includes a memory controller having a memory bus with a plurality of lanes, and a plurality of memory devices. Each memory device has a plurality of data pins and a plurality of detection circuits, wherein each detection circuit is coupled to one of the data pins to detect whether the data pin is coupled to one of the lanes of the memory bus. Each lane of the memory bus provides a point-to-point connection between the memory controller and exactly one of the device data lanes, wherein a subset of the data lanes of each memory device are coupled to one of the lanes of the memory bus. The memory capacity of a memory system may be increased by using more of the memory devices limited only by the width of the memory bus.

Abstract: A synchronous sequential latch array generated by an automated system for generating master-slave latch structures is disclosed. A master-slave latch structure includes N/2 rows of master-slave latch pairs, an N/2-to-1 multiplexer and control logic. N is equal to the number of latches that are included in the latch array.

Abstract: A data processing device includes a controller. The controller includes a compression circuit configured to compare a plurality of data groups, each of which has a first burst length and is transmitted in units of an input/output width, with a predetermined pattern, and perform data compression on the data groups based on a result of comparison. The controller further includes a compression data restructuring circuit configured to generate a transmission data group by restructuring the compressed data group to have a second burst length.

Abstract: While transmission of data to be transmitted and gap data to be transmitted by the same transmission path as that data is controlled so that a frequency of a data signal may become equal to or more than a certain frequency, a data output driver selects and outputs the data or the gap data as the data signal, a valid signal generation circuit outputs a valid signal that indicates whether or not the data is effective, and a reception circuit that is formed in a different die receives the data signal and the valid signal transmitted via the transmission path that includes a through silicon via and acquires the data from the data signal based on the valid signal.

Abstract: An SR latch circuit with single gate delay is provided. The circuit has an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage.

Abstract: Technical solutions are described for dynamically managing an operand-store-compare (OSC) prediction table for load and store operations executed out-of-order. One general aspect includes a method that includes receiving a request to retire a queue entry corresponding to an instruction. The method also includes identifying an OSC prediction for the instruction based on an OSC prediction table entry, where the OSC prediction indicates if the instruction is predicted to hit an OSC hazard. The method also includes determining if the instruction hit the OSC hazard. The method also includes in response to the OSC prediction indicating that the instruction is predicted to hit the OSC hazard and the instruction not hitting the OSC hazard, invalidating the OSC prediction table entry corresponding to the instruction. The present document further describes examples of other aspects such as methods, computer products.

Abstract: A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Abstract: A data transfer unit includes a page buffer to latch data of a normal bit line connected to a normal memory cell, a second page buffer to latch data of a parity bit line connected to a parity memory cell, and a third page buffer that is first replaced when the first page buffer is defective or when the second page buffer is defective. ECC Bus_1 is connected to the first, second, and third page buffers, respectively, and Data Bus_1 is connected to the first and third page buffers.

Abstract: An address input circuit of a semiconductor device includes: an address latch unit configured to generate latch addresses, by latching addresses sequentially provided by an external, according to a command decoding signal, wherein latch timings of each of the addresses are adjusted differently from one another; and a command decoder configured to decode a command provided from the external and generate the command decoding signal.

Abstract: A delay circuit includes units each of which includes a first delay element having a first input node and a first output node, a second delay element having a second input node and a second output node, and a third delay element between the first and second delay elements. The first output node of a first unit of the units is connected to the first input node of a second unit of the units. The second input node of the first unit is connected to the second output node of the second unit. A signal on the first input node of the first delay element of the first unit is output from the second output node of the second delay element of the first unit through the third delay element of the second unit.

Abstract: A data transfer unit includes a first page buffer to latch data of a normal bit line connected to a normal memory cell, a second page buffer to latch data of a parity bit line connected to a parity memory cell, and a third page buffer to be first replaced when the first page buffer is defective or when the second page buffer 102c is defective. An error code correction bus is connected to the first and second page buffers, and a data bus is connected to the first, second and third page buffers.

Abstract: A memory structure is provided that controls the activation of error handling bits as a function of operating voltage. In this way, error correction can be used to offset errors when the memory structure is run at low voltage (and frequency). However, negative performance impacts for such error correction, such as additional access latencies, can be avoided when the memory structure is run at higher voltage (and frequency) and memory errors are less likely. In addition, increased latencies due to evaluating error handling bits may be hidden by reading digital data bits from the memory structures speculatively and assuming no errors. Also, certain portions of memory structures may have larger cells, and therefore larger areas, than other portions, which may provide not only higher reliability at low operating voltages, but also faster operation with reduced latency.

Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.

Abstract: Integrated circuits with memory built-in self-test (BIST) logic and methods of testing using the same are disclosed. The method includes setting an address window for locating defects in a memory array. The method further includes comparing output data of the memory array to expected data to determine that a defect exists at location “M” in the memory array within the address window. The method further includes storing, in registers, the address M and a resultant bit fail vector associated with the location “M” of the defect found in the memory array. The method further includes resetting the registers to a null value and resetting the address window with a new minimum and maximum address pair, to compare the output data of the memory array to the expected data within the reset address window which excludes address M.

Abstract: A hybrid output driver includes a voltage mode main driver and a current mode emphasis driver that provides an adjustable differential output voltage swing. The current mode emphasis driver provides: push-pull swing control currents in response to a cursor data value, push-pull precursor currents in response to a precursor data value, and push-pull postcursor currents in response to a postcursor data value. In a normal operating mode, the swing control currents oppose voltages imposed by the voltage mode main driver on the differential output terminals. In a turbo operating mode, the swing control currents enhance voltages imposed by the voltage mode main driver on the differential output terminals.

Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

Abstract: A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.

Abstract: A device that includes first and second buffer circuits electrically connected to a terminal and an output control circuit activating the first buffer circuit and deactivating the second buffer circuit in a first state and activating one of the first and second buffer circuits and deactivating the other of the first and second buffer circuits based on input data in a second state. The output control circuit is brought into one of the first and second states.

Abstract: An embodiment of the present invention provides a semiconductor, including a non-volatile storage unit suitable for storing one or more first addresses; an address storage unit suitable for storing the first addresses sequentially received from the non-volatile storage unit as second addresses while deleting previously stored second addresses identical to an input address of the first addresses, in a reset operation; and a cell array suitable for replacing one or more normal cells with one or more redundancy cells based on the second addresses in an access operation.

Abstract: A non-volatile memory apparatus and a data verification method thereof are provided. The non-volatile memory apparatus includes a plurality of memory cells, a page buffer, a write circuit, a sense amplifier, and a sense and compare circuit. The page buffer stores a plurality of buffered data and programs the plurality of memory cells according to the plurality of buffered data. The write circuit receives a program data or a rewrite-in data and writes the program data or the rewrite-in data to the page buffer. The sense amplifier senses data read from the memory cells for generating a read-out data. The sense and compare circuit reads the buffered data, and compares the read-out data and a compared buffered data to generate a rewrite-in data. The sense and compare circuit determines the rewrite-in data to be the buffered data or an inhibiting data according to the compared result.

Abstract: A semiconductor memory device includes a first data bus having a first width, and a second data bus which is separate from the first data bus and which has a second width which is different from the first width. The semiconductor memory device further includes a data transfer unit configured for transferring data from memory cells connected to a plurality of bit lines. In a first operational mode, the data transfer unit connects a first number of bit lines from among the plurality of bit lines to the first data bus to transfer the data, the first number being equal to the first width. In a second operational mode, the data transfer unit connects a second number of bit lines from among the plurality of bit lines to the second data bus to transfer the data, the second number being equal to the second width.

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

Abstract: A semiconductor integrated circuit includes: a latch unit configured to latch data in response to an input control signal; and a latch control unit configured to determine whether or not any one of first and second memory areas is successively accessed, and adjust timing of the input control signal.

Abstract: Apparatus and methods are disclosed herein, including those that operate to initialize registers of a first memory device and a second memory device of a single-rank memory module by providing separate chip select signals to separately select a first memory device and a second memory device. A method may further include, subsequent to sensing that the initializing is completed, for example, providing a single chip select signal to simultaneously select the first memory device and the second memory device.

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

Abstract: A shared-signaling multi-device memory system is capable of changing between addressing modes without the multi-device memory being required to undergo a power cycle. First and second registers of a memory device are set to both contain first address-identification information in response a first address-assignment command that is received a power cycle. The first register is set to contain second address-identification information in response a second address-assignment command that is received subsequently to the first address assignment command. Depending on the value of the second address-identification information, the memory device is configured in an individual-device-addressing mode or a parallel addressing mode without a power cycle. The first register can be reset to the first address-identification information contained in the second register in response to an address-restore command without a power cycle. A corresponding method is also disclosed.

Abstract: A semiconductor device having a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell, so that the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced.

Abstract: Decoded 2n-bit bitcells in memory for storing decoded bits, and related systems and methods are disclosed. In one embodiment, a decoded 2n-bit bitcell containing 2n state nodes is provided. Each state node includes storage node to store decoded bit. Storage node provides bit to read bitline, coupled to decoded word output. Each state node includes active decoded bit input coupled to storage node that receives decoded bit from decoded word to store in storage node in response to write wordline. State node comprised of 2n?1 passive decoded bit inputs, each coupled to one of 2n?1 remaining storage nodes. 2n?1 passive decoded bit inputs receive 2n?1 decoded bits not received by active decoded bit input. State node includes logic that receives 2n?1 decoded bits. Logic retains decoded bit, provides it to passive decoded bit output. Passive decoded word output is coupled to storage node to store decoded bit in storage node.

Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.

Abstract: A memory operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory.

Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

Abstract: Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory device, the select command indicating a targeted memory volume of the plurality of memory volumes. In response to the select command, the method can include selecting the targeted memory volume of the memory volumes and putting at least a portion of a non-selected memory volume of the memory volumes in a particular state based, at least in part, on a previous state of the non-selected memory volume and/or a portion of an address associated with the select command.

Abstract: The semiconductor device includes an internal command generator and an internal address generator. The internal command generator generates first and second command latch signals from first and second internal clock signals in response to an external control signal and latches a command signal in response to the first and second command latch signals to generate a synthesized internal command signal. The internal address generator generates first and second address latch signals from the first and second internal clock signals in response to the external control signal and latches an address signal in response to the first and second address latch signals to generate a synthesized internal address signal.

Abstract: A pipe register circuit includes an address storage section configured to temporarily and sequentially store address signals input from an external in correspondence with a read command signal input together with the address signals, and an address output control section configured to generate an address output control signal for allowing the address signals stored in the address storage section to be output in correspondence with CAS latency, and output the address output control signal to the address storage section.

Abstract: A semiconductor memory device includes memory cells for storing data, page buffers each configured to comprise a dynamic latch and a static latch on which data to be programmed in to the memory cells or data read from the memory cells are latched, and a control logic configured to store a plurality of refresh mode select codes corresponding to various refresh cycles, and refresh the dynamic latch by exchanging data between the static latch and the dynamic latch according to a refresh cycle corresponding to a selected refresh mode select code.