Abstract: A decoder circuit to decode an address for accessing a memory cell in a memory array includes address latch circuitry, inverter circuitry, and first address pre-decode circuitry. The address latch circuitry receives an address signal and generates address holding signals during a setup period. The address latch circuitry latches the address holding signals during an address hold period following the setup period. The inverter circuitry receives the address signal and generates a complementary address signal. The first address pre-decode circuitry decodes the address signal and the address holding signals during the setup period to generate a first pre-decode address signal at an output of the first address pre-decode circuitry. In addition, the first address pre-decode circuitry decodes the address holding signals during the address hold period to maintain the first pre-decode address signal at the output of the first address pre-decode circuitry.

Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.

Abstract: A memory device includes a plurality of banks, a plurality of address buffers configured to receive addresses, and a buffer control unit configured to deactivate one or more of the plurality of address buffers when the number of activated banks among the plurality of banks is a prescribed number.

Abstract: Structures and related processes for effectively regulating power among slave chips in a 3D memory multichip package that employs TSVs for interlevel chip connections. Individual voltage regulators are employed on one or more of the slave chips for accurate level control of internal voltages, for example, word line driver voltage (VPP), back bias voltage (VBB), data line voltage (VDL), and bit line pre-charge voltage/cell plate voltage (VBLP/VPL). Employing regulators on one or more of the slave chips not only allows for precise regulation of power levels during typical memory stack operation, but also provides tolerance in small variations in power levels caused, for example, by manufacturing process variations. Moreover, less chip real estate is used as compared to techniques that provide complete power generators on each chip of a multichip stack.

Abstract: A semiconductor memory apparatus includes a reset pad configured to receive and transfer an external reset signal and an external control signal; a first input buffer configured to buffer the external reset signal in response to a buffer control signal and output an internal reset signal; a second input buffer configured to buffer the external control signal in response to the buffer control signal and output an internal control signal; and an input buffer control unit configured to generate the buffer control signal in response to an external command.

Abstract: A semiconductor device includes a pulse generation circuit configured to generate an enable pulse signal, which is activated in response to an active command signal and deactivated in response to a column command signal, and a plurality of fuse circuits configured to store repair addresses for a column repair and to output stored repair addresses in response to the enable pulse signal.

Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. Each half of the memory bank is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

Abstract: Command decoders are provided. The command decoder includes an input buffer configured for buffering and receiving command address signals having address information and command information at first, second, third, and fourth edges of a clock pulse signal according to a reference voltage, a latch circuit configured for latching the command address signals output from the input buffer at the first and third edges of the clock pulse signal to generate and output latched signals, a first command generator configured for decoding the latched signals output from the latch circuit at the first edge of the clock pulse signal to generate and output a first internal command, and a second command generator configured for decoding the latched signals output from the latch circuit at the third edge of the clock pulse signal to generate and output a second internal command.

Abstract: A semiconductor system including a semiconductor integrated circuit or a semiconductor chip, and a method of driving the semiconductor system are described. The semiconductor integrated circuit includes a plurality of semiconductor chips, at least one first chip through via suitable for penetrating through the plurality of semiconductor chips and interfacing a source ID code between the plurality of semiconductor chips, a plurality of second chip through vias suitable for penetrating through the plurality of semiconductor chips and interfacing a plurality of chip selection signals between the plurality of semiconductor chips, wherein the semiconductor chip uses one of chip selection signals as an internal chip selection signal in response to a chip ID code by selecting one of a unique ID code for the semiconductor chip and an alternative ID code for a preset semiconductor chip when the semiconductor chip fails.

Abstract: Disclosed is a flash memory device and programming method that includes; receiving buffer data and determining between a high-speed mode and a reliability mode for buffer data, and upon determining the reliability mode storing the buffer data in a first buffer region, and upon determining the high-speed mode storing the buffer data in a second buffer region. The memory cell array of the flash memory including a main region and a separately designated buffer region divided into the first buffer region and second buffer region.

Abstract: A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.

Abstract: A semiconductor device includes a first bit line section coupled to a first cell string, a second bit line section coupled to a second cell string, a page buffer coupled to the first bit line section and a switching circuit formed between the first bit line section and the second bit line section, wherein the switching circuit couples the first bit line section to second bit line section in response to a select signal.

Abstract: A memory includes a memory array having a plurality of word lines, a plurality of latching predecoders, and word line driver logic. Each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results.

Abstract: A new address transition detection (ATD) circuit for use on an address bus having a plurality of address signal lines comprises a first circuit for each address signal line and a second circuit. The first circuit has a first input, a second input and an output. The first input is coupled to an address signal line. The second input is coupled to an ATD signal. The first circuit saves the current level of the first input in response to an ATD pulse on the ATD signal and generates a change signal at its output by comparing the current level and the saved level of the first input. The second circuit has an input and an output. The second circuit receives on its input the change signal from the first circuit. In response, the second circuit generates the ATD pulse on the ATD signal at its output.

Abstract: A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal to output a first group identification signal, latch the identification signal in accordance with a second enable signal to output a second group identification signal, and latch the internal command signal in accordance with the second enable signal to output a group command signal. A comparator is configured to compare the first group identification signal with the second group identification signal, and generate a selection signal. A multiplexer is configured to select one of the group command signal and a module command signal as an input command in response to the selection signal.

Abstract: System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least two of the plurality of non-volatile memory to mitigate peak power consumption.

Abstract: A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different resistances at logic states “0” and “1.” A reference bit line is coupled to the supply voltage through a comparison resistance value, especially a resistance between high and low resistance of the memory element in the two logic states. Voltages on the bit line and reference bit line ramp toward a switching threshold at rates related to the resistance values. The first line to discharge to switching threshold voltage sets the sense circuit latch.

Abstract: A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

Abstract: A data output circuit includes an output control signal generation unit configured to generate output control signals in response to an output enable bar signal and a delay locked clock signal and a register configured to output stored data in response to the output control signals.

Abstract: A semiconductor memory apparatus includes: a data output signal transmitter configured to receive a data signal and a data mask signal and transmit a data output signal through a global data line, the data output signal being outputted by determining whether the data signal is masked or not; and a write driver configured to receive the data output signal through the global data line and input the received data output signal to a local data line corresponding to the data output signal.

Abstract: A semiconductor memory apparatus includes a reset pad configured to receive and transfer an external reset signal and an external control signal; a first input buffer configured to buffer the external reset signal in response to a buffer control signal and output an internal reset signal; a second input buffer configured to buffer the external control signal in response to the buffer control signal and output an internal control signal; and an input buffer control unit configured to generate the buffer control signal in response to an external command.

Abstract: A circuit includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102) is coupled to the memory and to the analog line coverage circuit, and the processor enables the analog line coverage circuit when the processor is in a debug mode.

Abstract: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells corresponding to intersections between the bit lines and the word lines, respectively, and including magnetic tunnel junction elements capable of storing data. A plurality of sense amplifiers respectively correspond to the bit lines and are configured to detect data stored in the memory cells via a bit line selected from among the corresponding bit lines. A plurality of read latch parts correspond to the sense amplifiers, respectively, and are configured to latch data detected by the corresponding sense amplifiers. A plurality of read global data buses are connected to the read latch parts, respectively, and are configured to consecutively transmit data latched by the read latch parts at a time of a data read operation.

Abstract: A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an MRS command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal.

Abstract: Systems and methods are provided for perform device selection in multi-chip package NAND flash memory systems. In some embodiments, the memory controller performs device selection by command. In other embodiments, the memory controller performs device selection by input address.

Abstract: According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.

Abstract: A semiconductor memory device includes a page buffer configured to store data read from a memory cell, a counter circuit configured to count the number of first data or second data in the read data for every read operation while the read operations are repeated a set number of times, and a control logic configured to determine the number of read operations and determine the read data of the memory cell based on the counted number.

Abstract: Described herein are embodiments of dynamic command slot realignment after clock stop exit. An apparatus configured for dynamic command slot realignment after clock stop exit may include memory including a first memory module configured to receive commands over a first channel via a first command slot and a second memory module configured to receive commands over a second channel via a second command slot, and a memory buffer configured to receive a clock sync command targeting the first command slot, and perform a write pointer exchange in response to detecting the clock sync command in the second command slot to realign the first command slot and the second command slot. Other embodiments may be described and/or claimed.

Abstract: According to the embodiments, a semiconductor memory device includes serially-connected cell transistors includes respective gate electrodes coupled to respective word lines, a first driver and a second driver which drive the word lines, and a connection module. The connection module electrically couples the first driver commonly to a first subset of the word lines, and electrically couples the second driver commonly to a second subset of the word lines different from the first subset of the word lines. The first and second subsets of the word lines include the same number of word lines.

Abstract: The data input circuit of a nonvolatile memory device includes a redundancy multiplexer configured to selectively output normal data and redundancy data to an internal global data line in response to a redundancy signal, a plurality of pipe registers coupled to the internal global data line and configured to latch normal data or redundancy data received through the internal global data line in response to a plurality of respective latch signals, and an output multiplexer configured to sequentially output the latched data in response to a plurality of selection signals.

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract: Circuitry that includes static random access memory (SRAM) access circuitry and a group of SRAM memory cells is disclosed. A digital fingerprint of the group of SRAM memory cells is determined by using the SRAM access circuitry to force at least a portion of the group of SRAM memory cells into a metastable state and then releasing the portion of the SRAM memory cells. Each SRAM memory cell that was released then selects one of two stable states and the SRAM access circuitry provides a selection profile based on the selections. The digital fingerprint is based on the selection profile.

Abstract: A semiconductor apparatus includes a first memory die; a second memory die; and a processor configured to provide an external command, an external start address and an external end address which are associated with a read operation, to the first memory die, and provide an external command, an external start address and an external end address, which are associated with a write operation, to the second memory die, in the case where data stored in the first memory die is to be transferred to and stored in the second memory die.

Abstract: Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.

Abstract: An address input circuit of a semiconductor device includes: an address latch unit configured to generate latch addresses, by latching addresses sequentially provided by an external, according to a command decoding signal, wherein latch timings of each of the addresses are adjusted differently from one another; and a command decoder configured to decode a command provided from the external and generate the command decoding signal.

Abstract: A decoder control makes use of controllable transfer gates, which effectively implement selectors, to implement required timing offsets for codes that have particular structure. For instance, such timing offsets are effective for LDPC codes with block off-diagonal structure, for instance, as described in the co-pending application. In some implementations, the memory architecture is formed of cells where each cell includes not only a storage element, by also control logic that combines a select signal and the write versus read signal. By co-locating this control logic in each memory cell, control logic and its associated signal distribution is reduced, thereby reducing circuit area and power consumption.

Abstract: A memory includes a plurality of latching predecoders, each including a first transistor coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.

Abstract: A semiconductor memory device includes a plurality of address input blocks configured to respectively receive a plurality of addresses that are related to burst ordering and a control circuit configured to selectively disable all or a part of the address input blocks in response to a burst length information during a write operation mode.

Abstract: A semiconductor memory apparatus includes a plurality of memory banks, wherein each memory bank includes a bank control unit configured to reduce a voltage level of a first node to a ground voltage level when the memory bank is selected to perform a predetermined operation; an error control unit configured to supply an external voltage to the first node when the memory bank is not selected to perform the predetermined operation; and a signal generation unit configured to generate a bank operation signal in response to the voltage level of the first node.

Abstract: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.

Abstract: According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases.

Abstract: A multiport latch-based memory device includes a latch array, a plurality of first multiplexers, and a second multiplexer. The latch array is responsive to output data from an input data register in a functional mode associated with the latch-based memory device. The plurality of first multiplexers is responsive to output data from the latch array in the functional mode. The plurality of first multiplexers is responsive to output data from the input data register in a test mode associated with the latch-based memory device. The second multiplexer selectively provides output data from the plurality of first multiplexers to the input data register in the test mode, thereby providing a data path bypassing the latch array in the test mode. Embodiments of a corresponding method and computer-readable medium are also provided.

Abstract: A semiconductor memory apparatus includes: a data output signal transmitter configured to receive a data signal and a data mask signal and transmit a data output signal through a global data line, the data output signal being outputted by determining whether the data signal is masked or not; and a write driver configured to receive the data output signal through the global data line and input the received data output signal to a local data line corresponding to the data output signal.

Abstract: A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.

Abstract: A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal.

Abstract: Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a memory block chip and a signal input/output chip. The memory block chip is configured to control a data access size according to specifications. The signal input/output chip is configured to transmit input data from an external device to the memory block chip or transmit output data from the memory block chip to an external device and process the input data or the output data by selectively enabling a clock phase control unit and a signal processing unit according to the specifications.

Abstract: A semiconductor apparatus includes an odd data clock buffer group configured to maintain or shift a phase of a multi-phase source clock signal, and output a first multi-phase clock signal, an even data clock buffer group configured to maintain or shift a phase of the multi-phase source clock signal, and output a second multi-phase clock signal, an odd data output buffer group configured to drive odd data in response to the first multi-phase clock signal and output the driven data to an odd data pad group, and an even data output buffer group configured to drive even data in response to the second multi-phase clock signal and output the driven data to an even data pad group, wherein the phases of clock signals of the first and second multi-phase clock signal are different from each other.

Abstract: Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal.

Abstract: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg?Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub?Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.