Read Mode Signal Only Patents (Class 365/233.17)
  • Patent number: 10824188
    Abstract: In one embodiment, the present disclosure includes multichip timing synchronization circuits and methods. In one embodiment, hardware counters in different systems are synchronized. Programs on the systems may include synchronization instructions. A second system executes synchronization instruction, and in response thereto, synchronizes a local software counter to a local hardware counter. The software counter on the second system may be delayed a fixed period of time corresponding to a program delay on the first system. The software counter on the second system may further be delayed by an offset to bring software counters on the two systems into sync.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: November 3, 2020
    Assignee: Groq, Inc.
    Inventors: Gregory Michael Thorson, Srivathsa Dhruvanarayan
  • Patent number: 9824056
    Abstract: The timing of the synchronous interface is controlled by a dock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: November 21, 2017
    Assignee: Rambus Inc.
    Inventor: Yuanlong Wang
  • Patent number: 9036437
    Abstract: A method and an apparatus for testing a memory are provided, and the method is adapted for an electronic apparatus to test the memory. In the method, a left edge and a right edge of a first waveform of a clock signal for testing the memory are scanned to obtain a maximum width between two cross points of the left edge and the right edge. A central reference voltage of a data signal outputted by the memory is obtained, and a data width between two cross points of the central reference voltage and a left edge and a right edge of a second waveform of the data signal is obtained. Whether a difference between the data width and the maximum width is greater than a threshold is determined; if the difference is greater than the threshold, the memory is determined to be damaged.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: May 19, 2015
    Assignee: Wistron Corporation
    Inventor: Min-Hua Hsieh
  • Patent number: 8976619
    Abstract: A semiconductor apparatus includes a phase detecting unit that continuously detects a first delay amount during a read operation, based on a phase difference between an external clock signal and an internal clock signal; a generating unit that generates a second control signal by delaying a first control signal by a second delay amount that when added to the first delay amount, the sum is a specific time period, a valid time period of the first control signal starts when the read operation starts and is at least to equal a read time for one data signal and less than the specific time period that is from the start of the read operation until output of a received data signal; and a delay control unit that delays the data signal by the first delay amount detected at a start of a valid time period of the generated second control signal.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 10, 2015
    Assignee: Fujitsu Limited
    Inventor: Noriyuki Tokuhiro
  • Patent number: 8958254
    Abstract: An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: February 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Manish Chandra Joshi, Parvinder Kumar Rana, Lakshmikantha Vakwadi Holla
  • Patent number: 8913459
    Abstract: A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with the clock signal. A read clock signal is provided to the plurality of DRAM devices to initiate a read operation in one of the plurality of DRAM devices that is selected by the address. The one DRAM device delays the read clock signal by an amount based on a speed of the one of the plurality of DRAM devices to generate. First delayed read clock and second delayed read clock signals are provided. The read data is received on the data bus in synchronization with the second delayed read clock signal.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: December 16, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Chikara Kondo
  • Patent number: 8873304
    Abstract: In various embodiments an integrated circuit or chip is provided, the integrated circuit including a memory device including a plurality of memory cells, and with the memory cells being configured to store a data content, and a controller being configured to write a predefined data pattern in the memory cells of the memory device, reading the data content of the memory cells, mapping each read data content which corresponds to an expected data content depending on the predefined data pattern to a predefined instruction for the controller, with the predefined instruction causing the controller to carry out a predefined action which is representative for the accurate operation of the memory cells, determining that the memory device operates accurately, if the controller carries out the predefined action, and determining that the memory device does not operate accurately, if the controller does not carry out the predefined action.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventor: Stephan Kronseder
  • Patent number: 8867287
    Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jin Youp Cha, Jae Il Kim
  • Patent number: 8842470
    Abstract: A memory control module includes a read module configured to receive a first signal read from a first storage region of a memory cell, and receive a second signal read from a second storage region of the memory cell. A data detection module is configured to, based on a noiseless signal, detect respective data in each of the first storage region and the second storage region. The noiseless signal includes an ideal signal and an interference signal associated with at least one of the first signal and the second signal.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: September 23, 2014
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Zining Wu
  • Patent number: 8804441
    Abstract: Methods and systems for detection and correction of timing signal drift in memory systems are provided. A start time and an end time of a first time interval is determined with control circuitry such that a last falling edge in a first of a plurality of data strobe sequences received from the memory occurs outside of the first time interval. A start time and an end time of a close-enable time interval is adjusted based at least in part on determining whether a second of the plurality of data strobe sequences occurs within the first time interval. Sampling of data received from the memory is disabled in response to determining that the last falling edge in the second received data strobe sequence occurs within the close-enable time interval.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: August 12, 2014
    Assignee: Marvell International Ltd.
    Inventor: Ross Swanson
  • Patent number: 8797823
    Abstract: A method and circuit for implementing faster-cycle-time and lower-energy write operations for Synchronous Dynamic Random Access Memory (SDRAM), and a design structure on which the subject circuit resides are provided. A first RAS (row address strobe) to CAS (column address strobe) command delay (tRCD) is provided to the SDRAM for a read operation. A second delay tRCD is provided for a write operation that is substantially shorter than the first delay tRCD for the read operation.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Connolly, Kyu-hyoun Kim, Warren E. Maule
  • Patent number: 8760946
    Abstract: Various method and apparatus embodiments for training a delay for enabling a data strobe signal in a memory subsystem are disclosed. In one embodiment, a system includes a memory controller configured to receive a data strobe signal. The memory controller includes a training circuit. The training circuit includes a first storage circuit coupled to receive the data strobe signal on a data input and an enable signal on a clock input, and a training unit configured to, based on an output signal received from the first flip-flop, adjust a phase of the enable signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: June 24, 2014
    Assignee: Advanced Micro Devices
    Inventors: Glenn A Dearth, Warren R Anderson, Anwar P Kashem, Richard W Reeves, Edoardo Prete, Gerald R Talbot
  • Patent number: 8755220
    Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: John F. Bulzacchelli, William J. Gallagher, Mark B. Ketchen
  • Patent number: 8724423
    Abstract: A memory operative to provide concurrent two-port read and two-port write access functionality includes a memory array comprising first and second pluralities of single-port memory cells organized into a plurality of rows of memory banks, and multiple checksum modules. The second plurality of memory cells are operative as spare memory banks. Each of the checksum modules is associated with a corresponding one of the rows of memory banks. The memory further includes a first controller and multiple mapping tables. The first controller and at least a portion of the first and second pluralities of memory cells enable the memory array to support two-port read or single-port write operations. A second controller is operative to receive read and write access requests, and to map logical and spare memory bank identifiers to corresponding physical memory bank identifiers via the mapping tables to thereby emulate concurrent two-port read and two-port write access functionality.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: May 13, 2014
    Assignee: LSI Corporation
    Inventors: Ting Zhou, Sheng Liu
  • Patent number: 8717832
    Abstract: Within a non-volatile memory device, a read operation directed to a nonvolatile memory cell having a positive threshold voltage applies a positive read voltage to a selected word line and a first control signal to a page buffer connected to a selected bit line, but if the memory cell has a negative threshold voltage the read operation applies a negative read voltage to the selected word line and a second control signal to the page buffer different from the first control signal.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 6, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seung-Bum Kim
  • Patent number: 8711605
    Abstract: A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventor: R. Jacob Baker
  • Patent number: 8705285
    Abstract: A system including a read module and a sequence detector module. The read module is configured to read a plurality of memory cells located along a bit line or a word line of a memory array and to generate a plurality of read signals. The sequence detector module is configured to detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals and (ii) a plurality of reference signals associated with the plurality of memory cells. One of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes (i) a first signal and (ii) a second signal. The first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line. The second signal includes interference from the second memory cell.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 22, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Xueshi Yang, Zining Wu
  • Patent number: 8705279
    Abstract: In a method of reading a nonvolatile memory device, the method comprising, a reading operation of reading data of a selected memory cell; and a read retry operation of performing one or more read operations by changing a non-selection read voltage applied to non-selected memory cells until the read operation succeeds, when it is detected that an error has occurred in the operation of reading data.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: April 22, 2014
    Assignee: SK Hynix Inc.
    Inventor: Se Hyun Kim
  • Patent number: 8699291
    Abstract: Circuits and techniques for operating a memory circuit are disclosed. A disclosed circuit includes a memory circuit and a sleep circuit with an output terminal coupled to the memory circuit. The sleep circuit is operable to receive a control signal and further operable to place the memory circuit in different modes of operation. The memory circuit may be placed in either a first mode of operation, a second mode of operation or a third mode of operation based at least partly on the control signal. An input terminal of the sleep circuit is coupled to an output terminal of the control circuit. The control circuit is operable to receive an enable signal and is operable to supply the control signal to the sleep circuit at first, second and third voltage levels during the first, second and third modes of operation, respectively, based on the enable signal and a clock signal.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: April 15, 2014
    Assignee: Altera Corporation
    Inventors: Chin Ghee Ch'ng, Wei Yee Koay, Boon Jin Ang
  • Patent number: 8693230
    Abstract: Disclosed herein is a device that includes a plurality of stacked core chips and an interface chip that controls the core chips. Each of the core chips includes a memory cell array, a penetration electrode, and an output circuit that outputs read data that are read from the memory cell array to the penetration electrode. The penetration electrode respectively provided in the core chips are commonly connected with each other, and the output circuits respectively provided in the core chips are activated in response to a read clock signal supplied from the interface chip.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 8, 2014
    Assignee: Elpida Memory, Inc.
    Inventor: Chikara Kondo
  • Patent number: 8675392
    Abstract: Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration to be sufficient for the write operation. In some embodiments, the pulse utilized for the reading may have an absolute value of voltage that is greater than or equal to the voltage utilized for the write operation. In some embodiments, the memory cells may comprise non-ohmic devices; such as memristors and diodes.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: March 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Bhaskar Srinivasan, Gurtej S. Sandhu
  • Patent number: 8671303
    Abstract: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: March 11, 2014
    Assignee: Altera Corporation
    Inventors: Yan Chong, Bonnie I. Wang, Chiakang Sung, Joseph Huang, Michael H. M. Chu
  • Patent number: 8625384
    Abstract: A synchronous type semiconductor storage device includes an array unit which includes a cell array and sense amplifiers. The synchronous type semiconductor storage device includes a read/write pulse generator which generates a read pulse signal and a write pulse signal according to a clock signal, the clock signal defining one cycle time of a read operation and a write operation with respect to the array unit as one cycle. The synchronous type semiconductor storage device includes a secondary amplifier which is activated according to the read pulse signal to read out data stored in the sense amplifiers through the read/write line. The synchronous type semiconductor storage device includes a write driver which is activated according to the write pulse signal to write data in the sense amplifiers through the read/write line.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: January 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mariko Iizuka
  • Patent number: 8593889
    Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: November 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Dean K. Nobunaga, June Lee, Chih Liang Chen
  • Patent number: 8582392
    Abstract: A non-volatile memory device is operated by outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively. A determination is made whether the read control signal and a write control signal are in synchronization at one of the first edges. Output of the data is stopped at the second edge that follows the one of the first edges of the read control signal if the read control signal and the write control signal are in synchronization at the one of the first edges.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-ryul Ryu
  • Patent number: 8576642
    Abstract: In at least one embodiment, a multiplexer has a plurality of sub-circuits, and each of the plurality of sub-circuits has a first transistor, a second transistor, and a third transistor. Drains of the first transistors are coupled with a first terminal of a fourth transistor, and drains of the second transistors are coupled with a second terminal of the fourth transistor. In at least one embodiment, a method of outputting data using the multiplexer includes turning on the second transistor of a selected one of the plurality of sub-circuits responsive to a clock signal and address information. The second transistor of a non-selected one of the plurality of sub-circuits is turned off. The fourth transistor is turned on responsive to the clock signal.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: November 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bin-Hau Lo, Yi-Tzu Chen, C. K. Su, Hau-Tai Shieh
  • Patent number: 8576612
    Abstract: A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: November 5, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Manish Garg, Chiaming Chai, Michael ThaiThanh Phan
  • Patent number: 8565033
    Abstract: Integrated circuits may communicate with off-chip memory. Such types of integrated circuits may include memory interface circuitry that is used to interface with the off-chip memory. The memory interface circuitry may be calibrated using a procedure that includes read calibration, write leveling, read latency tuning, and write calibration. Read calibration may serve to ensure proper gating of data strobe signals and to center the data strobe signals with respect to read data signals. Write leveling ensures that the data strobe signals are aligned to system clock signals. Read latency tuning serves to adjust read latency to ensure optimum read performance. Write calibration may serve to center the data strobe signals with respect to write data signals. These calibration operations may be used to calibrate memory systems supporting a variety of memory communications protocols.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: October 22, 2013
    Assignee: Altera Corporation
    Inventors: Valavan Manohararajah, Ivan Blunno, Ryan Fung, Navid Azizi
  • Patent number: 8547732
    Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: John F Bulzacchelli, William J Gallagher, Mark B Ketchen
  • Patent number: 8547779
    Abstract: An interleaved memory circuit includes a memory bank including at least one first memory cell for storing a charge representative of a first datum, the first memory cell being coupled with a first word line and a first bit line. The interleaved memory circuit further includes a local control circuit coupled with the memory bank. The interleaved memory circuit further includes a global control circuit coupled with the local control circuit, an interleaving access including a clock signal having a first cycle and a second cycle for accessing the first memory cell, where the second cycle is capable of enabling the local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: October 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuoyuan Hsu, Ming-Chieh Huang, Young Suk Kim, Subramani Kengeri
  • Patent number: 8526249
    Abstract: Methods and systems for detection and correction of timing signal drift in memory systems are provided. A start time and an end time of a first time interval is determined with control circuitry such that a last falling edge in a first of a plurality of data strobe sequences received from the memory occurs outside of the first time interval. A start time and an end time of a close-enable time interval is adjusted based at least in part on determining whether a second of the plurality of data strobe sequences occurs within the first time interval. Sampling of data received from the memory is disabled in response to determining that the last falling edge in the second received data strobe sequence occurs within the close-enable time interval.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: September 3, 2013
    Assignee: Marvell International Ltd.
    Inventor: Ross Swanson
  • Patent number: 8503250
    Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: August 6, 2013
    Assignee: MOSAID Technologies Incorporated
    Inventor: Paul Demone
  • Patent number: 8477558
    Abstract: Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: July 2, 2013
    Assignee: Intel Corporation
    Inventors: Jaume Abella, Xavier Vera, Javier Carretero Casado, Pedro Chaparro Monferrer, Antonio González
  • Patent number: 8462561
    Abstract: A burst read control circuit acts as an interface to allow a burst-read capable device to execute burst reads from a page-mode capable memory device. The burst read control circuit coordinates burst read requests from the burst-read capable device and subsequent responses from the page-mode capable memory device by accessing subsequent and contiguous memory locations of the page-mode capable memory device.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: June 11, 2013
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Dean Anthony Rametta
  • Patent number: 8451671
    Abstract: A multiplexing circuit includes a plurality of first circuits and a second circuit coupled to outputs of the plurality of first circuits. A first circuit of the plurality of first circuits is configured to receive a first data line as a first input and a clock signal as a second input, and provide an output signal to a first circuit output. After the first circuit is selected for use, the clock signal, a first sub-circuit of the first circuit coupled to the second circuit, and the second circuit are configured to provide a first output logic level to the output signal based on a first data logic level of the first data line; and a second sub-circuit of the first circuit coupled to the first circuit output is configured to provide a second output logic level to the output signal based on a second data logic level of the first data line.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bin-Hau Lo, Yi-Tzu Chen, C. K. Su, Hau-Tai Shieh
  • Patent number: 8452465
    Abstract: Systems and methods for reconfiguring ECU tasks for ensuring that a vehicle is operational upon failure of a task or an ECU. A first on-board reconfiguration strategy is generated and executed by an on-board unit of the vehicle to bring the vehicle to a safe state and a second off-line reconfiguration strategy is generated by a remote center unit and then executed by the on-board unit.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: May 28, 2013
    Assignee: GM Global Technology Operations LLC
    Inventors: Purnendu Sinha, Thomas E. Fuhrman
  • Patent number: 8441834
    Abstract: A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: May 14, 2013
    Assignee: Micron Technology, Inc.
    Inventor: R. Jacob Baker
  • Patent number: 8427899
    Abstract: A clock signal having a clock pulse width duration is received. A delay time is received. A first relationship and a second relationship between the clock pulse width duration and the delay time are determined. A new clock is generated that has a first new clock pulse width duration determined by the first relationship and the delay time and a second new clock pulse width duration determined by the second relationship and the clock pulse width duration. Switching between the first new clock pulse width duration and the second new clock pulse width duration is automatic based on the first relationship and the second relationship.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: April 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jack Liu
  • Patent number: 8422331
    Abstract: A data output control circuit controls a data output in a read operation. A data output control method includes a count shifting mode and a delay mode and can be used in low and high frequency operations, so that a data output can be stably controlled in a broad frequency range. The data output control circuit includes: a low frequency mode controller a high frequency mode controller and a selector selecting any one of first and second command signals through CAS latency information to be output as a data output control signal.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: April 16, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyeng Ouk Lee
  • Patent number: 8406080
    Abstract: A semiconductor memory device using system clock with a high frequency can maintain a constant operation margin even in the change of operation environments including voltage level, temperature, and process. The semiconductor memory device includes an output control signal generator configured to be responsive to a read pulse that is activated in response to a read command, to generate an odd number of first output source signals corresponding to a rising edge of a system clock and a even number of second output source signals corresponding to a falling edge of the system clock, and an output enable signal generator configured to generate a first rising enable signal and a falling enable signal on the basis of the first output source signal and generate a second rising enable signal on the basis of the second output source signal, according to column address strobe (CAS) latencies, the first rising enable signal being activated earlier than the second rising enable signal by a half cycle of the system clock.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: March 26, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee-Jin Byun
  • Patent number: 8395946
    Abstract: The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data according to the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: March 12, 2013
    Assignee: MStar Semiconductor, Inc.
    Inventors: Eer-Wen Tyan, Ming-Chieh Yeh, Yi Ling Chen
  • Patent number: 8385133
    Abstract: A flash memory system for an A/V player, utilizing a two-level round-robin write scheme upon N flash memory planes, enabling the A/V player to be loaded with data at a data throughput essentially N times the write throughput of one of the flash memory planes. The flash chips' memory cores and data registers, and the memory system's write buffers, can be kept fully utilized during data writing.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: February 26, 2013
    Assignee: Avnera Corporation
    Inventor: Charles L. Saxe
  • Patent number: 8369160
    Abstract: Various embodiments of a data output circuit of a semiconductor memory and related method are disclosed. In one exemplary embodiment, a data output circuit may include a plurality of global lines, a sense amplifier block configured to output a plurality of data to the plurality of global lines at different timings, a pipe latch block configured to latch the plurality of data transmitted through the plurality of global lines at different timings, and a control unit configured to control output timings of the plurality of data from the sense amplifier block and latch timings of the pipe latch block using an address signal.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: February 5, 2013
    Assignee: SK Hynix Inc.
    Inventor: Jae IL Kim
  • Patent number: 8369181
    Abstract: A semiconductor IC device includes a command decoder that provides internal read and internal write command signals in response to external command signals, and a delay control unit that is connected with the command decoder and provides an internal read command delay signal by controlling an activation timing of the internal read command signal in response to a test mode signal in a read mode.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: February 5, 2013
    Assignee: SK Hynix Inc.
    Inventor: Sun Hwa Park
  • Patent number: 8351281
    Abstract: A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: January 8, 2013
    Assignee: Rambus Inc.
    Inventors: Richard E Perego, Frederick A Ware
  • Patent number: 8325531
    Abstract: Systems (100) and methods (600) for reading data from a memory device (106). The methods involve (606) receiving first read request signals (118, 120, 122, 126, 128) for first data stored in the memory device. In response to the first read request signals, (608) retrieving a first page of data from a cell array (268) of the memory device. The methods also involve (616) receiving second read request signals for second data stored in the memory device. (618) Next, a determination is made as to whether at least a portion of a memory address for the second data is the same as at least a respective portion of a memory address for the first data. (622) If it is determined that the respective portions of the memory addresses are the same, then a read access to the cell array is disabled.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: December 4, 2012
    Assignee: Spansion LLC
    Inventor: Allan Parker
  • Patent number: 8310889
    Abstract: A semiconductor device including a plurality of memory cells arranged in a matrix pattern, a write amplifier which writes write data to the memory cell in synchronization with a clock, a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock, a plurality of column select switches which connect the plurality of the memory cells with the sense amplifier and the write amplifier, a column address decoder which makes the column select switch corresponding to one column among the plurality of the memory cells a conductive state based on a column address, a row address decoder which activates the memory cell of one row based on a row address, and a test write circuit which writes data corresponding to a logical level of a test signal to the memory cell based on a test mode signal.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Akihiro Banno
  • Patent number: 8284588
    Abstract: In a non-volatile logic circuit, a first input electrode and a second input electrode are formed on a semiconductor layer and interposed between an electric current source electrode and an output electrode in a plan view. The first input electrode is next to the second input electrode along the a direction orthogonal to the direction between the electric current source electrode and the output electrode. A method of operating the non-volatile logic circuit includes a step of writing one state selected from four states by applying voltages to the first input electrode and the second input electrode, respectively, and a step of measuring current generated by applying the voltage between the electric current power electrode and the output electrode to determine on the basis of the current, which of the high or low resistant state the non-volatile logic circuit has.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: October 9, 2012
    Assignee: Panasonic Corporation
    Inventor: Yukihiro Kaneko
  • Patent number: 8274849
    Abstract: An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Philippe Bauser
  • Patent number: 8270227
    Abstract: A method of reading a nonvolatile memory device comprises sensing data stored in memory cells adjacent to selected memory cells to identify adjacent aggressor cells, and performing separate precharge operations on bitlines connected to selected memory cells having adjacent aggressor cells and on bitlines connected to selected memory cells having adjacent non-aggressor cells.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: September 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Woo Park, Ohsuk Kwon