Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

Abstract: Methods, systems, and devices for configurable memory die capacitance are described. A memory device may include a capacitive component, which may include one or more capacitors and associated switching components. The capacitive component may be coupled with an input/output (I/O) pad and an associated input buffer, and the one or more capacitors of the capacitive component may be selectively couplable with the I/O pad via the switching components. Switching components may be activated individually, in coordination, or not at all, such that one, multiple, or none of the capacitors may be coupled with the I/O pad. The capacitive component, I/O pad, and input buffer may be included in a same die of the memory device. In some cases, a configuration of the capacitive component may be based on signaling received from a host device.

Abstract: A signal generation circuit includes: a clock module, configured to generate a clock signal based on a flag signal; a control module, configured to generate a control signal according to number of transitions of the clock signal within a fixed time; and a generation module, respectively connected to the clock module and the control module, and configured to receive the clock signal, the control signal, and the flag signal, and to generate a target signal. When the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level. After being maintained at the fourth level for a target duration, the target signal changes from the fourth level to the third level. The generation module is further configured to determine the target duration according to the clock signal and the control signal.

Abstract: A data path architecture and corresponding method of operation are disclosed that permit a first-in-first out (FIFO) buffer to immediately flush data—including potentially invalid initial byte(s)—upon receipt of a high-speed clock signal, and according to which, a delay difference between a data path clock signal and a high-speed clock signal is compensated for at a controller side by, for example, adjusting RE latency to discard/ignore the initially invalid bytes rather than by modifying FIFO depth or varying a number of delay stages in the high-speed clock signal path in order to satisfy the FIFO depth. Because FIFO depth is not used to absorb the clock signal delay difference, there is no need to modify the architecture (e.g., change the depth of a FIFO) to accommodate variation in the clock signal delay difference across different products/product generations, thereby providing high scalability.

Abstract: A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.

Abstract: Systems and methods are provided for controlling a sleep operation for a memory array. A memory system may include a memory array with a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell. The memory array may further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off. A latch circuit may generate the local word line sleep signal in response to a delayed clock signal and one or more power management control signals. The word line clock signal and the delayed clock signal may both being generated as a function of a memory clock signal.

Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

Abstract: A system and method for efficiently generating clock signals are described. In various implementations, an integrated circuit includes multiple clock frequency dividers both at its I/O boundaries and across its die. A clock frequency divider utilizes a first clock divider and a second clock divider that receive input clock signals with an initial phase difference between them. The first clock divider and the second clock divider generate output clock signals that have frequencies that are a fraction of the frequencies of the received input clock signals. The second clock divider uses a combined multiplexer and flip-flop (combined mux-flop) circuit. The combined mux-flop circuit receives a reset signal that is asserted asynchronously with respect to an input clock signal received by the second clock divider. The second clock divider generates an output clock signal that has the initial phase difference with an output clock signal of the first clock divider.

Abstract: The disclosure relates to a method for enabling the secure functions of a chipset (1) and especially the encryption of the content of the secure memory (7) when the device goes into low power mode. The content of the secure memory (7) may be encrypted and stored in an external memory (20) during low power mode of the chipset (1).

Abstract: Methods, systems, and devices for dynamic random access memory speed bin compatibility are described. For instance, a device (e.g., a memory device, a host device) may combine a first parameter with a second parameter to generate a third parameter, where the first parameter may be associated with a duration for a clock that is coupled with a memory array to perform a clock cycle and the second parameter may be associated with a timing constraint associated with initiating an access operation for the memory array. The device may determine a latency of a column address strobe based on the third parameter relative to (e.g., satisfying) a threshold value and may access one or more memory cells of the memory array based on the latency of the column address strobe.

Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. The latch clock generator includes a first inverter configured to generate an inverted signal of the first enable signal, and a NAND gate coupled to the first inverter to receive the inverted signal of the first enable signal. The NAND gate is configured to generate the latched clock signal based on the clock signal and the inverted signal of the first enable signal.

Abstract: A memory device includes a command interface configured to receive a two-cycle command from a host device via multiple command address bits. The memory device also includes a command decoder configured to decode a first portion of the multiple command address bits in a first cycle of the two-cycle command. The command decoder includes mask circuitry. The mask circuitry includes mask generation circuitry configured to generate a mask signal. The mask circuitry also includes multiplexer circuitry configured to apply the mask signal to block the command decoder from decoding a second portion of the multiple command address bits in a second cycle of the two-cycle command.

Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.

Abstract: Methods, systems, and devices for memory device access techniques are described. Memory systems may be enabled to allow device-controlled access to a portion of volatile memory at a host system. By enabling the memory system to access volatile memory at the host system, the memory system may perform access operations which may reduce a quantity of messages exchanged between the memory system to the host system. The host system may allocate a list of memory resources in volatile memory associated with a first access command. The host system may allocate the same memory resources for a second access command. By allocating the same memory resources, the memory device may transmit a Ready To Transfer (RTT) message for multiple access commands, rather than for each command. In some cases, reducing the quantity of RTT messages may reduce latency and improve performance at the memory system.

Abstract: A switch activation system including a charge pump, a load monitor, and a switch driver. The charge pump drives a negative voltage node to a predetermined negative voltage level. The load monitor monitors the charge pump and to assert a break done signal after the charge pump begins driving the negative voltage back to the predetermined negative voltage level after being increased. The switch driver turns on a first electronic switch in response to assertion of a corresponding activation signal and assertion of the break done signal. The break done signal is asserted only after electronic switches being turned off are fully turned off to avoid conflict. The charge pump operates at a frequency based on a difference between a voltage level of the negative voltage node and the predetermined negative voltage level to drive the negative voltage node back to its predetermined level within a predetermined period of time.

Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

Abstract: A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device compares a received signal with an original signal to generate a driving force control signal. The first semiconductor device also drives the original signal using a driving force in accordance with the driving force control signal to output an external transmission signal. The second semiconductor device receives the external transmission signal to generate a positive signal and a negative signal. The second semiconductor device also generates a restoration signal in response to the positive signal and the negative signal. The second semiconductor device additionally outputs the restoration signal as the external transmission signal to the first semiconductor device.

Abstract: A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.

Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

Abstract: A memory controller for accessing a memory, comprises a holding circuit which holds a plurality of read or write access requests from a bus master, a read/write control circuit which selects one of the access requests in the holding circuit and issues a read command or a write command; and an active control circuit which selects the access request held in the holding circuit and issues an active command, wherein the active control circuit includes a generation circuit that generates number of activated read commands and number of activated write commands, and a selection circuit that, when the number of activated read commands is not less a threshold, issues the active command of an read access, and when the number of activated write commands is not less than the threshold, issues the active command of a write access.

Abstract: A clock signal processing circuit includes a clock buffer configured to generate a pair of second clock signals with opposite phases after receiving a pair of first clock signals with opposite phases and configured to fix the second clock signals to determined levels according to a control signal until toggling of the first clock signals begins.

Abstract: The present technology relates to a page buffer and a semiconductor memory device including the same. The page buffer includes a bit line selector configured to connect a bit line of a memory cell array to a sensing node, a precharger configured to precharge a potential of the sensing node to a first level, and a latch component configured to sense data by detecting a time at which the potential of the sensing node is decreased from the first level to a second level.

Abstract: An integrated circuit includes a drivability control circuit and a data output circuit. The drivability control circuit is configured to generate a drivability control signal based on data patterns of a plurality of pieces of data. The data output circuit is configured to control drivability, which is reflected to each of the plurality of pieces of data, based on the drivability control signal.

Abstract: A data writing control device includes a control signal generator, a data strobe enable signal generator and a data strobe index generator. The control signal generator receives a write command, a preamble setting value and a latency setting value, and generates an internal write pulse and preamble information according to the write command, the preamble setting value and the latency setting value. The data strobe enable signal generator is coupled to the control signal generator and generates a data strobe pipeline enable signal according to the internal write pulse and the preamble setting value. The data strobe index generator is coupled to the data strobe enable signal generator, and generates a plurality of data strobe indexes according to the data strobe pipeline enable signal and the preamble information.

Abstract: A reference voltage training circuit may include: a normal buffer configured to generate a first received signal by receiving one of differential signals based on the other; a calibration signal generation circuit configured to generate a second received signal by receiving the one of the differential signals according to a reference voltage, and generate reference voltage calibration signals by comparing the phase of the second received signal to the phase of the first received signal; and a reference voltage generation circuit configured to calibrate the level of the reference voltage according to the reference voltage calibration signals.

Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

Abstract: A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.

Abstract: A memory device including a memory array operatively coupled to an array data bus and a deserializer circuit operatively coupled with the array data bus. The deserializer circuit includes a first ring counter including a first set of flip-flops to sequentially output a set of rising edge clock signals based on a reference clock input and a second ring counter portion including a second set of flip-flop circuits to sequentially output a set of falling edge clock signals based on the reference clock input. A rising data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a rising data portion from a respective latch circuit in response to a rising edge clock signal. A falling data circuit portion of the deserializer circuit includes a set of flip-flops that each receive a falling data portion from a respective latch circuit in response to a falling edge clock signal.

Abstract: The disclosure relates to a method for enabling the secure functions of a chipset (1) and especially the encryption of the content of the secure memory (7) when the device goes into low power mode. The content of the secure memory (7) may be encrypted and stored in an external memory (20) during low power mode of the chipset (1).

Abstract: A memory device and a glitch prevention method thereof are provided. The memory device includes a data strobe signal input circuitry, a transfer signal generating circuitry, a data alignment circuitry, and a blocking circuitry. The data strobe signal input circuitry is configured to input a data strobe signal. The transfer signal generating circuitry is configured to generate a transfer signal with pulses in synchronization with rising edges or falling edges of the data strobe signal in response to a transfer command. The data alignment circuitry is configured to align a data signal to be transferred in response to the generated transfer signal. The blocking circuitry is configured to block an input of the data strobe signal over a postamble timing of the data strobe signal according to a number of bursts counted in each time of data transfer.

Abstract: A storage device includes a semiconductor memory device and a storage controller. The semiconductor memory device receives write data based on a data strobe signal and data signals, and outputs read data based on the data strobe signal and the data signals. The storage controller transmits the data strobe signal and the data signals in parallel to the semiconductor memory device through signal lines. The storage controller includes a first delay circuit that delays the data signals such that some edges of windows of the data signals on the signal lines are desynchronized by first skew offsets which are different from one another.

Abstract: A memory system includes a memory medium and a memory controller configured to control the memory medium. The memory controller includes a training core and a training block. The training core is configured to detect a delay time of a clock signal to generate a delay selection signal during a training operation for the memory medium. The training block is configured to generate a delayed clock signal which is delayed by a time period set according to the delay selection signal outputted from the training core.

Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

Abstract: Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. The memory has a read operation for the first read mode including a first pre-access phase, an access phase, and a first post-access phase. The read operation for the second read mode includes a second pre-access phase, the access phase, and a second post-access phase. The read operation for either the first read mode or the second read mode is performed responsive to the memory receiving a read command. The second pre-access phase is different from the first pre-access phase, with the second pre-access phase having a shorter time than the first pre-access phase measured from receipt of the read command.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.

Abstract: An electronic device includes a write shift circuit configured to generate, when a write operation is performed, a period signal which is activated for a clock enable period, based on a write command in synchronization with a write clock signal. The electronic device also includes a clock generation circuit configured to generate, when the write operation is performed, the write clock signal based on the period signal. The electronic device further includes a termination control circuit configured to generate a termination enablement signal, based on the period signal in the write operation, which is activated for a termination operation period.

Abstract: Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.

Abstract: A group control circuit includes a selection signal generation circuit and first and second activation selection circuits. The selection signal generation circuit generates a source selection signal by synchronizing an entry control signal. The first activation selection circuit generates a plurality of first activation selection signals in synchronization with a first edge clock signal. The second activation selection circuit generates a plurality of second activation selection signals in synchronization with a second edge clock signal. The first and second activation selection circuits have a parallel structure.

Abstract: A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship between the control signal and the timing signal.

Abstract: Apparatuses and methods for clock leveling in semiconductor memory are disclosed. In an example apparatus, a latency control circuit is configured to provide in first and second modes an active first control signal having a timing based on latency information and a system clock. A clock leveling control circuit is configured to provide in the first mode an active second control signal responsive to an active first control signal at a clock transition of a first clock and further configured to provide in the second mode clock leveling feedback responsive to the active first control signal at a transition of a second clock. A read clock circuit is configured to provide the multiphase clocks responsive to the active second control signal. A serializer circuit configured to serialize the data based on the multiphase clocks from the read clock circuit to provide the data in series.

Abstract: This application relates to a data protection system and protection method of a display apparatus, and the system comprises a memory, a TCON, and a switcher. The switcher selectively outputs a constant potential signal and a read/write control signal to a memory according to a potential change of a control signal. When the switcher transmits and outputs the constant potential signal to the memory, the switcher disconnects an electrical coupling between the read/write control signal and a protection control end. The memory maintains timing control data to be write-protected according to the obtained signal, or switches the timing control data to be readable-and-writable or write-protected.

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.

Abstract: In some examples, a memory device may include an internal synchronization circuit that provides for double data rate operation of the memory device when external single data rate signals are provided to the memory device. The external signals may be command and/or address signals provided by an external testing circuits in some examples. The internal synchronization circuit may latch and/or delay at least some of the external signals such that different external commands are provided at the rising and falling edges of the clock signal of the memory device. The memory device may latch the external signals at both the rising and falling edges of the clock signal for double data rate operation of the memory device.

Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

Abstract: A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically.

Abstract: A method includes receiving a first and a second data from a first and second IO pad on a first and second data lines respectively. A data strobe is received from a third IO pad on a data strobe line. The first data and the second data are strobed based on the data strobe to generate a first and second strobed data. The first data from the first IO is received at the data strobe line and strobed based on the data strobe to form an another first strobed data and compared to the first strobed data to generate a comparison signal indicating whether adjustment to a delay of the first data line is needed. A delay command is generated to increase/decrease the delay of the first and second data line.

Abstract: A semiconductor device includes an internal clock generation circuit configured to generate first to fourth internal clocks from first and third divided clocks and a ground voltage in first and second modes. The semiconductor device also includes a data processing circuit configured to latch first to fourth internal data according to first to fourth input control signals. The data processing circuit is additionally configured to generate first to fourth output data by determining the output priority of the latched first and third internal data and the latched second and fourth internal data according to the first to fourth internal clocks, first to fourth rising output control signals, and first to fourth falling output control signals.

Abstract: A semiconductor storage device includes a first chip and a second chip. In response to a first command that is received on a first terminal of the first chip and a second terminal of the second chip that are connected to a command signal line, the first chip and the second chip execute in parallel a first correction process of correcting a duty cycle of a first output signal generated by the first chip and a second correction process of correcting a duty cycle of a second output signal generated by the second chip, respectively, according a common toggle signal.