Abstract: A vital-signs patch for a patient monitoring system that includes a housing containing a sensor that makes physiological measurements of a patient, a transmitter, a receiver, a memory, and a processor. The processor periodically takes a measurement from the sensor, converts the measurement to a data record, and stores the data record in the memory. Upon receipt of a signal from another device, the processor retrieves at least a portion of the data record, converts the retrieved portion of the data record to a vital-sign signal, and causes the transmitter to transmit the vital-sign signal to the other device.

Abstract: Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed.

Abstract: An improved multi-port register file system and method of operating. The multi-port register file memory system comprises: n single memory bit cells each storing a data value and having a single bit cell write port and a single read port connecting a respective local bit line, wherein corresponding parallel activated single bit cells output a stored data value in parallel at n read port outputs to a respective local bit line of n local bit lines, each single bit cell accessed in parallel according to a decoded read address signal. A receiver device is provided implementing n selection logic devices corresponding to n read ports, each selection logic device receiving each the n local bit line output values from the n single bit cells, and implementing logic based directly on the decoded read address signal to select a respective local bit line output as a global output bit.

Abstract: A Phase-Change Memory (PCM) includes a factory programming interface to receive data changing on both a positive transition and a negative transition of a dual edge clock. A transition detector generated internal clock provides a delayed edge to latch the program data. This dual-edge clock scheme provides a doubling in the data transfer rate.

Abstract: A method for data storage includes providing at least first and second readout schemes for reading storage values from a group of analog memory cells that are connected to respective bit lines. The first readout scheme reads the storage values using a first bit line charging configuration having a first sense time, and the second readout scheme reads the storage values using a second bit line charging configuration having a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout schemes is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout scheme.

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.

Abstract: A dual rail memory operable at a first voltage and a second voltage includes an input circuit, an output circuit and a clock generator circuit coupled with the input circuit. The input circuit is operable to receive at least a first input signal referenced to the first voltage and to generate a second input signal referenced to the second voltage. The output circuit is operable to receive at least a first output signal referenced to the second voltage and to generate a second output signal referenced to the first voltage. The clock generator circuit is operable to receive a first clock signal referenced to the first voltage and to generate a second clock signal referenced to the second voltage, a logic state of the second clock signal being a function of a logic state of the first clock signal.

Abstract: A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array storing setup data and reference data, and first and second latch units respectively configured to store the setup data and the reference data sensed from the memory cell array upon a power-up of the memory system. The controller is configured to control a sensing operation of the nonvolatile memory. An operating environment of the nonvolatile memory is determined by the setup data stored in the first latch unit, and the controller controls the nonvolatile memory to re-store the setup data of the memory cell array in the first latch unit when the reference data of the second latch unit is changed.

Abstract: An apparatus comprising a first line driver, a second line driver, a charge pump, and a control logic circuit coupled to the first line driver and the second line driver and configured to disable the charge pump when both a first control signal associated with the first line driver and a second control signal associated with the second line driver indicate a charge pump disable state. A network component comprising at least one processor configured to implement a method comprising receiving a first control signal and a second control signal, disabling a charge pump when both the first control signal and the second control signal indicate a charge pump disable state, and operating the charge pump to boost a voltage when the first control signal, the second control signal, or both indicate a charge pump active state.

Abstract: A method for calibration of a memory controller may include determining if an unused memory location exists in memory. The method may include writing a first pattern to the unused memory location in response to a determination that the unused memory location exists. The method may include determining if a second pattern exists in the memory in response to a determination that the unused memory location does not exist. The method may include iteratively modifying a first delay of a first delay control module among a plurality of delay values. The method may include reading from a memory location including the first pattern or the second pattern for each iteration of modification of the first delay. The method may include modifying one or more second delays, each second delay associated with one of one or more second delay control modules, based on the results of reading from the memory location.

Abstract: A device and method to perform memory operations at a clock domain crossing is disclosed. In a particular embodiment, a method includes providing a first clock signal to a write clock input of a memory to write data to the memory. The data is read from the memory according to a second clock signal that is different from the first clock signal. A third clock signal is provided to a read clock input of the memory. The third clock signal has a frequency that is substantially an integer multiple of a frequency of the second clock signal. The integer multiple is greater than one.

Abstract: A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.

Abstract: Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed.

Abstract: In a conventional DRAM, errors in reading data are likely to occur when the capacitance of a capacitor is reduced. A plurality of cells is connected to one main bit line Each cell includes a sub bit line and 2 to 32 memory cells. Further, each cell includes a selection transistor and a reading transistor, and a sub bit line is connected to a gate of the reading transistor. Since the parasitic capacitance of the sub bit line is sufficiently small, data of electric charge of a capacitor of each memory cell can be amplified without an error in the reading transistor and output to the main bit line.

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

Abstract: An interleaved memory circuit includes a memory bank including at least one first memory cell for storing a charge representative of a first datum, the first memory cell being coupled with a first word line and a first bit line. The interleaved memory circuit further includes a local control circuit coupled with the memory bank. The interleaved memory circuit further includes a global control circuit coupled with the local control circuit, an interleaving access including a clock signal having a first cycle and a second cycle for accessing the first memory cell, where the second cycle is capable of enabling the local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.

Abstract: A test mode control circuit is provided to strictly allow entry into a test mode or prevent a boot failure from occurring during a boot operation for a built-in parallel bit test. The test mode control circuit includes a latch, a real entry signal detector, an entry determinator, and a mode control signal generator. When a real entry signal is detected, the entry signal determinator generates an entry determination signal and a test mode control signal is obtained from the mode control signal generator.

Abstract: A semiconductor memory apparatus may comprise: an input buffer block configured to receive a write signal and a reference level signal, compare a the write signal with a the reference level signal to generate a first write control signal, and delay the first write control signal by a predetermined time to generate a second write control signal; a first decoder block configured to combine the second write control signal inputted from the input buffer block with externally inputted command signals, and generate a first write command signal; a clock control block configured to generate a clock control signal for determining determine a level of an internal clock signal in response to a level of the first write control signal outputted from the input buffer block; and a write signal control block configured to generate an internal write command signal according to a level of the first write command signal inputted from the first decoder block and the clock control signal inputted from the clock control block.

Abstract: A semiconductor apparatus includes a plurality of stacked chips. At least two of the chips are configured to receive a column command and generate a column control signal based on the column command. Generation timing of the column control signal generated based on a column command in one of the at least two chips substantially coincide with the generation timing in the other of the at least two of the plurality of chips.

Abstract: A semiconductor memory which is capable of performing data reading without a faulty operation irrespective of the span of an address skew period. In detecting whether an address transition has been made and precharging a bit line formed in a memory cell array when a certain delay period has elapsed after the address transition is detected, the delay period is adjusted based on a delay period extension signal.

Abstract: A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal.

Abstract: A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.

Abstract: A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.

Abstract: A method of implementing voltage level shifting for a memory device includes coupling one or more evaluation clock signals to a memory address decode circuit, the one or more evaluation clock signals operating at a first voltage supply level; and coupling a restore clock signal to the memory address decode circuit, the restore clock signal operating at a second voltage supply level that is higher than the first voltage supply level; wherein one or more outputs of the memory address decode circuit operate at the second voltage supply level.

Abstract: An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation.

Abstract: System and method for generating a sense amplifier enable (“SAE”) signal having a programmable delay with a feedback loop to control the SAE signal duty cycle, which can be used in SRAM or DRAM, or other kinds of memory cells. An illustrative non-limiting embodiment comprises: a programmable clock chopper, a low pass filter, a bias generator, a comparator, and a feedback control module.

Abstract: A semiconductor memory device includes an internal clock generator configured to generate an internal clock signal having a first clock period in response to a chip enable signal and change the first clock period of the internal clock signal in response to a clock control signal, and a controller configured to receive external commands including the chip enable signal and generate the clock control signal corresponding to a first external command other than the chip enable signal. Here, the semiconductor memory device performs a data input/output operation in response to the internal clock signal with the changed clock period.

Abstract: A semiconductor memory device is capable of performing a stable high-speed operation while inputting/outputting data. The semiconductor memory device includes an inversion output circuit configured to output a clocking pattern in a clocking mode, and an inversion pin to which the inversion output circuit is connected.

Abstract: A semiconductor memory device includes data transmission devices for transmit data in synchronization with each other. The semiconductor memory device includes a plurality of data transferring unit, a first control unit, a multiplexing unit, and a second control unit. The plurality of data transferring unit transfers data to a plurality of global lines. The first control unit controls the plurality of data transferring unit in response to a column select signal to select a column of a memory cell. The multiplexing unit multiplexes the data transferred to the plurality of global lines. The second control unit controls the multiplexing unit, wherein the second control unit synchronizes the column select signal with a column address signal having a column address information of the memory cell.

Abstract: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read commands are issued once per burst access eliminating toggling Read control line at cycle frequency. Control line transition terminates access and initializes another burst access.

Abstract: A semiconductor device includes a test circuit that generates a pulse signal from a timing signal. The test circuit outputs the pulse signal and a first set of address signals in response to a first type transition of the timing signal. The test circuit outputs the pulse signal and a second set of address signals in response to a second type transition of the timing signal. The second set of address signals is different from the first set of address signals.

Abstract: A flash memory device includes a plurality of memory blocks and a plurality of block selection circuits corresponding to the plurality of memory blocks. All of the block selection circuits are sequentially operated in response to block control signals, or two or more of the block selection circuits are operated in response to the block control signals.

Abstract: A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period.

Abstract: A circuit configured to change a mode of a plurality of memory devices having a power saving mode includes a command queue configured to hold memory access, and a cancellation unit configured to cancel the power saving mode of target devices of the memory access held up to a predetermined stage of the command queue.

Abstract: A wafer test trigger signal generating circuit of a semiconductor memory apparatus includes an enable timing control unit configured to generate an enable signal by using a plurality of address signals, and a trigger signal generating unit configured to generate a test trigger signal, which designates a decoding timing of a test mode defined by the plurality of address signals, in response to the enable signal.

Abstract: Circuitry for determining timing characteristics, for example, access time, setup time, hold time, recovery time and removal time, of as-manufactured digital circuit elements, such as latches, flip-flops and memory cells. Each element under test is embodied in variable-loop-path ring oscillator circuitry that includes multiple ring-oscillator loop paths, each of which differs from the other(s) in terms of inclusion and exclusion of ones of a data input and a data output of the element under test. Each loop path is caused to oscillate at each of a plurality of frequencies, and data regarding the oscillation frequencies is used to determine one or more timing characteristics of the element under test. The variable-loop-path ring oscillator circuitry can be incorporated into a variety of test systems, including automated testing equipment, and built-in self test structures and can be used in performing model-to-hardware correlation of library cells that include testable as-manufactured digital circuit elements.

Abstract: A semiconductor memory apparatus includes a clock input unit configured to receive a system clock and a data clock, a data clock phase regulation unit configured to regulate a frequency of the data clock, and delay the data clock by a delay varied in accordance with a training information signal, and a clock phase comparison unit configured to compare a phase of an output clock of the data clock phase regulation unit with a phase of the system clock, and generate the training information signal according to a result of the comparison.

Abstract: A data transfer circuit includes: an asynchronous memory to which transfer data is written from a first clock domain with a first clock and from which the written transfer data is read to a second clock domain with a second clock; a scan flip-flop whose input terminal is connected to a first position located on a data path, of the transfer data, from the asynchronous memory to the second clock domain, and whose output terminal is connected to a second position located on a data path, of the transfer data, from the asynchronous memory to the first position; and a clock selector which selects a clock to drive the scan flip-flop from the first clock and the second clock.

Abstract: A semiconductor memory device includes a memory cell array arranged in rows and columns, a row decoder and a control circuit. The row decoder drives word lines connected to the memory cell array by decoding a received row address and being synchronized with an internal clock signal. The control circuit receives a clock signal, a chip select signal and a mode signal, and generates the internal clock signal. The control circuit generates the internal clock signal so that the row decoder does not operate for a predetermined time in response to the chip select signal when the mode signal transitions from a power saving mode to a normal mode.

Abstract: An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory.

Abstract: A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.

Abstract: A nonvolatile ferroelectric memory immediately outputs data stored in a page buffer without performing a cell access operation when a page buffer is accessed. Since a block page address region and a column page address region are arranged in less significant bit region, and a row address region is arranged in more significant bit region, the cell operation is not performed in the access of the page address buffer, thereby improving reliability of the cell and reducing power consumption.

Abstract: A semiconductor integrated circuit has K (K is a natural number of 2 or more) number of memory cells coupled to a same word line, and multiple sense amplifier circuits coupled to the memory cells. The multiple sense amplifier circuits are divided into N (N is a natural number of 2 or more) number of groups. Among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation.

Abstract: A method for adjusting a timing between an internal clock and a command in a gear down mode of a memory device includes detecting a sync pulse at rising and falling edges of the internal clock, and adjusting between the internal clock of the memory device and the command according to the detection result.

Abstract: Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed.

Abstract: A data strobe signal noise prevention apparatus and semiconductor integrated circuit includes a transition protection unit configured to protect a transition of a data strobe signal in response to a control signal and a controller configured to determine when a burst operation completes and to generate the control signal.

Abstract: A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits.

Abstract: A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

Abstract: An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row address (PXID) and/or word enable (WE) signals are configured in response to receipt of self-refresh and refresh counter signals to output different timing and sequencing when in self-refresh mode than when in normal mode of the memory device. Conventionally, ISO signals are controlled from a block selection circuit which also controls bit line equalization (BLEQ) and sense amplifier enable (SAPN). While in conventional circuits the PXID and WE signals are generated in response to the output of the address decoder and thus have a fixed timing in relation to the output of the address decoder. The use of different timing and sequencing can lower power consumption, such as by outputting fewer signal transitions per block during self-refresh.