Abstract: A semiconductor memory device according to the present invention includes a burst counter for sequentially automatically generating an address of a predetermined bit number in synchronism with a clock on the basis of a predetermined sequence in the subsequent operation cycle in accordance with the inputted initial address, and a plurality of memory cell sub-arrays which is formed by dividing a memory cell array. The semiconductor memory device further comprises a plurality of block decoder selection-time adjusting circuits for sequentially outputting a first block selecting signal, which is the base of a signal for selecting each of the memory cell sub-arrays, as a second block selecting signal at a timing corresponding to a read latency and for outputting the first block selecting signal as a third block selecting signal which has a length corresponding to the read latency.

Abstract: A memory controller detects an approaching end of a currently open page for an access operation for a particular data stream. The memory controller, in response to detecting the approaching end of the currently open page and if the particular data stream is of a predetermined type, such as an isochronous data stream, the memory controller speculatively opens a next page in the memory.

Abstract: A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

Abstract: A programmable counter circuit for use in semiconductor memories for generating both sequential and interleave address sequences for block data accesses is disclosed. The output and complementary output of the counter for a previous bit are multiplexed to send the proper carry bit information to the counter for the next bit. In interleave mode, the carry bit forces the row/column counter to count in an interleave address sequence. In sequential mode, the start address of the memory access is captured and held. Either the output or complementary output of the counter for a previous bit is used to control the counter of the next bit based on the captured start address bit. The counter can be programmed to automatically increment the memory address in both a binary and interleave sequence in order to increase the access speed for blocks of sequential data in semiconductor memories.

Abstract: A dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM), having a full-page increment/decrement burst mode. In one embodiment, the DDR SDRAM/SGRAM includes a memory array and a logic circuitry coupled thereto. The memory array is addressable by even and odd word addresses. The logic circuitry has a burst increment mode to access the array starting at an even word address and a burst decrement mode to access the array starting at an odd word address.

Abstract: A clock synchronization semiconductor memory device in which the pre-charging time tRP can be accelerated by the variable delay time for write recovery. There is provided a unit for checking whether or not at least one clock cycle before the inputting of the pre-charge command is that for the write operation, and for holding the checked result. There is also provided a unit for performing switching control at the time of inputting the pre-charge command, responsive to the checked result, as to whether or not a pre-set delay time is to be introduced as from the time of inputting the pre-charge command until word line resetting.

Abstract: A dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM), having a full-page increment/decrement burst mode. In one embodiment, the DDR SDRAM/SGRAM includes a memory array and a logic circuitry coupled thereto. The memory array is addressable by even and odd word addresses. The logic circuitry has a burst increment mode to access the array starting at an even word address and a burst decrement mode to access the array starting at an odd word address.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory includes a clock connection to receive an external clock -signal, a chip select (CS#) connection to receive a chip select signal, a row address strobe (RAS#) connection to receive a row address strobe, a column address strobe (CAS#) connection to receive a column address strobe and a write enable (WE#) connection to receive a write enable signal. Control circuitry is provided to perform a burst read operation of memory cells in a first block of the memory and interrupt the burst read operation when the chip select signal is active, the row address strobe is either inactive or active, the column address strobe is de-active, the write enable signal is active, and the address signals identify the first block simultaneously during the burst read operation.

Abstract: A method for reading data from an integrated electronic memory device including a non-volatile memory matrix includes supplying the memory with an address of a memory location where a reading is to be effected, accessing the memory matrix in a random read mode, supplying the memory with a clock signal and an address acknowledge signal (LAN), detecting a request for burst read mode access, and starting the burst reading as the clock signal shows a rising edge. A related circuit is also provided.

Abstract: A burst length discriminating circuit for use in a synchronous semiconductor memory with a burst mode, which receives the three least significant address signals of an address, includes an inverter receiving the address IA2, a first D-type flipflop or latch for latching and holding the address signal IA0, a second D-latch for latching and holding the address signal IA1, and a third D-latch for latching and holding an output of the inverter. A decoder receives respective outputs of the first to third D-latches for selectively activating a burst length discrimination signal determined by a logical combination of the address signals IA0, IA1 and IA2, and activates an any burst length discrimination signal other than a burst length discrimination signal indicating the full page, when the outputs of all the first to third D-latches are at the high level.

Abstract: In a semiconductor memory system, an SDRAM comprises a memory cell array 101 which is divided into a plurality of cell array blocks, a column decoder, a row decoder, and a sense amplifier circuit. In the SDRAM, a first operation mode with a first cycle time is set when successive access within a cell array block is conducted, a second operation mode with a second cycle time shorter than the first cycle time is set when successive access covering the cell array blocks being apart from each other is conducted and a third operation mode with a medium cycle time is set when successive access covering the cell array blocks adjacent to each other is conducted. With the above constitution, a high speed access can be realized without provision of a specific accessory circuit while suppressing overhead for a semiconductor chip size.

Abstract: A memory device has address, data, and control buses, and a memory-cell array including a number of memory cells arranged in rows and columns, each memory cell operable to store a bit of data. A row address decoder circuit is adapted to receive a row address applied on the address bus and operates to decode the row address and activate a row of memory cells corresponding to the decoded row address. A column address decoder circuit is adapted to receive a column address applied on the address bus and operates to decode the column address and access a plurality of memory cells in the activated row. The data stored in the plurality of memory cells in the activated row is defined as a block of data. A precharge circuit is coupled to the memory-cell array and operates, when activated, to precharge and equilibrate the memory-cell array.

Abstract: A semiconductor memory having burst mode operation includes a memory cell array, a sense amplifier circuit determining data of memory cells, a latch circuit having first and second latch groups and latching data of a sense amplifier, an enable circuit provided with an chip enable signal and controlling readout operation the semiconductor. The enable circuit instructs the circuit for readout operation to activate until the latch circuit latches data even if the chip enable signal indicates stopping the readout operation of semiconductor memory to output data of memory cells correctly.

Abstract: Rapid data transfer and reduction in power consumption can be achieved by reducing the number of row accesses. A pattern of the memory regions to be selected in memory array is changed by word line mode designation of word line mode control circuit. Memory cells in the same row are selected in a line mode, whereas memory cells in different rows are simultaneously selected in a box mode.

Abstract: A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

Abstract: A microcontroller architecture that adds a dedicated bit in the op-code decode field to force data access to take place on a page of the random access memory (RAM) for that instruction. This allows the user to have any page selected and still have direct access to the special function registers or the register variables that are located on a pre-defined page of the RAM. The setting of the dedicated bit will not affect the current operation of the microcontroller nor will the setting of the bit modify the currently selected address stored in a page select register currently being used by the microcontroller.

Abstract: A flash memory (100) includes a core cell array (104), address decoders (116), one or more output buffers (110) and sensing circuitry including sense amplifiers which sense data at an address selected by the address decoders. A data switching multiplexer (108) is coupled to the output buffers to select a sense amplifier for a current word of data in response to a control signal (RWDEN) . A control circuit (106) is coupled to the data switching multiplexer to provide the control signal at a time to ensure the current word of data is provided to the output buffers.

Abstract: A method of using a reduced number of page tag registers to track a state of physical pages in memory systems are is described. An incoming system address request is received that includes a requested bank number and a requested page number. A page register located in memory controller corresponding to the requested bank number is then located and the stored page address included in the located page register is then compared to the requested page address. The requested page in the memory bank corresponding to the requested bank number is then accessed when the stored page address matches the requested page address for the requested memory bank. The stored page using page address from the page register of the bank which number is given by random page register number generator is closed if the requested bank and stored page address do not match. However, a new page using the page address from the incoming system address is opened after which the requested bank is accessed.

Abstract: There is disclosed a multi-step pulse generating circuit and a method of erasing a flash memory cell using the same, which can shorten the erase time for the flash memory and reduce the size of a device, in a way that it stores the information at the time when the suspense command is input during the multi-step pulse erase operation, switches it into a read mode, and resumes the erase operation from the time when the information is stored.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory includes a clock connection to receive an external clock signal, a chip select (CS#) connection to receive a chip select signal, a row address strobe (RAS#) connection to receive a row address strobe, a column address strobe (CAS#) connection to receive a column address strobe and a write enable (WE#) connection to receive a write enable signal. Control circuitry is provided to perform a burst read operation of memory cells in a first block of the memory and interrupt the burst read operation when the chip select signal is active, the row address strobe is either inactive or active, the column address strobe is de-active, the write enable signal is active, and the address signals identify the first block simultaneously during the burst read operation.

Abstract: A nonvolatile memory increases the number of times that data can be written and the length of time that data can be stored through use of architectural and addressing features. A principal feature lies in setting as a high reliability region a specific memory sector (first sector) among a plurality of memory sectors. Within the high reliability sector, two or more memory cells are written with the same data. During reading, the simultaneously written memory cells are read simultaneously, increasing current flow through the parallel current paths. This nonvolatile memory allows the size of the high reliability sector to be adjusted using signals supplied from external to the nonvolatile memory.

Abstract: In a semiconductor memory system, an SDRAM comprises a memory cell array 101 which is divided into a plurality of cell array blocks, a column decoder, a row decoder, and a sense amplifier circuit. In the SDRAM, a first operation mode with a first cycle time is set when successive access within a cell array block is conducted, a second operation mode with a second cycle time shorter than the first cycle time is set when successive access covering the cell array blocks being apart from each other is conducted, and third operation mode with a medium cycle time is set when successive access covering the cell array blocks adjacent to each other is conducted. With the above constitution, a high speed access can be realized without provision of a specific accessory circuit while suppressing overhead for the semiconductor chip size.

Abstract: A memory device is arranged in such a manner that an access-target memory cell is selected from a plurality of memory cells in accordance with the level of the byte-enable signal at the timing when the level of the corresponding row address strobe signal (/RAS signal) changes, and by this arrangement, the problem resided in the conventional memory device that it could not be decided as to whether a memory block in the DRAM core was to be a selected or non-selected byte until the fall of the corresponding column address strobe signal (/CAS signal), and thus the column decoder and the preamplifier that start operating at the fall of the /RAS signal could not be efficiently controlled is solved, and due to this, electric power that might otherwise be consumed at the time of executing a byte-unit access to the wide-bus DRAM can be reduced.

Abstract: One embodiment of the invention is a method for decoding a memory access address. A portion of the memory access address is compared to a plurality of boundary values, each of the plurality of boundary values representing an uppermost address for a group of memory devices, each of the memory devices in the group having the same configuration. A group number is generated that represents an addressed group that contains an addressed memory device that contains the memory access address. A device number is generated that represents the location of the addressed memory device within the addressed group. A device selection signal is generated responsive to the group number and the device number.

Abstract: A dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM), having a full-page increment/decrement burst mode. In one embodiment, the DDR SDRAM/SGRAM includes a memory array and a logic circuitry coupled thereto. The memory array is addressable by even and odd word addresses. The logic circuitry has a burst increment mode to access the array starting at an even word address and a burst decrement mode to access the array starting at an odd word address.

Abstract: According to a method of a reassign block processing time determination test of the present invention, for a hard disk drive being tested, reassign block processing is performed for a data block corresponding to a designated logical block address, and the time required for that reassign block processing is computed. When the reassign block processing time exceeds a prescribed time, the reassign block processing time is determined to be abnormal. It therefore becomes possible to detect a hard disk drive wherein the reassign block processing time exceeds the time allowed by a RAID system before configuring the RAID system, and thus to avoid fatal problems in operating the RAID system before they occur.

Abstract: The present invention comprises an efficient system and method for writing specific bytes in a wide-word configured memory. A memory controller is configured to write from a wide-word databus to specific bytes in a wide-word addressed memory. The memory controller uses wide-word memory addresses which possess resolution capable of addressing specific bytes, and, in addition, data mask bytes which inhibit data write operations to those bytes in a wide-word which are not intended to be written in a given memory write operation. In one embodiment of the present invention, data mask bytes are created by shifting predetermined bit patterns to the right by an amount calculated by arithmetically combining bits in the wide-word memory address. A flexible individual address generating scheme allows memory write operations which do not depend upon the memory write operation's data boundaries being evenly aligned with the boundaries of wide-words.

Abstract: A method and apparatus for outputting data stored in a non-volatile memory device. The non-volatile memory device includes a non-volatile memory array, an address input for receiving an address indicating a plurality of data values stored in the non-volatile memory array, a sense amplifier circuit to amplify the indicated plurality of data values, a multiplexer to receive the indicated plurality of data values, a clock input for receiving a clock signal and a data selector. The data selector generates a sequence of select signals in response to respective transitions of the clock signal. Each select signal of the sequence of select signals is asserted to the multiplexer to enable the multiplexer to output a respective one of the plurality of data values.

Abstract: A synchronous memory (30), comprising a row address circuit (48,50) latches a row address signal in response to a system clock signal and a binary select signal. The row address circuit produces at least one row select signal. A column address circuit (49,51-54) latches an initial column address signal in response to the system clock signal and the binary select signal. The column address circuit produces a plurality of column select signals in synchronization with the system clock signal. A memory array (75) is arranged in rows and columns of memory cells. Each memory cell stores a respective data bit. The memory array simultaneously produces an integral multiple of M data bits in response to the row select signal and the plurality of column select signals. An output circuit (OMUX) is coupled to receive the system clock signal and the integral multiple of M data bits.

Abstract: A programmable counter circuit for use in semiconductor memories for generating both sequential and interleave address sequences for block data accesses is disclosed. The output and complementary output of a burst counter circuit are multiplexed to send the proper carry bit information to the row/column counter of a memory device. In interleave mode, the carry bit is forced to match that of the burst counter, thus forcing the row/column counter of the memory device to count in an interleave address sequence. In sequential mode, the start address of the memory access is captured and held. Either the output or complementary output of the burst counter is used to control the column counter based on the captured start address bit. The counter can be programmed to automatically increment the memory address in both a binary and interleave sequence in order to increase the access speed for blocks of sequential data in semiconductor memories.

Abstract: A method for testing decoding circuits in a memory including a matrix of storage cells includes writing the same first word in all the storage cells, and then writing second words in the matrix such that each row and each column has at least one stored second word. The second words are different from the first words. If several second words are written in the same row or in the same column, then the second words are different from one another. Reading all the words in the memory permits verification of the integrity of the decoding circuits, and reduces the testing time of the memory.

Abstract: A memory access control technique includes receiving a memory access request indication, performing a memory access operation in accordance with the memory access request (the memory access operation directed to a page of memory), determining a characteristic of a memory access requestor based on the memory access request indication, and executing a paging policy based on the determined characteristic. Requestor characteristics may include the requestor specifying a paging policy, identification of the particular requestor, and identification of the type of requestor. The paging policy may be to maintain the accessed page of memory in an open state, or to close the accessed page following completion of the memory access operation.

Abstract: A semiconductor memory device precharges IO lines of the device rapidly at a write interrupt in normal and full page modes. The device includes a write interrupt detector, a precharge signal generator, and a precharge circuit. The write interrupt detector detects whether signals indicating a write interrupt in the normal mode are from the outside, and then generates a write interrupt detection signal. The precharge signal generator generates first and second precharge signals in response to the write interrupt detection signal, and the precharge circuit precharges IO lines at both sides of a memory cell array of the device before a read or write operation in the normal mode in response to the first and second precharge signals. Since the address access time of the semiconductor memory device is short, a high-speed semiconductor memory device can be implemented using the present invention.

Abstract: A microcontroller architecture that adds a dedicated bit in the op-code decode field to force data access to take place on a page of the random access memory (RAM) for that instruction. This allows the user to have any page selected and still have direct access to the special function registers or the register variables that are located on a pre-defined page of the RAM. The setting of the dedicated bit will not affect the current operation of the microcontroller nor will the setting of the bit modify the currently selected address stored in a page select register currently being used by the microcontroller.

Abstract: A memory access control technique includes receiving a memory access request indication, performing a memory access operation in accordance with the memory access request (the memory access operation directed to a page of memory), determining a characteristic of a memory access requester based on the memory access request indication, and executing a paging policy based on the determined characteristic. Requestor characteristics may include the requester specifying a paging policy, identification of the particular requester, and identification of the type of requester. The paging policy may be to maintain the accessed page of memory in an open state, or to close the accessed page following completion of the memory access operation.

Abstract: A semiconductor memory device includes a memory cell array, a plurality of word lines selectively activated by a row address signal from the outside, a plurality of bit lines selected by a column address signal from the outside, and sense amplifiers connected to the bit lines. The device further includes a row address latch circuit for latching the row address signal by using, as a trigger, a first edge of a clock signal from the outside, a sense amplifier activating circuit for activating the sense amplifier after a lapse of a given time from the first edge, a column address latch circuit for latching a column address signal by using, as a trigger, a second edge of the clock signal occurring after the first edge, and a precharge signal generating circuit for generating a precharge signal for precharging the bit lines after a lapse of a given time from the second edge.

Abstract: There is disclosed a test circuit for a flash memory device and method thereof, which comprises a byte program means for performing a byte program according to a byte program enable signal and a cell address signal and outputting the last address signal of a sector, a program fail signal and an address signal of the fail cell; a chip erase means for performing a chip erase operation according to an erase enable signal and said sector address signal and for outputting an erase fail signal and an address signal of a fail sector; a sector address increment means for increasing a sector address according to said sector address signal and outputting the last sector address signal; a first means for generating a test signal according to the test enable signal, said last sector address signal, a test erase enable signal, said program fail signal and said erase fail signal; a second means for generating a test program enable signal or a test erase enable signal according to the last sector address signal and the test

Abstract: A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.