Format Or Disposition Of Elements Patents (Class 365/51)
  • Patent number: 11366772
    Abstract: Separate inter-die connectors for data and error correction information and related systems, methods, and devices are disclosed. An apparatus includes a master die, a target die including data storage elements, inter-die data connectors, and inter-die error correction connectors. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct data between the master die and the target die. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are separate from the inter-die data connectors. The inter-die error correction connectors are configured to conduct error correction information corresponding to the data between the master die and the target die.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Vijayakrishna J. Vankayala
  • Patent number: 11321511
    Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: May 3, 2022
    Assignee: SiFive, Inc.
    Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra
  • Patent number: 11315917
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for testing the resistance of through silicon vias (TSVs) which may be used, for example, to couple multiple memory dies of a semiconductor memory device. A force amplifier may selectively provide a known current along a mesh wiring structure and through the TSV to be tested. The force amplifier may be positioned on a vacant area of the memory device, while the mesh wiring structure may be positioned in an area beneath the TSVs of the layers of the device. A chopper instrumentation amplifier may be selectively coupled to the TSV to be tested to amplify a voltage across the TSV generated by the current passing through the TSV. The chopper instrumentation amplifier may be capable of determining small resistance values of the TSV.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Akira Ide
  • Patent number: 11302701
    Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Yu Huang, Chien-Yuan Chen, Hau-Tai Shieh
  • Patent number: 11302383
    Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: April 12, 2022
    Assignees: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.
    Inventors: Chao-Chun Lu, Bor-Doou Rong, Chun Shiah
  • Patent number: 11296066
    Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: April 5, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Hwa Yun, Pan-Suk Kwak, Chan-Ho Kim, Bong-Soon Lim
  • Patent number: 11282895
    Abstract: Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars may be divided to form first and second pillars.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Fabio Pellizzer, Lorenzo Fratin
  • Patent number: 11276472
    Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: March 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Hun Kwak
  • Patent number: 11270742
    Abstract: A memory apparatus includes an internal circuit configured to output a plurality of output signals, a signal conversion circuit configured to convert a control signal to generate a selection signal, and a selection circuit configured to output one of the plurality of output signals based on the selection signal. The memory apparatus also includes a buffer configured to buffer output of the selection circuit and output the buffered output to a pad.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Suk Hwan Choi
  • Patent number: 11264088
    Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide a first power voltage via a conductive line for the plurality of first memory cells, and to provide a second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells via the conductive line and for corresponding memory cells of the plurality of second memory cells. A circuit structure of the power circuit is different from a circuit structure of the header circuit.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Cheng Wu, Chih-Yu Lin, Kao-Cheng Lin, Wei-Min Chan, Yen-Huei Chen
  • Patent number: 11264068
    Abstract: Apparatuses for providing a clock signal for a semiconductor device are described. An example apparatus includes a chip including a first clock tree and a second clock tree. The first clock tree includes a first wiring segment extending in a first direction and a second wiring segment extending in a second direction perpendicular to the first direction and coupled the first wiring segment. The second clock tree includes a third wiring segment extending in the second direction, a fourth wiring segment extending in the first direction and coupled to the third wiring segment, and a fifth wiring segment extending in the second direction and coupled to the fourth wiring segment.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ryosuke Yatsushiro, Seiji Narui
  • Patent number: 11264377
    Abstract: A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Scott E. Sills
  • Patent number: 11250901
    Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: February 15, 2022
    Assignee: Rambus Inc.
    Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
  • Patent number: 11244888
    Abstract: Disclosed herein is an apparatus that includes a memory cell array, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Naohisa Nishioka, Seiji Narui
  • Patent number: 11244708
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: February 8, 2022
    Assignee: Kioxia Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Patent number: 11239240
    Abstract: A semiconductor device comprises semiconductive pillars; digit lines laterally between the semiconductive pillars; nitride caps vertically overlying the digit lines; nitride structures overlying surfaces of the nitride caps; redistribution material structures comprising upper portions overlying upper surfaces of the nitride caps and the nitride structures, and lower portions overlying upper surfaces of the semiconductive pillars; a low-K dielectric material laterally between the digit lines and the semiconductive pillars; air gaps laterally between the low-K dielectric material and the semiconductive pillars, and having upper boundaries below the upper surfaces of the nitride caps; and a nitride dielectric material laterally between the air gaps and the semiconductive pillars. Memory devices, electronic systems, and method of forming a semiconductor device are also described.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Arzum F. Simsek-Ege, Guangjun Yang, Kuo-Chen Wang, Mohd Kamran Akhtar, Katsumi Koge
  • Patent number: 11233681
    Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: January 25, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Timothy M. Hollis, Markus Balb, Ralf Ebert
  • Patent number: 11227648
    Abstract: Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: January 18, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Patent number: 11222710
    Abstract: A method includes determining, for a plurality of memory dice, a signal reliability characteristic and ranking the plurality of memory dice based, at least in part, on the determined reliability characteristics. The method can further include arranging the plurality of memory dice to form a memory device based, at least in part, on the ranking.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mikai Chen, Zhenming Zhou, Zhenlei Shen, Murong Lang
  • Patent number: 11217308
    Abstract: The present disclosure includes apparatuses and methods for programming memory cells using asymmetric current pulses. An embodiment includes a memory having a plurality of self-selecting memory cells, and circuitry configured to program a self-selecting memory cell of the memory by applying a first current pulse or a second current pulse to the self-selecting memory cell, wherein the first current pulse is applied for a longer amount of time than the second current pulse and the first current pulse has a lower amplitude than the second current pulse.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: January 4, 2022
    Assignee: Micron Technology
    Inventors: Mattia Robustelli, Innocenzo Tortorelli, Richard K. Dodge
  • Patent number: 11217314
    Abstract: A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: January 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Hun Kwak
  • Patent number: 11195830
    Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory level comprising memory elements, a control logic level vertically adjacent and in electrical communication with the memory level and comprising control logic devices configured to effectuate a portion of control operations for the memory level, and an additional control logic level vertically adjacent and in electrical communication with the memory level and comprising additional control logic devices configured to effectuate an additional portion of the control operations for the memory level. A memory device, a method of operating a semiconductor device, and an electronic system are also described.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: December 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Kurt D. Beigel
  • Patent number: 11195836
    Abstract: A semiconductor memory device includes a stack structure having a plurality of layers vertically stacked on a substrate, each layer including, a first bit line and a gate line extending in a first direction, a first semiconductor pattern extending in a second direction between the first bit line and the gate line, the second direction intersecting the first direction, and a second semiconductor pattern adjacent to the gate line across a first gate insulating layer, the second semiconductor pattern extending in the first direction, a first word line adjacent to the first semiconductor pattern and vertically extending in a third direction from the substrate, a second bit line connected to an end of the second semiconductor pattern and vertically extending in the third direction from the substrate, and a second word line connected to another end of the second semiconductor pattern and vertically extending in the third direction.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hui-Jung Kim, Min Hee Cho, Junsoo Kim, Taehyun An, Dongsoo Woo, Yoosang Hwang
  • Patent number: 11182284
    Abstract: A memory module comprises a volatile memory subsystem, a non-volatile memory subsystem, and a module control device. The module control device is configured to read data from the non-volatile memory subsystem in response to a set of signals received from the memory channel indicating a non-volatile memory access request to transfer the data from the non-volatile memory subsystem to the volatile memory subsystem, and to provide at least a portion of the data to the volatile memory subsystem in response to receiving a dummy write memory command including a memory address related to the non-volatile memory access request via the memory channel. The volatile memory subsystem is further configured to receive the dummy write memory command and to receive the at least a portion of the first data in response to the dummy write memory command.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: November 23, 2021
    Assignee: Netlist, Inc.
    Inventor: Hyun Lee
  • Patent number: 11177008
    Abstract: A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: November 16, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Kensuke Yamamoto, Fumiya Watanabe, Shouichi Ozaki
  • Patent number: 11171142
    Abstract: An embodiment may include an integrated circuit. The integrated circuit may include a plurality of vertical transistor structures arranged in a two-dimensional grid pattern including a longitudinal set of grid-lines, a transversal set of grid-lines, and nodes at each intersection of the longitudinal set of grid-lines and the transversal set of grid-lines. Each vertical transistor structure is arranged substantially perpendicular to the plurality of layers of the integrated circuit and aligned with each node of the two-dimensional grid pattern.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
  • Patent number: 11164879
    Abstract: An embodiment may include a method of forming a microelectronic device. The method may include forming a pair of transistors stacked vertically and connected in series, each of the pair of transistors are of the same type. The method may include forming a memory element including a first inverter containing a first inverter transistor and an access transistor. The first inverter transistor is connected to a power supply rail. The access transistor is connected to a bitline. The first inverter transistor is a first transistor of the pair of vertically stacked transistors and the access transistor is a second transistor of the pair of vertically stacked transistors. The pair of transistors are arranged substantially perpendicular to the plurality of layers.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
  • Patent number: 11139002
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H. S. Tang
  • Patent number: 11133063
    Abstract: Aspects of the invention include performing a stochastic update for a crossbar array by generating a set of stochastic pulses for a crossbar array, the crossbar array including a plurality of row wires and a plurality of column wires, the plurality of row wires including a first row wire and the plurality of column wires including a first column wire, wherein a three terminal device is coupled to the first row wire and the first column wire at a crosspoint of the first row wire and the first column wire, and wherein a resistivity of the three terminal device is modified responsive to a coincidence of pulses from the set of stochastic pulses at the crosspoint of the first row and the first column, and wherein at least one terminal in the three terminal device is floating.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: September 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Seyoung Kim, Oguzhan Murat Onen, Tayfun Gokmen
  • Patent number: 11121246
    Abstract: A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level and to the first level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: September 14, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventor: Zvi Or-Bach
  • Patent number: 11107803
    Abstract: A method to construct a 3D system, the method including: providing a base wafer; and then transferring a memory control on top; and then thinning the memory control, transferring a first memory wafer on top; and then thinning the first memory wafer; and then transferring a second memory wafer on top; and then thinning the second memory wafer. A 3D device, the device including: a first stratum including first bit-cell memory arrays; a second stratum including second bit-cell memory arrays; and a third stratum, where the second stratum overlays the first stratum, where the first stratum overlays the third stratum, where the third stratum includes a plurality of word-line decoders to control the first bit-cell memory arrays and the second bit-cell memory arrays.
    Type: Grant
    Filed: March 28, 2021
    Date of Patent: August 31, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Patent number: 11094674
    Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level, mechanically resulting in the die pair having a minimum warpage. An electronic component may be bonded to an exposed surface of one of the semiconductor dies.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: August 17, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Nagesh Vodrahalli, Shrikar Bhagath, Rama Shukla
  • Patent number: 11087827
    Abstract: An edge memory array mat with access lines that are split in half, and a bank of sense amplifiers formed in a region that separates the access line segment halves extending perpendicular to the access line segments. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes digit line (DL) jumpers or another structure configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yuan He
  • Patent number: 11083078
    Abstract: An electronic assembly is provided, including a wiring board, a control element, and a pair of first internal electrical connectors. The wiring board includes a mounting surface, an outer patterned conductive layer, a plurality of inner patterned conductive layers, a plurality of near conductive holes, a plurality of far conductive holes, and a first conductive path. The outer patterned conductive layer is located between the mounting surface and the inner patterned conductive layers. The control element is mounted on the mounting surface of the wiring board. The pair of first internal electrical connectors are mounted on the mounting surface of the wiring board, and are adapted for mounting a pair of memory modules.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: August 3, 2021
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Yu-Chieh Wei, Yen-Chen Chen, Yu-Ching Hung
  • Patent number: 11024634
    Abstract: A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Huang, Hong-Chen Cheng, Cheng Hung Lee, Hung-Jen Liao
  • Patent number: 11024385
    Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module includes a first semiconductor die comprising first non-volatile memory cells, a second semiconductor die comprising second non-volatile memory cells, and a third semiconductor die comprising control circuitry. The first, the second and the third semiconductor die are bonded together. The control circuitry is configured to control memory operations in the first memory cells in parallel with the second memory cells.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 1, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Patent number: 11016894
    Abstract: Techniques and apparatus to manage cache coherency for different types of cache memory are described. In one embodiment, an apparatus may include at least one processor, at least one cache memory, and logic, at least a portion comprised in hardware, the logic to receive a memory operation request associated with the at least one cache memory, determine a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status, perform the memory operation request via a small cache coherence process responsive to the cache status being a small cache status, and perform the memory operation request via a giant cache coherence process responsive to the cache status being a small cache status. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: May 25, 2021
    Assignee: INTEL CORPORATION
    Inventors: Rajesh Sankaran, Ishwar Agarwal, Stephen Van Doren
  • Patent number: 11017852
    Abstract: A method of forming a memory device includes: forming a polish stop layer over a metallization layer in an inter-metal dielectric layer; performing an etching process to form an opening in the polish stop layer, in which a sidewall of the opening extends at an acute angle relative to a top surface of the polish stop layer; forming an electrode material in the opening and over the polish stop layer; planarizing the electrode material until a top surface of the polish stop layer is exposed so as to form a bottom electrode surrounded by the polish stop layer; and forming a stack of a resistance switching layer and a top electrode over the bottom electrode.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chi Tu, Chu-Jie Huang, Sheng-Hung Shih, Nai-Chao Su, Wen-Ting Chu
  • Patent number: 11018130
    Abstract: An integrated circuit (IC) die is provided, which includes a die body; electrostatic discharge (ESD) circuitry formed in the die body; contact pads exposed on an active side of the die body; a first conductive tower formed in the die body and electrically coupling a first contact pad to the ESD circuitry. The first conductive tower comprises first, second, third, and fourth segments formed from metal layers of the die body; a first via electrically coupling the first segment to the second segment; a second via electrically coupling the first segment to the third segment; a third via electrically coupling the second segment to the fourth segment; and a fourth via electrically coupling the third segment to the fourth segment, the second segment electrically parallel with the third segment. The IC die further comprises at least a first data line disposed between the first, second, third, and fourth segments.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 25, 2021
    Assignee: XILINX, INC.
    Inventor: Mohammed Fakhruddin
  • Patent number: 11011580
    Abstract: According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 18, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Kenichi Murooka
  • Patent number: 10991675
    Abstract: A method to construct a 3D system, the method including: providing a base wafer; and then transferring a first memory wafer on top of the base wafer; and then thinning the first memory wafer; and then transferring a second memory wafer on top of the first memory wafer; and then thinning the second memory wafer; and transferring a memory control on top of the second memory wafer; and then thinning the memory control, where the first memory wafer includes a cut-layer, and where the thinning of the first memory wafer includes using the cut-layer to control the thickness of the first memory wafer.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: April 27, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Patent number: 10991700
    Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Song Guo, Sanh D. Tang, Vlad Temchenko, Shivani Srivastava
  • Patent number: 10978460
    Abstract: Semiconductor structures are provided. A semiconductor structure includes a memory cell and a logic cell. The memory cell includes a latch circuit formed by two cross-coupled inverters, and a pass-gate transistor coupling an output of the latch circuit to a bit line. A first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact. The logic cell includes a transistor. A second source/drain region of the transistor is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact. The first and second vias are the same height. The interconnect line and the bit line are formed in the same metal layer, and the bit line is thicker than the interconnect line.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10964389
    Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Chien-Chen Lin
  • Patent number: 10964807
    Abstract: A 3D semiconductor device including: a first level including a single crystal layer, a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the single crystal layer and includes interconnects between the first transistors forming control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; and polysilicon pillars, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the third transistors, where at least one of the second memory cells is at least partially atop of the control circuits.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: March 30, 2021
    Assignee: Monolithic 3D Inc.
    Inventor: Zvi Or-Bach
  • Patent number: 10950277
    Abstract: An integrated circuit including a signal line layout is disclosed. A signal line layout may include a number of signal lines configured for conveying a number of signals. The signal line layout may further include a number of shield lines. Each signal line of the number of signal lines may be positioned adjacent a first shield line and a second shield line of the number of the shield lines. Further, first shield line may extend a length of an adjacent signal line and the second shield line may extend less than a length of the adjacent signal line. An electronic system including circuitry having one or more signal line layouts, and methods of forming signal line layout are also described.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Nobehara, Takamitsu Onda
  • Patent number: 10943622
    Abstract: An example apparatus includes: a control chip; a plurality of memory chips stacked on the control chip, the plurality of memory chips including first and second memory chips; and a plurality of via conductors connected between the plurality of memory chips and the control chip. Each of the first and second memory chips is divided into a plurality of channels including a first channel. The plurality of via conductors include a first via conductor electrically connected between the first channel in the first memory chip and the control chip, and a second via conductor electrically connected between the first channel in the second memory chip and the control chip. The first and second memory chips substantially simultaneously output read data read from the first channel to the first and second via conductors, respectively.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Seiji Narui
  • Patent number: 10923191
    Abstract: A 3D microelectronic device is provided with several superimposed layers of components, with an upper layer including one or several memory cells having a SRAM structure and provided with a rear biasing electrode. The biasing of the rear biasing electrode is modified to switch the memory cells from a ROM operating mode to a SRAM operating mode.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: February 16, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: David Coriat, Adam Makosiej
  • Patent number: 10916274
    Abstract: A power management integrated circuit includes first pads, second pads, a third pad, and a fourth pad that are configured to be connected with an external device, a regulation block that receives first voltages from the first pads, converts the first voltages to second voltages, and outputs the second voltages to the second pads, a communication block that receives a command through the third pad and outputs an internal information request received together with the command responsive to the command, and a logic block that controls an operation of the regulation block, receives the internal information request from the communication block, and outputs internal state information to the fourth pad based on the internal information request.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: February 9, 2021
    Inventors: Jong-Geon Lee, Kyudong Lee, Jinseong Yun
  • Patent number: RE48930
    Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: February 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Kitae Park