Format Or Disposition Of Elements Patents (Class 365/51)
  • Patent number: 10559574
    Abstract: The present invention discloses a three-dimensional vertical read-only memory (3D-OTPV) comprising Schottky diodes. It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string is vertical to the substrate and comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. A plurality of Schottky diodes are formed between the horizontal address lines and the vertical address lines.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: February 11, 2020
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10541022
    Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: January 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Wook Kim, Hyuk-Joon Kwon, Sang-Keun Han, Bok-Yeon Won
  • Patent number: 10529397
    Abstract: Provided herein may be a memory chip, a package device having the memory chip, and a method of operating the package device. The memory chip comprising a plurality of memory blocks each including a plurality of memory cells for storing data; a plurality of input/output pads to which a chip address is inputted; and a plurality of peripheral circuits configured to program the chip address to a selected memory block among the memory blocks.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Jin Yong Seong, Ho Jun Kang, Sang Bin Park
  • Patent number: 10515935
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer; at least one first metal layer above the first single crystal layer; a second metal layer above the first metal layer; a plurality of first transistors atop the second metal layer; a plurality of second transistors atop the second transistors; a plurality of third transistors atop the second transistors; a third metal layer above the plurality of third transistors: a fourth metal layer above the third metal layer; and a second single crystal layer above the fourth metal layer; and a plurality of connecting metal paths from the fourth metal layer to the second metal layer, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error, where the fourth metal layer is providing global power distribution to the device.
    Type: Grant
    Filed: May 12, 2019
    Date of Patent: December 24, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 10504911
    Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Allen McTeer
  • Patent number: 10490274
    Abstract: The semiconductor memory includes a plurality of word lines; and a plurality of columns including a plurality of resistive storage cells corresponding to the plurality of word lines, the plurality of columns being divided into a plurality of pages each having one or more columns; a memory circuit coupled to the semiconductor memory to sense data stored in the resistive storage cells; and a memory control circuit coupled to the semiconductor memory and the memory circuit to control sensing of the stored data by the memory circuit to, in a read operation, sense data of resistive storage cells included in a selected page by continuously active-precharging one or more word lines among the plurality of word lines in a period in which the selected page among the plurality of pages is activated.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventor: Kwang-Myoung Rho
  • Patent number: 10490258
    Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: November 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Kiyoshi Kato, Wataru Uesugi, Takahiko Ishizu
  • Patent number: 10490267
    Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
  • Patent number: 10490562
    Abstract: The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTPV). It comprises horizontal address lines and memory holes there-through, an antifuse layer and vertical address lines in said memory holes. The antifuse layer comprises at least first and second sub-layers with different antifuse materials. The 3D-OTPV comprises no separate diode layer.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: November 26, 2019
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang
  • Patent number: 10482929
    Abstract: Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit's resistance to its respective source line.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: November 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang, Gengming Tao
  • Patent number: 10482060
    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: November 19, 2019
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Arifur Rahman
  • Patent number: 10438665
    Abstract: According to one embodiment, a memory device is connected to one or more information processing devices. The memory device includes a shared memory and a memory controller. The memory controller is configured to analyze an access to the shared memory by the one or more information processing devices and decide on an access method for accessing the shared memory by the one or more information processing devices. The memory controller is configured to give an instruction indicating the decided access method to the one or more information processing devices.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 8, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yusuke Shirota, Tatsunori Kanai, Satoshi Shirai
  • Patent number: 10437766
    Abstract: A data storage device is provided. The data store device includes a first printed circuit board (PCB) comprising a main transmission line formed on at least one surface of the first PCB and/or within the first PCB, a memory controller and a plurality of nonvolatile memory devices. The memory controller is provided on the first PCB. The plurality of nonvolatile memory devices are provided on the first PCB. The plurality of nonvolatile memory devices are connected to the memory controller through a channel and exchange data with the memory controller. The channel includes a data transmission line connecting data pads of the memory controller and the nonvolatile memory devices. The data transmission line comprises the main transmission pattern and an open stub contacting the main transmission pattern. The open stub does not contact any other conductor other than the main transmission pattern.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Woon Park, Sun-Ki Yun, Kwang-Soo Park
  • Patent number: 10424921
    Abstract: A semiconductor die including: a die-to-die interface including an input/output (I/O) circuitry area and an electrical contact area; wherein the electrical contact area includes an array of electrical contacts disposed on a side of the semiconductor die; and wherein the I/O circuitry area includes a plurality of drivers, each of the drivers coupled to at least one electrical contact in the electrical contact area, and a plurality of electrostatic discharge (ESD) protection devices, each of the ESD protection devices coupled to a respective driver, further wherein the I/O circuitry area and the electrical contact area are separated in a top-down view of the semiconductor die.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: September 24, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Kenneth Dubowski, Luverne Ray Peterson, Thomas Bryan, Stephen Knol, Sreeker Dundigal, Alvin Loke
  • Patent number: 10418372
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source select line. The semiconductor device may include word lines. The semiconductor device may include a channel layer. The semiconductor device may include a source structure. The source structure may be disposed under the source select line. The source structure may be in contact with the channel layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 10403344
    Abstract: Disclosed is a semiconductor device, including a memory cell array including a plurality of memory cells, a read circuit suitable for generating read data corresponding to a read current flowing in a first direction through a selected memory cell of the plurality of memory cells, a reverse read control circuit suitable for generating a reverse read control signal corresponding to the read data, and a reverse current generation circuit suitable for generating a reverse current flowing in a second direction through the selected memory cell in response to the reverse read control signal.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventor: Kyo-Yun Lee
  • Patent number: 10388640
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: August 20, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Patent number: 10388699
    Abstract: A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mu-Hui Park, Wooyeong Cho
  • Patent number: 10388396
    Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: August 20, 2019
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, John Eric Linstadt, Paul William Roukema
  • Patent number: 10373654
    Abstract: A memory device includes a first die configured to: generate a segment set based on a source data, wherein: the source data is information corresponding to a device operation, the source data having a block length representing a number of bits therein, the segment set including at least a first segment and a second segment, the first segment and the second segment having a number of bits less than the block length, and communicate the segment set with the second die; a second die configured to process the segment set according to the device operation; and a set of inter-die connectors electrically coupling the first die and the second die, the inter-die connectors include a number of dedicated Through-Silicon-Vias (TSVs), wherein the number is less than the block length.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Vijayakrishna J. Vankayala, Liang Chen
  • Patent number: 10373932
    Abstract: A stacked semiconductor structure is provided. The stacked semiconductor structure includes a substrate, a first electronic component, a first fillet, and a first redistribution layer. The substrate has a support surface. The substrate includes a first pad disposed on the support surface. The first electronic component is disposed on the support surface and has a first bottom surface, a first top surface, and a first side surface connecting the first bottom surface and the first top surface. The first electronic component includes a second pad disposed on the first top surface. The first fillet is disposed on the support surface and the first side surface and has a first inclined surface. The first redistribution layer is disposed on the support surface, the first top surface, and the first inclined surface and electrically connecting the first pad to the second pad.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: August 6, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10366983
    Abstract: A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Scott E. Sills
  • Patent number: 10360953
    Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 23, 2019
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Yoshinori Matsui
  • Patent number: 10354734
    Abstract: Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Masanobu Saito, Shuji Tanaka, Shinji Sato
  • Patent number: 10331354
    Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hak-Soo Yu, Je-Min Ryu, Reum Oh, Pavan Kumar Kasibhatla, Seok-In Hong
  • Patent number: 10325884
    Abstract: Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and coupled to one another and the logic component, a plurality of memory component programmable delay lines (PDLs), of the plurality of memory component PDLs associated with a respective one of the plurality of memory components, and a logic component programmable delay line (LPDL) coupled to the logic component and each of the plurality of memory component PDLs.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Feng Lin, Yuanzhong Wan
  • Patent number: 10297588
    Abstract: A semiconductor device includes at least one first gate strip, at least one second gate strip, at least one first conductive line and at least one first conductive via. An end surface of the at least one first gate strip and an end surface of the at least one second gate strip are opposite each other. The at least one first conductive line is over the at least one first gate strip and the at least one second gate strip and across the end surface of the at least one first gate strip and the end surface of the at least one second gate strip. The at least one first conductive via connects the at least one first conductive line and the at least one first gate strip.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Cheng Lin, Hui-Ting Yang, Shih-Wei Peng, Jiann-Tyng Tzeng, Charles Chew-Yuen Young, Chih-Ming Lai
  • Patent number: 10297296
    Abstract: A storage device capable of performing power gating is provided. A memory cell of the storage device includes a bistable circuit, a first transistor, a second transistor, and a backup circuit. The first transistor and the second transistor are electrically connected to a first bit line and a second bit line, respectively. A precharge circuit that precharges the first bit line and the second bit line with different voltages is provided. The backup circuit includes a retention node, an input node, an output node, a third transistor, a fourth transistor, and a capacitor. The third transistor controls electrical continuity between the retention node and the input node. A gate of the fourth transistor and a terminal of the capacitor are electrically connected to the retention node. The input node is electrically connected to one of nodes Q and Qb of the bistable circuit, and the output node is electrically connected to the other of the nodes Q and Qb of the bistable circuit.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: May 21, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Kiyoshi Kato
  • Patent number: 10290328
    Abstract: A memory module is operable in a computer system to communicate with a system memory controller via a command/address bus and a data bus. The memory module comprises a register device coupled to the command/address bus, and a plurality of DRAM packages coupled to the data bus and to the register device via a set of module control lines. Each respective DRAM package comprises stacked array dies and a control die. The control die includes data signal conduits and control signal conduits. In response to the memory module receiving a set of command/address signals from the system memory controller, the register device outputs control signals, and the control die configures the data signal conduits in accordance with the control signals to enable respective bits of one or more data signals to be communicated between a selected die among the stacked dies and the system memory controller.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: May 14, 2019
    Assignee: NETLIST, INC.
    Inventor: Hyun Lee
  • Patent number: 10283194
    Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 7, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Yabuuchi, Shinji Tanaka
  • Patent number: 10270030
    Abstract: The present disclosure generally relates to a structure, system, and method for manufacturing an electrical component for a memory device. For example, depositing alternating layers of conductive and insulator materials over an etch stop layer to create a vertical stack, etching a trench through the vertical stack to expose the etch stop layer, electroplating the conductive layers using a plating material based on a desired electrical behavior, and forming a connection between the plating materials for each of the conductive layers.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: April 23, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Christian R. Bonhôte, Jeffrey Lille
  • Patent number: 10255986
    Abstract: The present invention provides a computer implemented method, system, and computer program product of assessing in-field reliability of computer memories. In an embodiment, the present invention includes taking control of a portion of a computer memory circuit, utilizing a portion of a computer memory bus associated with the portion of the computer memory circuit, moving computer memory circuit data stored in the portion of the computer memory circuit to a host computer storage device, executing a set of logical operations assessing reliability of the portion of the computer memory circuit, resulting in assessment data stored in a reliability error monitor (REM) computer storage device, transmitting the stored assessment data from the REM computer storage device to a computer memory controller circuit, and in response to the transmitting, moving the moved computer memory circuit data from the host computer storage device back to the portion of the computer memory circuit.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Kyu-hyoun Kim, Anil B. Lingambudi, Adam J. McPadden
  • Patent number: 10231341
    Abstract: A packaged module for use in a wireless communication device has a substrate supporting an integrated circuit die that includes at least a microprocessor and radio frequency receiver circuitry and a stacked filter assembly configured as a filter circuit that is in communication with the radio frequency receiver circuitry. The stacked filter assembly includes a plurality of passive components, where each passive component is packaged as a surface mount device. At least one passive component is in direct communication with the substrate and at least another passive component is supported above the substrate by the at least one passive component that is in the direct communication with the substrate.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: March 12, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Darren Roger Frenette, George Khoury, Leslie Paul Wallis, Lori Ann DeOrio
  • Patent number: 10223011
    Abstract: A storage device includes a nonvolatile memory device and a controller configured to generate a read command according to a request of an external host device and transmit the read command to the nonvolatile memory device. The nonvolatile memory device is configured to perform a read operation in response to the read command, to output read data to the controller, and to store information of the read operation in an internal register.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: March 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyejin Yim, Jinyub Lee, Kyung-Hwa Kang, Minseok Kim, Minsu Kim, Sung-Won Yun
  • Patent number: 10211150
    Abstract: A memory structure is provided. The memory structure comprises M array regions and N contact regions. M is an integer ?2. N is an integer ?M. Each array region is coupled to at least one contact region. Each contact region comprises a stair structure and a plurality of contacts. The stair structure comprises alternately stacked conductive layers and insulating layers. Each contact is connected to one conductive layer of the stair structure. Two array regions which are adjacent to each other are spatially separated by two contact regions, which are coupled to the two array regions, respectively.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: February 19, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 10192613
    Abstract: In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: January 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Yamaki
  • Patent number: 10163759
    Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yu Lin, Kao-Cheng Lin, Li-Wen Wang, Yen-Huei Chen
  • Patent number: 10153029
    Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Hun Kwak, Hee-Woong Kang, Jun-Ho Seo, Hee-Won Lee
  • Patent number: 10153196
    Abstract: Some embodiments include a memory array having a first set of lines extending along a first direction, and a second set of lines over the first set of lines and extending along a second direction. Lines of the second set cross lines of the first set at cross-point locations. Memory structures are within the cross-point locations. Each memory structure includes a top electrode material, a bottom electrode material and a programmable material. Rails of insulative material extend parallel to the lines of the second set and alternate with the lines of the second set along the first direction. The programmable material has first regions within the memory structures and second regions over the rails of insulative material. A planarized surface extends across the lines of the second set and across the second regions of the programmable material. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Sills
  • Patent number: 10134471
    Abstract: Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Kumar K. Chinnaswamy, Randy B. Osborne, Erik W. Peter
  • Patent number: 10133625
    Abstract: A storage device may include a primary storage array comprising a plurality of memory devices, one or more parity memory devices, and a controller configured to store a block of data. The controller may be configured to store the block of data by at least: writing the block of data to the primary storage array, determining parity data for the block of data, and writing at least a portion of the determined parity data to the one or more parity memory devices.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: November 20, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zvonimir Z. Bandic, Robert E. Mateescu, Seung-Hwan Song
  • Patent number: 10128316
    Abstract: This semiconductor memory device includes: global first wiring lines; global second wiring lines; and memory blocks connected to the global first wiring lines and the global second wiring lines. The memory block includes: local first wiring lines; local second wiring lines; and memory cells connected to the local first wiring lines and the local second wiring lines. The memory cell includes: a variable resistance element; first electrodes disposed on a first surface of the variable resistance element; and second electrodes arranged on a second surface of the variable resistance element. The first electrodes are connected to the local first wiring lines, and the second electrodes are connected to the local second wiring lines.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: November 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chika Tanaka, Masumi Saitoh
  • Patent number: 10127974
    Abstract: Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Joong Kim, Ho-young Song, Hoi-ju Chung, Ju-yun Jung, Sang-uhn Cha
  • Patent number: 10115451
    Abstract: A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: October 30, 2018
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Neal Berger, Yuniarto Widjaja
  • Patent number: 10084126
    Abstract: According to one embodiment, a magnetic memory device includes first and second magnetic members, and a conductive member. The first magnetic member includes first, second, and third extending portions. The first extending portion extends along a first direction. The second extending portion extends along a second direction. The third extending portion includes a third connection portion connected with the first and second extending portions. The third extending portion extends along a third direction. The conductive member extends along a fourth direction. The first and second directions are inclined with respect to the fourth direction. The conductive member includes a portion overlapping at least parts of the first and second extending portions in a fifth direction. The fifth direction crosses the first, the second and the fourth directions. The conductive member includes a metal. A direction from the third extending portion toward the second magnetic member crosses the third direction.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: September 25, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Michael Arnaud Quinsat, Takuya Shimada, Tsuyoshi Kondo
  • Patent number: 10083722
    Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: September 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Reum Oh, Je-Min Ryu, Pavan Kumar Kasibhatla
  • Patent number: 10079489
    Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: September 18, 2018
    Assignee: Intel Corporation
    Inventors: Guido Droege, Andre Schaefer, Uwe Zillmann
  • Patent number: 10074605
    Abstract: Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10049711
    Abstract: According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: August 14, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keisuke Nakatsuka, Tadashi Miyakawa, Katsuhiko Hoya, Takeshi Hamamoto, Hiroyuki Takenaka
  • Patent number: 10043815
    Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: August 7, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mikiko Mori, Ryota Suzuki, Tatsuya Kato, Wataru Sakamoto, Fumie Kikushima