Abstract: A semiconductor memory device, includes, a cell array including a plurality of memory banks, a command decoder configured to decode a read/write command, a read command, and a write command that are input from outside of the semiconductor memory device, an address decoder receiving a read address and a write address, an input receiver configured to transmit write data input through a write data pad to a global input/output driver of a memory bank corresponding to the write address, and an output driver configured to transmit read data output from an input/output sense amplifier of a memory bank corresponding to the read address to a read data pad, wherein the write data is input via the write data pad in a single data rate method and transmitted to the global input/output driver without deserialization processing, and the read data is transmitted from the input/output sense amplifier to the read data pad without serialization processing.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: This invention discloses sustainable DRAM with principle power supply voltage which is unified with an external logic circuit. The DRAM circuit is configured to couple with the external logic circuit and with a principle power supply voltage source. The DRAM circuit comprises a first sustaining voltage generator and a DRAM core circuit. The first sustaining voltage generator generates a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM circuit. The DRAM core circuit has a DRAM cell comprising an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator. Wherein, a voltage level of the principle power supply voltage source to the DRAM circuit is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit.

Abstract: A static random-access memory (SRAM) circuit includes an SRAM bitcell coupled to a word line, a bit line and a complementary bit line. A precharge circuit is coupled to the bit line and the complementary bit line and includes a precharge input. A first keeper transistor is coupled to the bit line and a second keeper transistor is coupled to the complementary bit line. A write driver circuit includes a select input receiving a select signal, a write data input, and a write data compliment input, and is operable to write a data bit to the SRAM bitcell. A combinatorial logic circuit provides a precharge signal to the precharge circuit based on the select signal and a bit line precharge signal.

Abstract: A semiconductor device includes a memory cell including a write transistor and a read transistor that are electrically connected to each other. The write transistor includes a write bit line disposed over a substrate, a write channel structure disposed on the write bit line and extending in a direction perpendicular to a surface of the substrate on the write bit line, a write gate dielectric layer disposed on a side surface of the write channel structure, and a write word line disposed on the write gate dielectric layer. The read transistor includes a read gate electrode layer disposed on the write channel structure, a read gate dielectric layer disposed on the read gate electrode layer, a read channel layer disposed on the read gate dielectric layer, and a read word line and a read bit line that are disposed at opposite ends of the read channel layer.

Abstract: A semiconductor device is provided. The semiconductor device includes: first, second and third active patterns on a logic cell region of a substrate and are spaced apart from each other in a first direction; first and second gate electrodes, the first gate electrode crossing the first active pattern and the second gate electrode crossing the second active pattern; a first separation pattern provided between the first and second active patterns; a second separation pattern provided between the second and third active patterns; a first gate insulating layer interposed between the first gate electrode and the first active pattern; and a first gate cutting pattern interposed between the first and second gate electrodes, and in contact with a top surface of the first separation pattern.

Abstract: A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.

Abstract: The disclosure provides a convolution operation accelerator and a convolution operation method and belongs to the field of microelectronic devices. Input data of each word line may be subjected to a multiply-accumulate operation together with two upper and lower layers of convolution kernel units, so that natural sliding of the convolution kernel units in a y direction in two-dimensional input is achieved. The oblique bit lines and multiple copies of a convolution kernel in each layer of a non-volatile memory array may enable a multiplication operation between one piece of input data and convolution kernel data at different positions in the same convolution kernel. In this way, the natural sliding of the convolution kernel units in an x direction in the two-dimensional input is achieved.

Abstract: An OTP memory cell includes an antifuse transistor, a first transistor and a second transistor. The antifuse transistor includes a first fin, a second fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. A central region of the first fin and a central region of the second fin are covered by a first gate structure. The first drain/source contact layer is electrically connected with a first terminal of the first fin and a first terminal of the second fin. The second drain/source contact layer is electrically connected with a second terminal of the second fin but not electrically connected with a second terminal of the first fin. The first transistor is connected with the first drain/source contact layer. The second transistor is connected with the second drain/source contact layer.

Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

Abstract: A power electronics module for a test arrangement for testing a power electronics controller includes: supply connections for supplying energy; at least one load connection for providing at least one electrical connection variable; a supply circuit for providing electrical control voltages; a selection circuit with circuit breakers for switching one of the electrical control voltages onto the at least one load connection of the power electronics module; and an interface for controlling the circuit breakers. The supply connections of the power electronics module are AC supply connections. The supply circuit is a multi-phase circuit for providing a plurality of phase voltages on a plurality of phase conductors. The selection circuit connects a phase conductor to the at least one load connection of the power electronics module.

Abstract: A method includes: coupling a first gate to a first word line through a first gate via, wherein the first gate extends along a first direction; coupling the first gate to a second word line through a second gate via, wherein each of the first gate, a second gate, the first gate via and the second gate via is disposed on a first active area which extends along the second direction, wherein the second gate extends along the first direction and is separated from the first gate along a second direction; coupling the first active area to a first bit line through a first conductive via; and aligning the first gate via, the second gate via and the a first conductive via with each other along the second direction.

Abstract: A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

Abstract: In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets. The off-module buffer controller receives control signals transmitted by the memory control component and re-drives/re-transmits the control signals to the memory sockets. The off-module buffer controller generates buffer-control signals in response to the control signals and outputs the buffer-control signals to the off-module data buffers to multiplex host-control-component access to the memory sockets.

Abstract: Methods, systems, and devices for techniques for operating a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.

Abstract: A volatile memory device having a reduced area may include; a row decoder extending in a first direction, a column decoder extending in a second direction, a cell region between the row decoder and the column decoder and including a first sense amplifier and a first bit line connected to the first sense amplifier, and a first peripheral circuit region spaced apart from the cell region in the first direction and including includes a first complementary bit line connected to the first sense amplifier. The first sense amplifier may be configured to perform a read/write operation in relation to a first memory cell connected to the first bit line using the first complementary bit line.

Abstract: Methods, systems, and devices for memory device with a split pillar architecture are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars and cell material may be divided to form a first and second storage components and first and second pillars.

Abstract: The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.

Abstract: A semiconductor structure includes a substrate and first and second SRAM cells. The first SRAM cell includes first and second pull-up transistors, first and second pull-down transistors, and first and second pass-gate transistors. The first and the second pass-gate transistors have a first channel width. The first and the second pull-down transistors have a second channel width. A ratio of the second channel width to the first channel width is in a range of 1.05 to 1.5. The second SRAM cell includes third and fourth pull-up transistors, third and fourth pull-down transistors, and third and fourth pass-gate transistors. The third and the fourth pass-gate transistors have a third channel width. The third and the fourth pull-down transistors have a fourth channel width. The third and the fourth channel widths are substantially same. The fourth channel width is larger than the second channel width. The transistors are GAA transistors.

Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.

Abstract: A local amplifying circuit, a data readout method and a memory are provided. The local amplifying circuit includes: write control transistors, configured to connect a global data line to a local data line based on a write enable signal; column selection transistors, configured to connect a bit line to the local data line based on a column selection signal; a first control NMOS transistor, having a gate connected to the local data line, one of a source and a drain being connected to the global data line and the other being connected to a corresponding read control transistor; a second control NMOS transistor, having a gate connected to a complementary local data line, one of a source and a drain being connected to a complementary global data line and the other being connected to a corresponding read control transistor.

Abstract: According to one embodiment, a semiconductor memory device includes: a stacked structure including a plurality of first layers stacked with a second layer therebetween above a substrate having a memory region in which a plurality of memory cells are arranged and an outer edge portion surrounding the memory region, the stacked structure having a stepped portion at which ends of the first layers form a stepped shape at an end of the stacked structure in a first direction within the memory region, wherein at least some of the first layers among the plurality of first layers extend, along a second direction perpendicular to the first direction, from above the outer edge portion at a first end side of the substrate through above the memory region over the substrate to above the outer edge portion at a second end side of the substrate.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

Abstract: An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.

Abstract: A memory device including a memory bank array which includes a first edge memory block, a second edge memory block, and a plurality of memory blocks placed between the first edge memory block and the second edge memory block; a plurality of sense amplifiers between the plurality of memory blocks, and that connect a first bit line of a memory block on one side of each of the plurality of sense amplifiers and a first complementary bit line of a memory block on an other side of each of the plurality of sense amplifiers; a first edge sense amplifier connected to a second bit line and a second complementary bit line of the first edge memory block; and a second edge sense amplifier connected to a third bit line and a third complementary bit line of the second edge memory block.

Abstract: A SEDRAM-based stacked Cache system is integrated in multiple layers of wafers bonded together and includes a Cache, a Cache controller and a SEDRAM controller; the multiple layers of wafers includes a SEDRAM wafer structure and a processor wafer structure; a SEDRAM unit is integrated in each layer of SEDRAM wafer in the SEDRAM wafer structure and configured as a storage space of the Cache; a CPU, the Cache controller, the SEDRAM controller and a memory controller are integrated in the processor wafer structure.

Abstract: A memory structure and a system-on chip (SOC) device are provided. A memory structure according to the present disclosure includes a first static random access memory (SRAM) macro comprising first gate-all-around (GAA) transistors and a second SRAM macro comprising second GAA transistors. The first GAA transistors of the first SRAM macro each includes a first plurality of channel regions each having a first channel width (W1) and a first channel thickness (T1). The second GAA transistors of the second SRAM macro each comprises a second plurality of channel regions each having a second channel width (W2) and a second channel thickness (T2). W2/T2 is greater than W1/T1.

Abstract: A memory device is provided. The memory device includes at least one memory chip and a logic chip. Each of the at least one memory chip includes a memory array, a plurality of bit lines, and a plurality of data paths. The data paths respectively correspond to the bit lines. The number of the data paths is equal to or less than the number of the bit lines. A plurality of data transmission ports of the logic chip are electrically connected to the data paths of the at least one memory chip in a one-to-one manner. The number of the data transmission ports is equal to a sum of the data paths of the at least one memory chip.

Abstract: A storage device having multiple storage dies is disclosed. The storage device comprises: a printed circuit board having a main surface, a plurality of universal input/output pins, placed on the main surface of the printed circuit board, and a plurality of random access storage dies, corresponding to the plurality of universal input/output pins, placed on the plurality of universal input/output pins.

Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.

Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

Abstract: A method for fabricating a vertical memory device includes: forming a memory cell array that includes a vertical thyristor and a word line over a first substrate; forming a peripheral circuit unit in a second substrate; bonding the memory cell array with the peripheral circuit unit; removing the first substrate to expose one side of the vertical thyristor; and forming a bit line that is coupled to the one side of the vertical thyristor and the peripheral circuit unit.

Abstract: Methods, systems, and devices for external power functionality techniques for memory devices are described. A memory system, which may be coupled to a first power source associated with a first voltage, may detect whether a second power source associated with a second voltage higher than the first voltage is available. The memory device may activate a functionality to use the second power source for the access operations if the second power source is available, and the memory device may then perform one or more access operations using the second voltage from the second power source based on the activated functionality.

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

Abstract: The present disclosure relates to a memory device based on a ferroelectric capacitor, which includes a control unit for writing data into a memory cell or reading data from the memory cell and a plurality of memory cells arranged in an array; each memory cell includes an external interface, a first switch, a transistor, a first capacitor and a second capacitor, wherein at least one of the first capacitor and the second capacitor is a ferroelectric capacitor; the first switch has a first port connected with a first word line, a second port connected with a bit line, and a third port connected with one end of the first capacitor; and the transistor has a gate electrode connected with another end of the first capacitor and one end of the second capacitor, a source electrode connected with a first read terminal, and a drain electrode connected with a second read terminal, wherein another end of the second capacitor is connected with a second word line.

Abstract: To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j-lth sub memory cell.

Abstract: A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays and in-die peripheral-circuit components thereof, whereas the second die comprises processing circuits and off-die peripheral-circuit components of the 3D-M arrays. The first and second dice are communicatively coupled by a plurality of inter-die connections.

Abstract: Methods, systems, and devices for dynamic power distribution for stacked memory are described. A stacked memory device may include switching components that support dynamic coupling between a shared power source of the memory device and circuitry associated with operating memory arrays of respective memory dies. In some examples, such techniques include coupling a power source with array circuitry based on an access activity or a degree of access activity for the array circuitry. In some examples, such techniques include isolating a power source from array circuitry based on a lack of access activity or a degree of access activity for the array circuitry. The dynamic coupling or isolation may be supported by various signaling of the memory device, such as signaling between memory dies, signaling between a memory die and a central controller, or signaling between the memory device and a host device.

Abstract: An operation method of a semiconductor device is disclosed. The semiconductor device includes separate first and second dies in a package and receives first types of signals through first and second respective channels independent of each other and corresponding to the first and second respective dies. The method includes a step in which when information for controlling internal operations of the first and second dies is first applied to the first die through a first pad, the first die performs the internal operation and also transmits the information to the second die through an internal interface connecting the first die and the second die, and a step in which when the information is transmitted to the second die, the second die performs the internal operation.

Abstract: SRAM arrays are provided. A SRAM array includes a plurality of SRAM cells and a plurality of well strap cells. Each of the SRAM cells arranged in the same column of the cell array includes a first transistor formed in a first P-type well region of a substrate, a second transistor formed in an N-type well region of the substrate, and a third transistor formed in a second P-type well region of the substrate. Each well strap cell is arranged on one of the columns in the cell array and includes a first P-well strap structure formed on the first P-type well region, a second P-well strap structure formed on the second P-type well region, and an N-well strap structure formed on the N-type well region. The first and second P-well strap structures and the N-well strap structure are separated from the SRAM cells by a dummy area.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first set of memory cells and a first selector are formed within a first group of metal layers and inter-level dielectric (ILD) layers above the substrate. A second set of memory cells and a second selector are formed within a second group of metal layers and ILD layers above the first group of metal layers and ILD layers. The first selector is coupled to the first set of memory cells to select one or more memory cells of the first set of memory cells based on a first control signal. In addition, the second selector is coupled to the second set of memory cells to select one or more memory cells of the second set of memory cells based on a second control signal. Other embodiments may be described and/or claimed.

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

Abstract: A memory device includes a multi-layer stack. The multi-layer stack is disposed on a substrate and includes a plurality of first conductive lines and a plurality of dielectric layers stacked alternately, wherein each of the plurality of first conductive lines has a first side and a second side opposite to the first side. The memory device further includes a plurality of second conductive lines crossing over the plurality of first conductive lines, wherein widths of the plurality of second conductive lines are increased as the plurality of second conductive lines become far away from the first side.

Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array, execute the query, and send only the particular data to the host upon executing the query.

Abstract: A semiconductor device may include a memory bank, an X-decoder adjacent to the memory bank in a row direction, a Y-decoder adjacent to the memory bank in a column direction, X-lines extending from the X-decoder across the memory bank in the row direction, Y-lines extending from the Y-decoder across the memory bank in the column direction, and a plurality of connection lines.

Abstract: A structure includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

Abstract: A semiconductor memory device according to an embodiment includes a memory chip and a circuit chip. The memory chip includes first and second joint metals. The circuit chip includes first and second sense amplifiers, and third and fourth joint metals facing the first and second joint metals, respectively. The first sense amplifier includes first and second active regions. The first active region includes a first transistor coupled between the third joint metal and the second active region. The second amplifier includes third and fourth active region. The third active region includes a second transistor coupled between the fourth joint metal and the fourth active region. The third and fourth joint metals overlap the first and third active regions, respectively.

Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

Abstract: A memory device can comprise an array of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers, and a plurality of vertical sense lines coupled to each of the plurality of tiers. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line and configured to electrically couple the respective vertical sense line to a horizontal sense line. The memory device can also comprise a semiconductor under the array (SuA) circuitry, comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.