Abstract: A memory apparatus having at least one memory cell set comprising a first spin torque memory cell electrically connected in series to a second spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The memory cell set itself is configured to switch between a high resistance state and a low resistance state. The memory apparatus also has at least one reference cell set comprising a third spin torque memory cell electrically connected in anti-series to a fourth spin torque memory cell, with each spin torque memory cell configured to switch between a high resistance state and a low resistance state. The reference cell set itself has a reference resistance that is a midpoint of the high resistance state and the low resistance state of the memory cell set.

Abstract: The present invention provides a method for providing magnetic shielding for a circuit comprising magnetically sensitive materials, comprising actively shielding the circuit from a disturbing magnetic field. A corresponding semiconductor device is also provided. The method and device allows shielding for strong disturbing magnetic fields.

Abstract: An inadvertent write can be prevented when a read is performed. The duration of the write current pulse for writing information in the magnetic memory layer is longer than the duration of the read current pulse for reading the information from the magnetic memory layer.

Abstract: Data, stored in MRAM-cells (12) should be protected against misuse or read-out by unauthorised persons. The present invention provides an array (10) of MRAM-cells (12) provided with a security device (14) for destroying data stored in the MRAM-cells (12) when they are tampered with. This is achieved by placing a permanent magnet (16) adjacent the MRAM-array (10) in combination with a soft-magnetic flux-closing layer (18). As long as the soft-magnetic layer (18) is present, the magnetic field lines (20) from the permanent magnet (16) are deviated and flow through this soft-magnetic layer (18). When somebody is tampering with the MRAM-array (10), e.g. by means of reverse engineering, and the flux-closing layer (18) is removed, the flux is no longer deviated and affects the nearby MRAM-array (10), thus destroying the data stored in the MRAM-cells (12).

Abstract: A bistable resistance random access memory comprises a plurality of programmable resistance random access memory cells where each programmable resistance random access memory cell includes multiple memory members for performing multiple bits for each memory cell. The bistable RRAM includes a first resistance random access member connected to a second resistance random access member through interconnect metal liners and metal oxide strips. The first resistance random access member has a first resistance value Ra, which is determined from the thickness of the first resistance random access member based on the deposition of the first resistance random access member. The second resistance random access member has a second resistance value Rb, which is determined from the thickness of the second resistance random access member based on the deposition of the second resistance random access member.

Abstract: A tamper-resistant packaging approach protects an integrated circuit (100) from undesirable access. According to an example embodiment of the present invention, data is encrypted as a function of the state of a plurality of magnetically-responsive circuit elements (130-135) and then decrypted as a function of the state (130-135). A package (106) is arranged to prevent access to the integrated circuit and having magnetic particles (120-125) therein. The magnetic particles (120-125) are arranged to cause the magnetically-responsive circuit elements (130-135) to take on a state that is used to encrypt the data. The state of these elements is again accordingly used to decrypt the data (e.g., as a key). When the magnetic particles are altered, for example, by removing a portion of the package, the state of one or more of the magnetically-responsive circuit elements is changed, thus rendering the state incapable of being used for decrypting the data.

Abstract: Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore, in terms of suppressing occurrence of read disturb, the read current supply duration may be shortened to increase the threshold value of the current causing the magnetization reversal and thereby ensure a sufficient read disturb margin. Therefore, the read current supply duration may be shortened relative to the write current supply duration ensure the read disturb margin and suppress occurrence of read disturb.

Abstract: A write control method for a magnetoresistive random access memory, which includes a memory cell having a recording layer with an axis of easy magnetization and an axis of hard magnetization. The write control method includes writing a datum into the memory cell. The writing of the datum includes applying a pulsative first magnetic field substantially parallel to the axis of easy magnetization of the recording layer and a pulsative second magnetic field substantially parallel to the axis of hard magnetization to the recording layer so as to cause a period of the pulsative first magnetic field and a period of the pulsative second magnetic field to overlap each other, and applying a pulsative third magnetic field having substantially the same direction as the pulsative first magnetic field to the recording layer at least once after applying the pulsative first magnetic field to the recording layer.

Abstract: Methods and apparatus are provided for magnetoresistive random access memory (MRAM) bits (52, 52?) combined with associated drive or sense transistors (53, 141) to form an integrated MRAM array. The MRAM array has lower electrodes (602, 150, 160, 162) of the MRAM bits (52, 52?) formed substantially directly on a source or drain region (56, 142, 152-2) of associated drive or sense transistors (53, 141), so that the intervening vias (302, 34, 36) and underlying interconnects layers (332, 35) of the prior art (20) can be eliminated. An interconnect layer (65) is provided above the MRAM bit (52, 52?) and transistor (53, 141) combination (50, 125, 129, 133) for coupling upper electrodes (41, 164) of the MRAM bits (52, 52?) and other electrodes (601, 58, 152-1, 152-3, 186-1, 186-3) of the transistors (53, 141) to other elements of the array.

Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).

Abstract: A magnetic memory device and methods thereof are provided. The example magnetic memory device may include a transistor disposed within a given unit cell region and a magnetic tunneling junction (MTJ) element connected to the transistor, the MTJ element including an MTJ cell and first and second pad layers forming a magnetic field at first and second ends of the MTJ cell, the transistor including a drain connected to the first pad layer in the given unit cell region and a bit line, a source connected to the second pad layer in an adjacent unit cell region, and a gate connected to a word line corresponding to the given unit cell region.

Abstract: A circuit with an inter-module radiation interference shielding mechanism is disclosed. The circuit includes a circuit module producing a radiation field. At least one radiation shielding module is situated between the circuit module and another module that is vulnerable to the interference of the radiation field. The shielding module is substantially tangential to the radiation field.

Abstract: A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.

Abstract: A data writing method for writing data sequentially in a cross-point memory cell array having a variable resistive element whose electric resistance is changed by application of an electric stress is provided. When data is sequentially written in memory cells in the same row or column, the writing order of the memory cells to be written is determined according to the length from an electric connection point to a selected memory cell to be written and the increase/decrease direction of the electric resistance of each selected memory cell changed by data writing, the electric connection point being between a write voltage applying circuit, which applies a data writing voltage to a same wiring of the selected word line or bit line connected to the selected memory cell, and the same wiring, and the data writing is executed based on the determined writing order.

Abstract: The present invention provides a method for providing magnetic shielding for a circuit comprising magnetically sensitive materials, comprising actively shielding the circuit from a disturbing magnetic field. A corresponding semiconductor device is also provided. The method and device allows shielding for strong disturbing magnetic fields.

Abstract: A method and system for providing a magnetic element are disclosed. The method and system include providing a pinned layer, providing a spacer layer, and providing a free layer. The free layer is ferrimagnetic and includes at least one of a conductive ferrite, a garnet, a ferrimagnetic alloy excluding a rare earth, a heavy rare-earth-transition metal alloy, a half-metallic ferrimagnetic, and a bilayer. The bilayer includes a rare earth-transition metal alloy layer and a spin current enhancement layer. The magnetic element is configured to allow the free layer to be switched due to spin transfer when a write current is passed through the magnetic element.

Abstract: A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The structure for transmission line operation includes a second layer of electrically conductive material on the second layer of insulating material.

Abstract: A phase change memory cell includes a MOS select transistor having a gate coupled to a word line, and a source and drain region coupled between first and second bit lines, respectively. A first phase change element is coupled between the first bit line and the source region of the MOS select transistor. A method of reading a selected cell in the array is provided by evaluating a body effect impact of a state of the phase change element associated with the selected cell on a MOS select transistor.

Abstract: Magnetic shielding is provided using a variety of methods, systems, devices and circuits. Aspects of present invention provide a method for providing magnetic shielding for a circuit comprising magnetically sensitive materials. The circuit is actively shielded from a disturbing magnetic field. A corresponding semiconductor device is also provided. The method and device can provide shielding for strong disturbing magnetic fields.

Abstract: A storage device includes a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from the first threshold voltage, and a circuit element connected in series with the storage element, wherein letting R be a resistance value of the storage element after writing, V be the second threshold voltage, and I be a current that can be passed through the storage element at a time of erasure, R?V/I.

Abstract: A word line driver and decoder for use in a magnetic memory includes a main word line driver and a sub word line driver that cooperate to drive current on a selected one from a number of the magnetic memory's word lines. The main word line driver and sub word line driver employ pull up and pull down transistors that configured to drive current on the selected word line in either a read or write ‘0’ direction or a read or write ‘1’ direction in response to control signals that allow reliable magnetic memory operation. An address decoder selects and activates a multiplexer in the sub word line driver to coordinate the current drive. The main word line driver employs current mirrors, transistor switches, and logic control to prevent direct Vdd to Vss shorting in transitioning from ‘0’ and ‘1’, and read and write data storage operations.

Abstract: Magnetic multilayer structures, such as magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves, having one or more spin diffusion layers to diffuse the electron spins outside the MTJ or spin valve structure to reduce the spin transfer switching current for switching the free layer.

Abstract: A Magnetic Random Access Memory (MRAM), in which very little current flows through MTJ elements and very little voltage is applied across them, the MRAM being provided with sense-amplifiers capable of amplifying the potential difference between their corresponding pairs of bit lines at high speed. This is accomplished by a sense amplifier including CMOS inverters cross-connected or connected in loop, a P-channel MOS transistor for shutting the power off during standby, and N-channel MOS transistors for initializing the output of the sense amplifier during standby. A ground terminal of the inverter is connected to a bit line through a transistor of a bit switch, and a ground terminal of the inverter is connected to a bit line through a transistor of a bit switch.

Abstract: A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The structure for transmission line operation includes a second layer of electrically conductive material on the second layer of insulating material.

Abstract: A magnetic tunnel junction device includes a magnetically programmable free magnetic layer. The free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layers.

Abstract: A magnetoresistance effect element includes a first ferromagnetic layer (1), insulating layer (3) overlying the first ferromagnetic layer, and second ferromagnetic layer (2) overlying the insulating layer. The insulating layer has formed a through hole (A) having an opening width not larger than 20 nm, and the first and second ferromagnetic layers are connected to each other via the through hole.

Abstract: A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines.

Abstract: During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

Abstract: An MRAM device is provided which includes an array of magnetic elements, a plurality of conductive lines configured to set magnetization states of the magnetic elements and circuitry configured to vary current applications along one or more of the conductive lines. In some cases, the MRAM device may additionally or alternatively include circuitry which is configured to terminate an application of current along one or more of the conductive lines before magnetization states of one or more magnetic elements selected for a write operation of the device are changed. In either case, a device is provided which includes an MRAM array and a first storage circuit comprising one or more magnetic elements, wherein the first storage circuit is configured to store parameter settings characterizing operations of the magnetic random access memory array within the magnetic elements. Methods for operating the devices provided herein are contemplated as well.

Abstract: An information storage device is provided. The information storage device may be a magnetic random access memory (MRAM) device including a resistive cross point array of spin dependent tunneling (SDT) junctions or magnetic memory elements, with word lines extending along rows of the SDT junctions and bit lines extending along the columns of the SDT junctions. The present design includes a plurality of heating elements connected in series with associated magnetic memory elements, each heating element comprising a diode. Voltage applied to a magnetic memory element and associated heating element causes reverse current to flow through the diode, thereby producing heat from the diode and heating the magnetic memory element, thereby facilitating the write function of the device.

Abstract: A method, information processing system and computer readable medium for transferring data between applications on a computer is disclosed. The method includes selecting data from a first application and selecting a copy-to command for copying the data selected from the first application. The method further includes selecting a second application as a destination for the data selected. The method further includes selecting a location in the second application for inserting the data selected.

Abstract: MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.

Abstract: A multiple-bit memory cell for use in a magnetic random access memory circuit includes a first adiabatic switching storage element having a first anisotropy axis associated therewith and a second adiabatic switching storage element having a second anisotropy axis associated therewith. The first and second anisotropy axes are oriented at a substantially non-zero angle relative to at least one bit line and at least one word line corresponding to the memory cell. The memory cell is configured such that two quadrants of a write plane not used for writing one of the storage elements can be beneficially utilized to write the other storage element so that there is essentially no loss of write margin in the memory cell.

Abstract: An improved magnetic random access memory (MRAM) has two sets of signal lines where each set is substantially perpendicular to the other, and memory cells located at the intersections of the signal lines. Each memory cell has a magneto-resistant element containing a magnetization layer whose magnetic characteristics change depending on the intensity of the magnetic field applied. A desired magnetic field can be applied to any cell by supplying appropriate write currents to the signal lines intersecting at that cell. The relationship between applied magnetic fields, two different threshold function values, and four different magnetic fields that result at each cell is disclosed. Better performance, namely, improved selectivity and a more stable write operation, results.

Abstract: A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.

Abstract: A multiple-memory-layer magnetic random access memory (MRAM) has multiple memory layers arranged as pairs and stacked on a substrate. The first memory layer in the pair comprises a plurality of rows of memory cells located between electrically conductive access lines, and the second memory layer in the pair is substantially identical to the first memory layer, but is rotated about an axis perpendicular to the substrate so that the access lines and memory cell rows in one memory layer of the pair are orthogonal to their counterpart lines and rows in the other memory layer. The memory cells in each layer are aligned vertically (perpendicular to the substrate) with the memory cells in the other layer, with the vertically aligned memory cells forming memory cell columns that extend perpendicularly from the substrate. Each memory cell column has an electrical switch between the lowermost memory cell and the substrate.

Abstract: A method and system for providing a magnetic memory including magnetic memory cells associated with a word line segment is disclosed. The magnetic memory cell includes a magnetic storage device and an isolation device. The isolation device is coupled to the magnetic tunneling junction and with a combined word line for reading and writing to the magnetic memory cell. The magnetic storage device and the isolation device are configured such that no direct current path to ground exists during the writing to the magnetic memory cell. In one aspect, in a write mode, the combined word line associated with the word line segment and the word line segment are activated. In the read mode, at least a portion of the memory cells associated with the word line segment are selected using the combined word line.

Abstract: Methods and apparatuses are disclosed for retrieving data stored in a magnetic integrated memory. In one embodiment, the method includes applying a perturbing hard-axis magnetic field to a magnetic element in a magnetic integrated memory and detecting a change in an electrical parameter caused by said perturbing hard-axis magnetic field.

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated magnetic memory structures. In one aspect, the present teachings relate to magnetic memory structure fabrication techniques in a high density configuration that includes an efficient means for programming high density magnetic memory structures.

Abstract: The present invention relates to a magnetic ring unit and a magnetic memory device; an object of the invention is to control the direction of rotation of the magnetic flux freely and with high reproducibility in a simple structure without using a thermal process such as pinning; and a magnetic ring unit is formed of a magnetic ring in eccentric ring form where the center of the inner diameter is located at a decentered position relative to the center of the outer diameter.

Abstract: This invention provides a probe based magnetic memory storage device. In a particular embodiment, magnetic memory cells are provided in an array. Each cell provides a magnetic data layer and a conductor. At least one movable probe having a tip characterized by a conductor and a soft reference layer is also provided. In addition, an intermediate layer joined to either the movable probe or each memory cell is provided. The movable probe may be placed in contact with a given memory cell, the probe and cell thereby forming a tunnel junction memory cell with the intermediate layer serving as the tunnel junction. The magnetic field provided by the probe conductor may be combined with a field provided by the cell conductor to produce a switching field to alter the orientation of the data layer. The memory cells may include a material wherein the coercivity is decreased upon an increase in temperature. The probe may also include a heat generator.

Abstract: Device and method for memory cell isolation. The memory cell includes a resistive component, such as a magnetic random access memory (MRAM) cell, and an isolation component, such as a four-layer diode. The memory cell may be included in a memory array. The method includes rapidly applying a forward bias across the isolation element to activate the isolation element.

Abstract: A magnetic storage element and a recording method using the same capable of ensuring correct information recording without causing erroneous writing are proposed. A magnetic storage device having the magnetic storage elements incorporated therein, and being capable of recording information in a stable and correct manner even if the magnetic characteristics vary from the element to element is also proposed. The magnetic storage element comprises a storage layer, magnetic field applying means for applying magnetic field to the storage layer, and a magnetic field shield, disposed between the magnetic field application means and the storage layer, comprising a soft magnetic material, for shielding at least a part of the magnetic field. Recording to the magnetic storage element is made effective by applying a magnetic field to the storage layer while heating the magnetic field shield to thereby allow it to reduce or lose its magnetization.

Abstract: A magnetic tunneling junction (MTJ) memory cell for a magnetic random access memory (MRAM) array is formed as a chain of magnetostatically coupled segments. The segments can be circular, elliptical, lozenge shaped or shaped in other geometrical forms. Unlike the isolated cells of typical MTJ designs which exhibit curling of the magnetization at the cell ends and uncompensated pole structures, the present multi-segmented design, with the segments being magnetostatically coupled, undergoes magnetization switching at controlled nucleation sites by the fanning mode. As a result, the multi-segmented cells of the present invention are not subject to variations in switching fields due to shape irregularities and structural defects.

Abstract: A magnetic memory includes a magnetic substance composed of a disc-shaped first magnetic layer and a ring-shaped second magnetic layer which is formed on the first magnetic layer.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.

Abstract: An MRAM device comprising an array of MRAM elements, with each element having an MRAM bit influenced by a magnetic field from a current flowing through a conductor, also includes a magnetic keeper formed adjacent the conductor to advantageously alter the magnetic field. The magnetic keeper alters the magnetic field by concentrating the field within the keeper thereby reducing the extent in which fringe field exists, thus allowing the MRAM elements to be formed closer to increase the areal density of the MRAM device. Increase in magnetic field flux due to the magnetic keeper allows operation of the MRAM device with lowered power. Soft magnetic materials such as nickel iron, nickel iron cobalt, or cobalt iron may be used to form the magnetic keeper.

Abstract: There is provided a MRAM capable of reading at any timing information of memory cells at different addresses connected to the same bit line. Specifically, a memory cell of an address (AD00) has MOS transistors (Q1, Q2) connected in series and a magnetic tunnel resistive element (MR00), which are disposed between bit lines (BL0a, BL0b). The gate electrodes of the MOS transistors (Q1, Q2) are respectively connected to word lines (WL0a, WL0b). Memory lines (ML0, ML1) are connected in common to a reference voltage source (VR1) via N-channel MOS transistors (Q3, Q31), and are respectively connected to current sources with a switch (S1, S2). The bit lines (BL0a, BL0b, BL1a, BL1b) are respectively connected to inputs of buffers with a switch (B1 to B4), and their outputs are supplied to the corresponding sense amplifier (SA1).

Abstract: A method and system for providing and using a magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory cells and providing at least one magnetic write line coupled with the plurality of magnetic memory cells. Each of the magnetic memory cells includes a magnetic element having a data storage layer. The data storage layer stores data magnetically. The magnetic write line(s) are magnetostatically coupled with at least the data storage layer of the magnetic element of the corresponding magnetic memory cells. Consequently, flux closure is substantially achieved for the data storage layer of each of the plurality of magnetic memory cells.