Abstract: A memory structure and method to fabricate the same is described. The memory structure includes a first memory cell having a first pair of non-volatile portions. The memory structure also includes a second memory cell having a second pair of non-volatile portions. The first and second pairs of non-volatile portions are disposed in an inter-locking arrangement.

Abstract: A tree-structure memory device. A tree-structure memory device comprises a plurality of bit lines formed on a substrate and arranged in at least one plane substantially parallel to a substrate surface and extending substantially in a first direction. A plurality of layers having a plurality of memory cells is arranged in a first array. At least one tree structure corresponds to a plurality of layers and a bit line, and has a trunk portion and at least one branch portion that corresponds to one of the layers. A word-line group includes at least one word line crossing with the branch portion of the tree structure at a first intersection region. A memory cell of the first array is located at the first intersection region in a layer of the layers. The first array of memory cells includes at least one memory cell comprising a phase-change-material layer disposed between the word line and the branch portion of the tree structure at the first intersection region without an intervening current-steering element.

Abstract: A ferroelectric nanostructure formed as a low dimensional nano-scale ferroelectric material having at least one vortex ring of polarization generating an ordered toroid moment switchable between multi-stable states. A stress-free ferroelectric nanodot under open-circuit-like electrical boundary conditions maintains such a vortex structure for their local dipoles when subject to a transverse inhomogeneous static electric field controlling the direction of the macroscopic toroidal moment. Stress is also capable of controlling the vortex's chirality, because of the electromechanical coupling that exists in ferroelectric nanodots.

Abstract: A three-dimensional solid-state memory is formed from a plurality of bit lines, a plurality of layers, a plurality of tree structures and a plurality of plate lines. Bit lines extend in a first direction in a first plane. Each layer includes an array of memory cells, such as ferroelectric or hysteretic-resistor memory cells. Each tree structure corresponds to a bit line, has a trunk portion and at least one branch portion. The trunk portion of each tree structure extends from a corresponding bit line, and each tree structure corresponds to a plurality of layers. Each branch portion corresponds to at least one layer and extends from the trunk portion of a tree structure. Plate lines correspond to at least one layer and overlap the branch portion of each tree structure in at least one row of tree structures at a plurality of intersection regions.

Abstract: The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.

Abstract: According to an embodiment of the invention, systems, apparatus and methods are disclosed for providing bimodal voltage references for use in differential signaling between components or devices. According to an embodiment, a switchable power supply is used to produce at least one of two or more supply voltages based on the value of a selection signal received by the switchable power supply. This selection signal is also used by at least one of the elements to switch between a reference voltage produced by another device and a reference voltage derived from the supply voltage. In certain embodiments, the reference voltage derived from the power supply and the selection via a multiplexing circuit is contained within one of the devices (e.g., a chip), which provides certain design and cost advantages.

Abstract: A disk drive system including a write circuit for controlling current through a magnetic write head includes an H-switch circuit and a charge-pumping circuit. The H-switch circuit controls direction of current through the magnetic write head. The charge-pumping circuit is connected to the H-switch circuit for storing energy during a first state of the H-switch circuit, and delivering energy upon switching from the first state to a second state of the H-switch circuit to accelerate a change in direction of current through the write head.

Abstract: The present invention discloses an interface circuit suitable for a high-speed semiconductor device.

Abstract: A semiconductor memory device is grouped into a plurality of flexible macro chips. Under the circumstances, a clock input first stage circuit is arranged in a first flexible macro chip to supply an internal reference clock signal and a first internal clock signal in response to an external reference clock signal. Further, a group of command input first stage circuits are collectively arranged in a second flexible macro chip different from the first flexible macro chip. In this event, the the first internal clock signal is directly supplied to the command input first stage circuits so as to input a command signal.

Abstract: An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.

Abstract: An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.

Abstract: A random access memory (1) is described in which one address of a row of addresses is activatable. There is also realized a block addressing mode in which all addresses between a selectable first address and a selectable second address are activated. To this end there are provided two address registers (4, 5) and a logic tree structure (8) which consists of modules. At each level of the tree structure a module receives a part of the information from the two address registers in order to determine, possibly co-controlled by information received from a higher level of the tree, whether one or both limit addresses are situated within the address range covered by the module and, if the answer is negative, to determine whether all addresses of this address range must be activated or remain deactivated.