Interconnection Arrangements Patents (Class 365/63)
  • Patent number: 11328758
    Abstract: A magnetic memory and its programming control method and reading method, and a magnetic storage device of the magnetic memory are provided in the present disclosure. The magnetic memory includes a first magnetic tunnel junction memory cell, including a first terminal coupled to a first bit line, and further includes a switch device, including a first terminal coupled to a second terminal of the first magnetic tunnel junction memory cell, and a control terminal connected to a switch control signal. The magnetic memory further includes a second magnetic tunnel junction memory cell, including a first terminal coupled to a second bit line, and a second terminal coupled to a second terminal of the switch device. The magnetic memory further includes a first transistor, a second transistor, and a sensing amplifier.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: May 10, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Dan Ning, Zi Jian Zhao, Tao Wang, Hao Ni
  • Patent number: 11295810
    Abstract: Combinations of resistive change elements and resistive change element arrays thereof are described. Combinational resistive change elements and combinational resistive change element arrays thereof are described. Devices and methods for programming and accessing combinations of resistive change elements are described. Devices and methods for programming and accessing combinational resistive change elements are described.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: April 5, 2022
    Assignee: Nantero, Inc.
    Inventors: Jia Luo, Lee E. Cleveland, Ton Yan Tony Chan
  • Patent number: 11295808
    Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byongmo Moon, Jihye Kim, Je Min Ryu, Beomyong Kil, Sungoh Ahn
  • Patent number: 11270998
    Abstract: Described herein are apparatuses, methods, and systems associated with a memory circuit in a three-dimensional (3D) integrated circuit (IC). A control circuit of the memory circuit may include logic transistors in a logic layer of the 3D IC. The control circuit may further include one or more interconnects (e.g., local or global interconnects) and/or other devices in one or more front-side metal layers of the 3D IC. The memory circuit may further include a memory array in back-side metal layers of the 3D IC. The memory array may be formed in the back-side metal layers that are closest to the logic layer. Other embodiments may be described and claimed.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventor: Yih Wang
  • Patent number: 11270759
    Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell region including first metal pads and a memory cell array; and a peripheral circuit region including a second metal pads and vertically connected to the memory cell region by the first metal pads and the second metal pads directly. The peripheral circuit region includes a row decoder block; a buffer block storing a command and an address received from an external semiconductor chip through the first pads; a page buffer block connected to the memory cell array through bit lines, connected to the third pads through data lines, and exchanging data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block receiving control signals from the external semiconductor chip through the second pads, and controlling the row decoder block and the page buffer block.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chanho Kim, Daeseok Byeon, Hyunsurk Ryu
  • Patent number: 11264084
    Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell array; a row decoder block; a buffer block that stores a command and an address received from an external semiconductor chip through the first pads and provides the address to the row decoder block; a page buffer block that is connected to the memory cell array through bit lines, is connected to the third pads through data lines, and exchanges data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block that receives the command from the buffer block, receives control signals from the external semiconductor chip through the second pads, and controls the row decoder block and the page buffer block based on the received command and the received control signals.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: March 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chanho Kim, Daeseok Byeon, Hyunsurk Ryu
  • Patent number: 11232829
    Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: January 25, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Toby D. Robbs, Charles L. Ingalls
  • Patent number: 11227639
    Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 18, 2022
    Assignee: Rambus Inc.
    Inventor: Thomas Vogelsang
  • Patent number: 11222848
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Zhiguo Qian, Jianyong Xie
  • Patent number: 11222831
    Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: January 11, 2022
    Inventors: Jung Ho Do, Seungyoung Lee
  • Patent number: 11211106
    Abstract: A device includes a first reference storage unit, a second reference storage unit, a first reference switch, and a second reference switch. The first reference switch includes a first terminal coupled to a first reference bit line, a second terminal coupled to the first reference storage unit, and a control terminal coupled a reference word line. The second reference switch includes a first terminal coupled to a second reference bit line, a second terminal coupled to the second reference storage unit, and a control terminal coupled the reference word line. The first reference storage unit is configured to receive a bit data through the first reference switch, and to generate a first signal having a first logic state.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Fu Lee, Yu-Der Chih, Hon-Jarn Lin, Yi-Chun Shih
  • Patent number: 11189630
    Abstract: A memory device and an electronic device including the same are provided. The memory device includes a first memory cell disposed at an intersection of first and second conductive lines that extend in first and second directions, respectively, a second memory cell spaced apart from the first memory cell by a first distance in the first direction, a third memory cell spaced apart from the first memory cell by a second distance in the second direction, a first insulating pattern disposed between the first memory cell and the second memory cell, and a second insulating pattern disposed between the first memory cell and the third memory cell. The second insulating pattern has a lower thermal conductivity than the first insulating pattern.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Gun Kang, Hyun Seok Kang, Deok Lae Ahn, Jae Geun Oh, Won Ki Joo, Su-Jin Chae
  • Patent number: 11176970
    Abstract: Semiconductor devices and systems are disclosed. A semiconductor device includes a redistribution layer including a first polygonal structure for conveying a first power signal and including a first cutout region. The semiconductor device further includes a second polygonal structure for conveying a second power signal. Further, the semiconductor device includes an island polygon for conveying a third power signal and positioned within the first cutout region, wherein the island polygon does not touch the first polygonal structure.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Takayori Hamada, Yasuhiko Tanuma
  • Patent number: 11170827
    Abstract: There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Jin Ha Hwang
  • Patent number: 11164849
    Abstract: Embodiments provide a chip assembly and a chip. The chip assembly includes a substrate, a first chip and a second chip stacked on an upper surface of the substrate, and the first chip is arranged above the second chip. At edges of first sides of the first chip and the second chip there is provided with a first pad pair, and at edges of second sides of the first chip and the second chip there is provided with a second pad pair. The second pad pair is arranged between two adjacent functional units at an outermost side of the edge of the second side of the first chip or the second chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent functional units.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: November 2, 2021
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kai Tian, Hongwen Li
  • Patent number: 11144241
    Abstract: A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Liang Chen
  • Patent number: 11133057
    Abstract: An integrated circuit structure includes an SRAM array including a first sub-array having a first plurality of rows and a plurality of columns of SRAM cells, and a second sub-array having a second plurality of rows and the plurality of columns of SRAM cells. A first bit-line and a first complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in a column in the first sub-array. A second bit-line and a second complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in the column in the second sub-array. The first bit-line and the first complementary bit-line are disconnected from the second bit-line and the second complementary bit-line. A sense amplifier circuit is electrically coupled to, and configured to sense, the first bit-line, the first complementary bit-line, the second bit-line, and the second complementary bit-line.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11114175
    Abstract: A Read Only Memory (ROM) cell array includes: a first transistor coupled to a first word line; a second transistor coupled to a second word line; and a third transistor disposed between the first transistor and the second transistor, the third transistor having a first gate terminal permanently coupled to a power rail.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: September 7, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Paramjeet Singh, Bipin Duggal
  • Patent number: 11095556
    Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 17, 2021
    Assignee: INTEL CORPORATION
    Inventors: Debendra Das Sharma, Michelle C. Jen, Mark S. Myers, Don Soltis, Ramacharan Sundararaman, Stephen R. Van Doren, Mahesh Wagh
  • Patent number: 11094382
    Abstract: A semiconductor memory device includes a plurality of page buffers defined in active regions of a substrate; and a plurality of wiring lines disposed over the page buffers, and coupled to the page buffers through contacts. The plurality of wiring lines may include contact portions which are coupled with the contacts, respectively. The plurality of wiring lines may be configured into a bent shape such that the contact portions are offset toward center lines of the active regions.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung Lae Oh, Dong Hyuk Kim, Tae Sung Park, Soo Nam Jung
  • Patent number: 11081151
    Abstract: Examples may include techniques to improve a read operation to a memory array. Examples include identifying characteristics of memory cells in the memory array such as relative positions of memory cells within the memory array and then set multiple read reference voltages or currents to detect a memory state of memory cells based on identified characteristics.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventor: Davide Mantegazza
  • Patent number: 11082043
    Abstract: A memory device comprising: a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to operation cycle different to another access unit whose form factor is different to that of the access unit.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 3, 2021
    Assignee: SK hynix Inc.
    Inventors: Won Ha Choi, Oung Sic Cho, Jong Hoon Oh
  • Patent number: 11054992
    Abstract: A memory system may include a controller; and a plurality of memory modules, wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common, wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips coupled to the buffer chip, wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Kyung Whan Kim
  • Patent number: 11049872
    Abstract: A a semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternatively stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact ping CP1 which extends in the second area in the first direction and is connected to the logic circuit.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 29, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Nojima, Kojiro Shimizu
  • Patent number: 11031779
    Abstract: A memory system includes a non-volatile memory block, a random bit block, and a sense amplifier. The non-volatile memory block includes a plurality of non-volatile memory cells for storing a plurality of bits of data. Each of the non-volatile memory cells includes a first storage transistor. The random bit block includes a plurality of random bit cells for providing a plurality of random bits. Each of the random bit cells includes a second storage transistor and a third storage transistor. The sense amplifier senses a first read current of a non-volatile memory cell during a read operation of the non-volatile memory cell and senses a second read current of a random bit cell during a read operation of the random bit cell. The first storage transistor, the second storage transistor, and the third storage transistor are storage transistors of the same type.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 8, 2021
    Assignee: eMemory Technology Inc.
    Inventor: Wein-Town Sun
  • Patent number: 11024579
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of gate structures extending in a first direction over a substrate between a plurality of source/drain regions. A lower power rail is formed extending in a second direction perpendicular to the first direction. A first connection pin is formed to be electrically coupled to one of the plurality of source/drain regions and to the lower power rail. The first connection pin is formed according to a cut mask having cut regions that define opposing ends of the first connection pin. An upper power rail is formed directly over the lower power rail and extending in the second direction. The upper power rail is electrically coupled to the first connection pin.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Peng, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Yung-Sung Yen
  • Patent number: 11011582
    Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anna Maria Conti, Andrea Redaelli, Agostino Pirovano
  • Patent number: 11004475
    Abstract: Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Seiji Narui
  • Patent number: 10998319
    Abstract: Provided is a memory structure including a substrate having a memory region and a peripheral region, a capacitor array, a transistor array, bit lines, and contacts. The capacitor array is on the substrate in the memory region. The transistor array is on and electrically connected to the capacitor array. The bit lines are extended along a row direction in parallel with each other on the transistor array, and are electrically connected to the transistor array. Each of the contacts is connected to one of the bit lines and a conductive device at the substrate in the peripheral region. Each of the contacts includes a first portion, a second portion, and a third portion. The second portion is between the first portion and the third portion. The third portion is electrically connected to the conductive device. Distances between each of the third portions and the memory region are the same.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: May 4, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 10998379
    Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Russell L. Meyer, Agostino Pirovano, Lorenzo Fratin
  • Patent number: 10991415
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip having a latency counter supplied with a first command and configured to generate a second command when a predetermined period is elapsed after the first command is activated; and a second semiconductor chip having an active control circuit configured to activate a state signal in response to the first command when the state signal is in an inactive state, deactivate the state signal in response to the first command when the state signal is in an active state, and activate the state signal in response to the second command generated based on the first command that is activated when the state signal is in the active state.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 27, 2021
    Assignee: Micron Tehcnology, Inc.
    Inventor: Homare Sato
  • Patent number: 10991423
    Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
  • Patent number: 10984885
    Abstract: A memory test array and a test method thereof are provided. The memory test array includes a first memory array, a second memory array, and a plurality of first common conductive pads. The first memory array includes a plurality of first bit lines and a plurality of first word lines. The second memory array is adjacent to the first memory array and includes a plurality of second bit lines and a plurality of second word lines. Each of the first common conductive pads has a first end and a second end, and the first ends and the second ends are respectively coupled to the first bit lines and the second bit lines, or respectively coupled to the first word lines and the second word lines. The memory test array of the present disclosure can effectively save the area of the memory test chip and make the test process more efficient.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: April 20, 2021
    Assignees: Jiangsu Advanced Memory Technology Co., Ltd., Jiangsu Advanced Memory Semiconductor Co., Ltd.
    Inventors: Hsiung-Shih Chang, Yu-Cheng Liao, Meng-Hsueh Tsai
  • Patent number: 10978348
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: April 13, 2021
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Patent number: 10964355
    Abstract: A device includes a memory array. The memory array includes a first sub-bank, a first strap cell coupled to the first sub-bank, and a first continuous data line. The first continuous data line includes a first portion and a second portion coupled to the first sub-bank via the first strap cell. The first portion of the first continuous data line is disposed above the first strap cell and the second portion of the first continuous data line is disposed above the first portion of the first continuous data line.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Patent number: 10957742
    Abstract: Devices and methods are provided to construct resistive random-access (RRAM) array structures which comprise RRAM memory cells, wherein each RRAM memory cell is formed of multiple parallel-connected RRAM devices to reduce the effects of resistive switching variability of the RRAM memory cells.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, ChoongHyun Lee, Seyoung Kim, Wilfried Haensch
  • Patent number: 10943668
    Abstract: A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction; a plurality of first memory cells; a first driver including a first selection line driver that drives the plurality of first selection lines on a basis of a first selection control signal and a second selection line driver that drives the plurality of second selection lines on a basis of the first selection control signal, the first and second selection line drivers being arranged side-by-side in the first direction; and a second driver including a third selection line driver that drives the plurality of third selection lines on a basis of a second selection control signal and a
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 9, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Haruhiko Terada, Makoto Kitagawa, Yoshiyuki Shibahara, Yotaro Mori
  • Patent number: 10937778
    Abstract: A tier of a 3D circuit comprising: one or more macro circuits, each macro circuit comprising a plurality of macro cells arranged in an array, the macro cells being separated from each other by spaces; and interconnection vias positioned in the spaces between the macro cells.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: March 2, 2021
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Hughes Metras, Fabien Clermidy, Didier Lattard, Sébastien Thuries, Pascal Vivet
  • Patent number: 10937500
    Abstract: A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Sanad Bushnaq
  • Patent number: 10908211
    Abstract: An integrated circuit and a detection method for multi-chip status thereof are provided. The integrated circuit includes at least one chip. The at least one chip has a stack status pin and a busy pin. The at least one chip applies a bias voltage on the busy pin according to a voltage status of the stack status pin. The at least one chip further detects an indication voltage on the busy pin, and decides whether a number of the at least chip is plural according to the indication voltage on the busy pin.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: February 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Ying-Te Tu
  • Patent number: 10885949
    Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: January 5, 2021
    Assignee: Rambus Inc.
    Inventor: Yohan Frans
  • Patent number: 10885971
    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: January 5, 2021
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Ming Li
  • Patent number: 10884923
    Abstract: A memory module-includes memory device groups, and a control circuit configurable to receive a system clock and input address and control (C/A) signals from a memory controller, and output a module clock, module C/A signals and data buffer control signals. The memory module further includes data buffers corresponding to respective memory device groups and configurable to receive the module clock and the data buffer control signals from the control circuit. A respective data buffer includes a n-bit wide data path and logic configured to control the data path in response to the data buffer control signals. The n-bit wide data path includes at least one programmable delay element controlled by the logic. The respective data buffer is further configurable to generate a respective local clock having a respective programmable delay from the module clock and to provide the respective local clock to a respective memory device group.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 5, 2021
    Assignee: NETLIST, INC.
    Inventors: Hyun Lee, Jayesh R. Bhakta
  • Patent number: 10886177
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: January 5, 2021
    Assignee: XCELSIS CORPORATION
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Patent number: 10879261
    Abstract: According to one embodiment, a semiconductor memory includes: a first member extending in a first direction perpendicular to a surface of a substrate, and including a first semiconductor layer; first and second interconnects extending in a second direction parallel to the surface of the substrate, the second interconnect neighboring the first interconnect in a third direction; a second member extending in the first direction and above the first member, the second member including a second semiconductor layer; third and a fourth interconnects extending in the second direction, the fourth interconnect neighboring the third interconnect in the third direction; and a third semiconductor layer between the first and the second members, the third semiconductor layer being continuous with the first and the second semiconductor layers.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Fumitaka Arai
  • Patent number: 10872654
    Abstract: A memory device includes a plurality of sub-word line drivers with, each sub-word line driver configured to receive a main word line signal and configured to drive a respective local word line to at least one of an active state, a soft-landing state, an off state based on the main word line signal and a phase signal. The memory device also includes a plurality of phase drivers with each phase driver configured to generate the respective phase signal. The memory device can further include a processing device configured to drive the respective local word line to the soft-landing state prior to entering the off state when transitioning from the active state to the off state so as to provide row hammer stress mitigation between adjacent local word lines corresponding to the plurality of sub-word line drivers. Each sub-word line driver includes a diode-connected transistor.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kyuseok Lee
  • Patent number: 10872651
    Abstract: A volatile memory device and a self-refresh method thereof are provided. The volatile memory device includes a dynamic memory array. The self-refresh method includes transmit a self-refresh request signal when entering a power saving mode. A voltage boost signal is periodically enabled according to the self-refresh request signal. When the enabled voltage boost signal is detected, an operating voltage for driving a self-refresh operation is pulled up to a self-refresh level. When the operating voltage is pulled up to the self-refresh level, the dynamic memory array is self-refreshed. When the self-refresh operation is completed, the operating voltage is floated.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: December 22, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Yuji Nakaoka
  • Patent number: 10854294
    Abstract: A semiconductor memory device includes a plurality of memory cell arrays accessed through a plurality of row lines and a plurality of bit lines; a pass transistor coupled to one of the plurality of row lines and configured to transfer an operating voltage to the one of the plurality of row lines; and a plurality of wiring lines disposed in a wiring line layer over the pass transistor. The wiring line layer includes a wiring inhibition interval which overlaps a source and a drain of the pass transistor. One or more of the plurality of wiring lines is disposed outside of the wiring inhibition interval.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Jin Ho Kim, Jeong Hwan Kim, Sang Hyun Sung, Sung Lae Oh
  • Patent number: 10847191
    Abstract: A semiconductor device includes a first pattern comprising first lines at a first interval and second pattern at the first interval. The second lines are between the first lines. A third pattern is above the first and the second patterns in a first and second areas. The third pattern includes third portions spaced from each other at the first interval in the first area and fourth portions spaced from each other at the first interval in the second area. The third portions are directly above the second lines in the first area and the fourth portions are directly above the first lines in the second area. A first contact is between third portions in the first area and connected to a first line of the first pattern. A second contact is between the fourth portions in the second area and connected to a second line of the second pattern.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: November 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yusuke Kasahara
  • Patent number: 10838831
    Abstract: Techniques for remapping portions of an array of non-volatile memory (NVM) resident on a die, in which the die is one of a plurality of NVM dice forming a memory device. A processing device partitions the NVM into a plurality of subslice elements comprising respective physical portions of non-volatile memory having proximal disturb relationships. The NVM has a first portion of the subslice elements allocated as user subslice elements and a second portion as spare subslice elements and the processing device performs an error analysis to identify a predetermined number of subslice elements having highest error rates for a memory domain on the die. For the identified subslice elements having the highest error rates, the processing device remaps user subslice elements to spare subslice elements that were not identified as having the highest error rates to remove subslice element or elements having highest error rates from a user space of the NVM.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: November 17, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Samuel E. Bradshaw, Justin Eno