Interconnection Arrangements Patents (Class 365/63)
  • Patent number: 10978348
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: April 13, 2021
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Patent number: 10964355
    Abstract: A device includes a memory array. The memory array includes a first sub-bank, a first strap cell coupled to the first sub-bank, and a first continuous data line. The first continuous data line includes a first portion and a second portion coupled to the first sub-bank via the first strap cell. The first portion of the first continuous data line is disposed above the first strap cell and the second portion of the first continuous data line is disposed above the first portion of the first continuous data line.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Patent number: 10957742
    Abstract: Devices and methods are provided to construct resistive random-access (RRAM) array structures which comprise RRAM memory cells, wherein each RRAM memory cell is formed of multiple parallel-connected RRAM devices to reduce the effects of resistive switching variability of the RRAM memory cells.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, ChoongHyun Lee, Seyoung Kim, Wilfried Haensch
  • Patent number: 10943668
    Abstract: A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction; a plurality of first memory cells; a first driver including a first selection line driver that drives the plurality of first selection lines on a basis of a first selection control signal and a second selection line driver that drives the plurality of second selection lines on a basis of the first selection control signal, the first and second selection line drivers being arranged side-by-side in the first direction; and a second driver including a third selection line driver that drives the plurality of third selection lines on a basis of a second selection control signal and a
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 9, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Haruhiko Terada, Makoto Kitagawa, Yoshiyuki Shibahara, Yotaro Mori
  • Patent number: 10937778
    Abstract: A tier of a 3D circuit comprising: one or more macro circuits, each macro circuit comprising a plurality of macro cells arranged in an array, the macro cells being separated from each other by spaces; and interconnection vias positioned in the spaces between the macro cells.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: March 2, 2021
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Hughes Metras, Fabien Clermidy, Didier Lattard, Sébastien Thuries, Pascal Vivet
  • Patent number: 10937500
    Abstract: A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Sanad Bushnaq
  • Patent number: 10908211
    Abstract: An integrated circuit and a detection method for multi-chip status thereof are provided. The integrated circuit includes at least one chip. The at least one chip has a stack status pin and a busy pin. The at least one chip applies a bias voltage on the busy pin according to a voltage status of the stack status pin. The at least one chip further detects an indication voltage on the busy pin, and decides whether a number of the at least chip is plural according to the indication voltage on the busy pin.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: February 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Ying-Te Tu
  • Patent number: 10885949
    Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: January 5, 2021
    Assignee: Rambus Inc.
    Inventor: Yohan Frans
  • Patent number: 10885971
    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: January 5, 2021
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Ming Li
  • Patent number: 10884923
    Abstract: A memory module-includes memory device groups, and a control circuit configurable to receive a system clock and input address and control (C/A) signals from a memory controller, and output a module clock, module C/A signals and data buffer control signals. The memory module further includes data buffers corresponding to respective memory device groups and configurable to receive the module clock and the data buffer control signals from the control circuit. A respective data buffer includes a n-bit wide data path and logic configured to control the data path in response to the data buffer control signals. The n-bit wide data path includes at least one programmable delay element controlled by the logic. The respective data buffer is further configurable to generate a respective local clock having a respective programmable delay from the module clock and to provide the respective local clock to a respective memory device group.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 5, 2021
    Assignee: NETLIST, INC.
    Inventors: Hyun Lee, Jayesh R. Bhakta
  • Patent number: 10886177
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: January 5, 2021
    Assignee: XCELSIS CORPORATION
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Patent number: 10879261
    Abstract: According to one embodiment, a semiconductor memory includes: a first member extending in a first direction perpendicular to a surface of a substrate, and including a first semiconductor layer; first and second interconnects extending in a second direction parallel to the surface of the substrate, the second interconnect neighboring the first interconnect in a third direction; a second member extending in the first direction and above the first member, the second member including a second semiconductor layer; third and a fourth interconnects extending in the second direction, the fourth interconnect neighboring the third interconnect in the third direction; and a third semiconductor layer between the first and the second members, the third semiconductor layer being continuous with the first and the second semiconductor layers.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Fumitaka Arai
  • Patent number: 10872654
    Abstract: A memory device includes a plurality of sub-word line drivers with, each sub-word line driver configured to receive a main word line signal and configured to drive a respective local word line to at least one of an active state, a soft-landing state, an off state based on the main word line signal and a phase signal. The memory device also includes a plurality of phase drivers with each phase driver configured to generate the respective phase signal. The memory device can further include a processing device configured to drive the respective local word line to the soft-landing state prior to entering the off state when transitioning from the active state to the off state so as to provide row hammer stress mitigation between adjacent local word lines corresponding to the plurality of sub-word line drivers. Each sub-word line driver includes a diode-connected transistor.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kyuseok Lee
  • Patent number: 10872651
    Abstract: A volatile memory device and a self-refresh method thereof are provided. The volatile memory device includes a dynamic memory array. The self-refresh method includes transmit a self-refresh request signal when entering a power saving mode. A voltage boost signal is periodically enabled according to the self-refresh request signal. When the enabled voltage boost signal is detected, an operating voltage for driving a self-refresh operation is pulled up to a self-refresh level. When the operating voltage is pulled up to the self-refresh level, the dynamic memory array is self-refreshed. When the self-refresh operation is completed, the operating voltage is floated.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: December 22, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Yuji Nakaoka
  • Patent number: 10854294
    Abstract: A semiconductor memory device includes a plurality of memory cell arrays accessed through a plurality of row lines and a plurality of bit lines; a pass transistor coupled to one of the plurality of row lines and configured to transfer an operating voltage to the one of the plurality of row lines; and a plurality of wiring lines disposed in a wiring line layer over the pass transistor. The wiring line layer includes a wiring inhibition interval which overlaps a source and a drain of the pass transistor. One or more of the plurality of wiring lines is disposed outside of the wiring inhibition interval.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Jin Ho Kim, Jeong Hwan Kim, Sang Hyun Sung, Sung Lae Oh
  • Patent number: 10847191
    Abstract: A semiconductor device includes a first pattern comprising first lines at a first interval and second pattern at the first interval. The second lines are between the first lines. A third pattern is above the first and the second patterns in a first and second areas. The third pattern includes third portions spaced from each other at the first interval in the first area and fourth portions spaced from each other at the first interval in the second area. The third portions are directly above the second lines in the first area and the fourth portions are directly above the first lines in the second area. A first contact is between third portions in the first area and connected to a first line of the first pattern. A second contact is between the fourth portions in the second area and connected to a second line of the second pattern.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: November 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yusuke Kasahara
  • Patent number: 10838831
    Abstract: Techniques for remapping portions of an array of non-volatile memory (NVM) resident on a die, in which the die is one of a plurality of NVM dice forming a memory device. A processing device partitions the NVM into a plurality of subslice elements comprising respective physical portions of non-volatile memory having proximal disturb relationships. The NVM has a first portion of the subslice elements allocated as user subslice elements and a second portion as spare subslice elements and the processing device performs an error analysis to identify a predetermined number of subslice elements having highest error rates for a memory domain on the die. For the identified subslice elements having the highest error rates, the processing device remaps user subslice elements to spare subslice elements that were not identified as having the highest error rates to remove subslice element or elements having highest error rates from a user space of the NVM.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: November 17, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Samuel E. Bradshaw, Justin Eno
  • Patent number: 10832748
    Abstract: Methods, systems, and devices that supports dual-mode modulation in the context of memory access are described. A system may include a memory array coupled with a buffer, and a multiplexer may be coupled with the buffer, where the multiplexer may be configured to output a bit pair representative of data stored within the memory array. The multiplexer may also be coupled with a driver, where the driver may be configured to generate a symbol representative of the bit pair that is output by the multiplexer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 10818675
    Abstract: SRAM structures are provided. A SRAM structure includes multiple SRAM cells arranged in multiple rows and multiple columns. A first SRAM cell is adjacent to a second SRAM cell in the same row. A third SRAM cell is adjacent to the first SRAM cell in the same column. A fourth SRAM cell is adjacent to the second SRAM in the same column. A contact plug is positioned between the first, second, third and fourth SRAM cells. A VSS line is electrically coupled to the first, second, third and fourth SRAM cells through the contact plug. The contact plug is free of the barrier layer.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hung Hsieh, Yu-Min Liao, Jhon-Jhy Liaw
  • Patent number: 10818548
    Abstract: Various semiconductor fabrication methods and structures are disclosed for cost effectively fabricating a self-aligned contact. A source-drain active region is on a substrate and horizontally extends to sidewall spacers of two adjacent gate stacks on the substrate. A conductive material layer including Titanium is formed by selective deposition on the source-drain active area. An interlevel dielectric (ILD) layer is deposited over the source-drain active area and the two gate stacks. Vertical directional etching in the ILD layer forms a vertical trench contacting the conductive material layer. Selective wet etching in the vertical trench selectively etches the conductive material layer and forms a void therein. Deposition of a second conductive material in the vertical trench fills the vertical trench, including the void, and the second conductive material contacts the top surface of the source-drain active area to form a source-drain self-aligned contact.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 27, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kafai Lai, Chih-Chao Yang, Yongan Xu, Su Chen Fan
  • Patent number: 10811393
    Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: October 20, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Mikihiko Ito, Masaru Koyanagi, Masafumi Nakatani, Shinya Okuno, Shigeki Nagasaka, Masahiro Yoshihara, Akira Umezawa, Satoshi Tsukiyama, Kazushige Kawasaki
  • Patent number: 10797037
    Abstract: An integrated circuit device having a plurality of stacked dies is described. The integrated circuit device comprises a first die of the plurality of stacked dies having an input/output element configured to receive an input signal, the first die comprising a signal driver circuit configured to provide the input signal to each die of the plurality of stacked dies and a chip select circuit for generating a plurality of chip select signals for the plurality of stacked dies; and a second die of the plurality of stacked dies coupled to the first die, the second die having a function block configured to the receive the input signal; wherein the second die receives the input signal in response to a chip select signal of the plurality of chip select signals that corresponds to the second die. A method of implementing an integrated circuit device having a plurality of stacked dies is also described.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 6, 2020
    Assignee: XILINX, INC.
    Inventor: Qi Lin
  • Patent number: 10789253
    Abstract: A storage device, connected to a computer including a processor and first memory, and executing a program, stores data processed under the program. The computer includes a protocol processing unit that accesses data in the storage device, an accelerator that includes an arithmetic unit executing a part of a process of the program, and a second memory storing data, and executes the part of the process. The first memory receives a processing request for processing data, and causes the accelerator to execute a command to process data, corresponding to the processing request for the processing request including a process to be executed by the arithmetic unit. The accelerator requests the protocol processing unit to provide target data indicated by a command received from the program, reads data from the storage device via the protocol processing unit, and stores the data in the second memory. The arithmetic unit executes the command.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: September 29, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhisa Fujimoto, Shinji Fujiwara, Satoru Watanabe, Akira Yamamoto
  • Patent number: 10755170
    Abstract: A technique relates a resistive processing unit (RPU) array. A set of conductive column wires are configured to form cross-points at intersections between the set of conductive row wires and a set of conductive column wires. Two-terminal RPUs are hysteretic such that the two-terminal RPUs each have a conductance state defined by hysteresis, where a two-terminal RPU of the two-terminal RPUs is located at each of the cross-points.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tayfun Gokmen, Rudolf M. Tromp
  • Patent number: 10725943
    Abstract: Apparatuses and methods for transferring data from memory on a data path are described. An example apparatus includes: one or more data terminals; a plurality of memory banks, one of the plurality of memory banks being selected responsive, at least in part, to a bank address; and a data path including a plurality of data path routes and a plurality of switching buffers on the plurality of data path routes. The plurality of switching buffers are arranged such that one or more of the plurality of switching buffers are selected responsive, at least in part, to the bank address and activates one of the plurality of data path routes.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hiromasa Noda
  • Patent number: 10727234
    Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.
    Type: Grant
    Filed: November 27, 2016
    Date of Patent: July 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Ding-Lung Chen, Xing Hua Zhang, Shan Liu, Runshun Wang, Chien-Fu Chen, Wei-Jen Wang, Chen-Hsien Hsu
  • Patent number: 10685707
    Abstract: A memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, each of the plurality of memory cells including a switching element and an information storage element connected to the switching element and containing a phase-change material, a decoder unit configured to determine a selected word line and a selected bit line connected to a selected memory cell to read data, among the plurality of memory cells, and a current compensation circuit configured to remove a leakage current from the selected word line, the leakage current corresponding to a sun of off-currents flowing in unselected bit lines, excluding the selected bit line, among the plurality of bit lines, from the selected word line.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Venkataramana Gangasani, Tae Hui Na, Bilal Ahmad Janjua
  • Patent number: 10678719
    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 9, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Kenneth L. Wright, John Eric Linstadt, Craig Hampel
  • Patent number: 10672663
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: June 2, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed, Eric M. Nequist
  • Patent number: 10672463
    Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: June 2, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Makoto Yabuuchi
  • Patent number: 10654041
    Abstract: System, apparatuses, and methods for performing automated reagent-based analysis are provided. Also provided are methods for automated attachment of a cap to a reaction receptacle, and automated removal of a cap from a capped reaction receptacle.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: May 19, 2020
    Assignee: Gen-Probe Incorporated
    Inventor: Byron J. Knight
  • Patent number: 10642922
    Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Phil Knag, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Abhishek Sharma, Sasikanth Manipatruni, Amrita Mathuriya, Ram Krishnamurthy, Ian A. Young
  • Patent number: 10644002
    Abstract: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: May 5, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10635610
    Abstract: A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: April 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Gary James Calder, Benjamin James Kerr, Philip Rose
  • Patent number: 10614014
    Abstract: To increase the number of selectable chips without adding a signal line to a general purpose memory controller. A semiconductor storage device includes a memory controller, a plurality of memory chips, a selection unit which is connected to the memory controller and is connected with the plurality of memory chips to be able to select any one of the plurality of memory chips, and a switch unit which is connected to the memory controller and the selection unit. The memory controller and the selection unit are connected by a signal line for transmitting a first signal outputted from the memory controller and configured to select the memory chips. The memory controller and the switch unit are connected by a signal line for transmitting a second signal outputted from the memory controller and configured to select the memory chips.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: April 7, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Ikeda, Yutaka Uematsu, Shungo Okabe, Akihiro Inamura, Takahiko Iwasaki, Junji Ogawa
  • Patent number: 10614859
    Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: April 7, 2020
    Assignee: Rambus Inc.
    Inventor: Thomas Vogelsang
  • Patent number: 10600691
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 24, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Patent number: 10600735
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 24, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Patent number: 10600780
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 24, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Patent number: 10593378
    Abstract: A memory device includes: a plurality of data pads; a data distribution circuit suitable for distributing data received through some data pads of the plurality of data pads to a first data bus, and distributing data received through the other data pads to a second data bus, in a first mode; a first channel region suitable for storing data obtained by copying the data of the first data bus at a predetermined ratio of 1:N where N is an integer equal to or more than 2; and a second channel region suitable for storing data obtained by copying the data of the second data bus at the predetermined ratio of 1:N.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 17, 2020
    Assignee: SK hynix Inc.
    Inventors: Myeong-Jae Park, Young-Jae Choi
  • Patent number: 10586786
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 10, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed, Eric M. Nequist
  • Patent number: 10579773
    Abstract: The invention relates to an integrated circuit comprising: a row of sink cells, a first driver cell, a second driver cell, an interconnect line connecting the first driver cell to the sink cells of the row; and a shunt line connecting the second driver cell to a point between ends of the interconnect line, wherein a segment of the interconnect line between the point and the first driver cell is bigger than 60% of a length the interconnect line and less than 80% of the length of the interconnect line.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joachim Keinert, Jens Noack, Monika Strohmer, Holger Wetter
  • Patent number: 10566054
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell having a variable resistance unit, a first selector, and a second selector. The first and second selectors are connected in series with the variable resistance unit and have different switching characteristics from one another. A control unit is provided to write data to the memory cell by setting a resistance state of the variable resistance unit and to read data from the memory cell according to the resistance state of the variable resistance unit.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: February 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shingo Nakazawa, Takayuki Miyazaki
  • Patent number: 10565138
    Abstract: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Ram Krishnamurthy, Sasikanth Manipatruni, Gregory Chen, Van Le, Amrita Mathuriya, Abhishek Sharma, Raghavan Kumar, Phil Knag, Huseyin Sumbul, Ian Young
  • Patent number: 10559550
    Abstract: A memory device includes a first volatile memory chip that includes a first volatile memory cell array storing first data and that receives or outputs the first data at a first bandwidth, and a second volatile memory chip that includes a second volatile memory cell array storing second data and that receives or outputs the second data at a second bandwidth different from the first bandwidth.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungbae Lee, Kwanghyun Kim, Sang-Kyu Kang, Do Kyun Kim, DongMin Kim, Ji Hyun Ahn
  • Patent number: 10546095
    Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Eric Foreman, Jeffrey Hemmett
  • Patent number: 10541018
    Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: James A. McCall, Christopher P. Mozak, Christopher E. Cox, Yan Fu, Robert J. Friar, Hsien-Pao Yang
  • Patent number: 10447584
    Abstract: A memory network includes a first local memory group, a second local memory group, and multiple first channels. The first local memory group includes multiple first memory devices that are not directly connected to each other. The second local memory group includes multiple second memory devices that are not directly connected to each other. The first channels are configured to connect the first memory devices to the second memory devices in a one to one relationship.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 15, 2019
    Assignees: SK HYNIX INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Gwangsun Kim, John Dongjun Kim, Yong-Kee Kwon
  • Patent number: 10417377
    Abstract: The invention relates to an integrated circuit comprising: a row of sink cells, a first driver cell, a second driver cell, an interconnect line connecting the first driver cell to the sink cells of the row; and a shunt line connecting the second driver cell to a point between ends of the interconnect line, wherein a segment of the interconnect line between the point and the first driver cell is bigger than 60% of a length the interconnect line and less than 80% of the length of the interconnect line.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joachim Keinert, Jens Noack, Monika Strohmer, Holger Wetter
  • Patent number: RE48191
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryota Katsumata, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota