Interconnection Arrangements Patents (Class 365/63)
  • Patent number: 10600691
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 24, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Patent number: 10600780
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 24, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Patent number: 10600735
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 24, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Patent number: 10593378
    Abstract: A memory device includes: a plurality of data pads; a data distribution circuit suitable for distributing data received through some data pads of the plurality of data pads to a first data bus, and distributing data received through the other data pads to a second data bus, in a first mode; a first channel region suitable for storing data obtained by copying the data of the first data bus at a predetermined ratio of 1:N where N is an integer equal to or more than 2; and a second channel region suitable for storing data obtained by copying the data of the second data bus at the predetermined ratio of 1:N.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 17, 2020
    Assignee: SK hynix Inc.
    Inventors: Myeong-Jae Park, Young-Jae Choi
  • Patent number: 10586786
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 10, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed, Eric M. Nequist
  • Patent number: 10579773
    Abstract: The invention relates to an integrated circuit comprising: a row of sink cells, a first driver cell, a second driver cell, an interconnect line connecting the first driver cell to the sink cells of the row; and a shunt line connecting the second driver cell to a point between ends of the interconnect line, wherein a segment of the interconnect line between the point and the first driver cell is bigger than 60% of a length the interconnect line and less than 80% of the length of the interconnect line.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joachim Keinert, Jens Noack, Monika Strohmer, Holger Wetter
  • Patent number: 10566054
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell having a variable resistance unit, a first selector, and a second selector. The first and second selectors are connected in series with the variable resistance unit and have different switching characteristics from one another. A control unit is provided to write data to the memory cell by setting a resistance state of the variable resistance unit and to read data from the memory cell according to the resistance state of the variable resistance unit.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: February 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shingo Nakazawa, Takayuki Miyazaki
  • Patent number: 10565138
    Abstract: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Ram Krishnamurthy, Sasikanth Manipatruni, Gregory Chen, Van Le, Amrita Mathuriya, Abhishek Sharma, Raghavan Kumar, Phil Knag, Huseyin Sumbul, Ian Young
  • Patent number: 10559550
    Abstract: A memory device includes a first volatile memory chip that includes a first volatile memory cell array storing first data and that receives or outputs the first data at a first bandwidth, and a second volatile memory chip that includes a second volatile memory cell array storing second data and that receives or outputs the second data at a second bandwidth different from the first bandwidth.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungbae Lee, Kwanghyun Kim, Sang-Kyu Kang, Do Kyun Kim, DongMin Kim, Ji Hyun Ahn
  • Patent number: 10546095
    Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Eric Foreman, Jeffrey Hemmett
  • Patent number: 10541018
    Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: James A. McCall, Christopher P. Mozak, Christopher E. Cox, Yan Fu, Robert J. Friar, Hsien-Pao Yang
  • Patent number: 10447584
    Abstract: A memory network includes a first local memory group, a second local memory group, and multiple first channels. The first local memory group includes multiple first memory devices that are not directly connected to each other. The second local memory group includes multiple second memory devices that are not directly connected to each other. The first channels are configured to connect the first memory devices to the second memory devices in a one to one relationship.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 15, 2019
    Assignees: SK HYNIX INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Gwangsun Kim, John Dongjun Kim, Yong-Kee Kwon
  • Patent number: 10417377
    Abstract: The invention relates to an integrated circuit comprising: a row of sink cells, a first driver cell, a second driver cell, an interconnect line connecting the first driver cell to the sink cells of the row; and a shunt line connecting the second driver cell to a point between ends of the interconnect line, wherein a segment of the interconnect line between the point and the first driver cell is bigger than 60% of a length the interconnect line and less than 80% of the length of the interconnect line.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joachim Keinert, Jens Noack, Monika Strohmer, Holger Wetter
  • Patent number: 10410727
    Abstract: A non-volatile memory (NVM) includes at least one memory unit region, each including a memory array and having first memory cells in the odd columns and second memory cells in the even columns. Corresponding to each memory unit region, the NVM includes a multiplexer including first bit line decoders and second bit line decoders, a comparator circuit including a first input terminal and a second input terminal, and a bias generation circuit generating a bias voltage. When reading a data information from a first memory cell, a first output voltage of the first memory cell is sent to the first input terminal and the bias voltage is sent to the second input terminal. When reading a data information from a second memory cell, a second output voltage of the second memory cell is sent to the second input terminal and the bias voltage is sent to the first input terminal.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: September 10, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Yi Jin Kwon, Hao Ni, Jim Chia-Ming Hsu, Xiao Yan Liu
  • Patent number: 10404286
    Abstract: A memory module includes data memories and at least one parity memory. Each of the data memories includes a first memory cell array with a first memory region to store data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits to perform error detection/correction associated with the data set. The at least one parity memory includes a second memory cell array with a first parity region to store parity bits associated with user data set corresponding to all of the data set stored in each of the data memories and a second parity region to store second parity bits for error detection/correction associated with the parity bits.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoon Sin, Sang-Uhn Cha, Ye-Sin Ryu, Seong-Jin Cho
  • Patent number: 10403352
    Abstract: The present disclosure includes apparatuses and methods for compute in data path. An example apparatus includes an array of memory cells. Sensing circuitry is coupled to the array of memory cells. A shared input/output (I/O) line provides a data path associated with the array. The shared I/O line couples the sensing circuitry to a compute component in the data path of the shared I/O line.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Richard C. Murphy
  • Patent number: 10354956
    Abstract: A contact level silicon oxide layer and a silicon nitride layer is formed over a semiconductor device on a semiconductor substrate. A contact via cavity extending to the semiconductor device is formed. A lower contact via structure portion is formed and recessed between top and bottom surface of the silicon nitride layer. An upper contact via structure portion including a hydrogen diffusion barrier material is formed in a remaining volume of the contact via cavity to provide a contact via structure. A three-dimensional memory array is formed over the silicon nitride layer. Metal interconnect structures are formed to provide electrical connection between the contact via structure and a node of the three-dimensional memory array. The hydrogen diffusion barrier material and the silicon nitride layer block downward diffusion of hydrogen.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Daxin Mao, Hiroyuki Ogawa, Johann Alsmeier
  • Patent number: 10354047
    Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric Foreman, Jeffrey Hemmett
  • Patent number: 10348298
    Abstract: This disclosure generally relates to repeaters, and, in particular, repeaters for open-drain systems. In one embodiment, an apparatus comprises a first port, a second port, a current detector, a transistor, and a control logic circuit. A current detector input of the current detector is coupled to the first port. A transistor channel electrode of the transistor is coupled to the second port. A control logic circuit input of the control logic circuit is coupled to the current detector output, and a control logic circuit output of the control logic circuit is coupled to a transistor control electrode of the transistor.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: July 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vikas Suma Vinay, Tatsuyuki Nihei, Christopher Lewis Kraft
  • Patent number: 10339981
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: July 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Patent number: 10324841
    Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in groups, each group including at least one memory device, while the data buffer control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits, a respective buffer circuit corresponding to a respective group of memory devices. The plurality of buffer circuits are distributed across a surface of the memory module such that each data buffer control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits include clock regeneration circuits to regenerate a clock signal received from the module control device and to provide regenerated clock signals to respective groups of memory devices.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: June 18, 2019
    Assignee: NETLIST, INC.
    Inventors: Hyun Lee, Jayesh R. Bhakta
  • Patent number: 10319741
    Abstract: A semiconductor device includes first and second select lines, first and second vertical pillars, and first and second subsidiary lines. The select lines are spaced apart and include a first separating insulation layer therebetween. Each of the first and second vertical pillars is connected to a corresponding one of the first or second select lines. The first vertical pillars are closer to the first separating insulation layer. The second vertical pillars arranged in an oblique direction from the first vertical pillars. Each of the first subsidiary lines connects a pair of the first vertical pillars. Each of the second subsidiary lines connects a pair of the second vertical pillars adjacent. The first and second subsidiary lines are alternately disposed along a first direction, and ends of the first and second subsidiary lines are aligned along the first direction.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Wangho Shin
  • Patent number: 10310744
    Abstract: According to one embodiment, a memory system includes a first memory, a second memory, a third memory, a data transmission controller, and a processing unit. The second memory is configured to store first management information to manage the first memory. The third memory is configured to be accessed at a speed higher than the second memory. The processing unit causes the data transmission controller to transmit second management information and third management information from the second memory to the third memory in a burst mode before a read process is performed on the first memory. The second management information and the third management information are related to the read process and are included in the first management information. The processing unit performs the read process on the first memory using the second management information and the third management information stored in the third memory.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: June 4, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Erika Ikeda, Yoshihisa Kojima
  • Patent number: 10296704
    Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric Foreman, Jeffrey Hemmett
  • Patent number: 10283171
    Abstract: An apparatus includes a first tier, a second tier and a memory. The second tier is vertically stacked on the first tier. The memory includes a column of memory bit cells. A first portion of the column of memory bit cells is on the first tier. A second portion of the column of memory bit cells is on the second tier.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shyh-An Chi
  • Patent number: 10276429
    Abstract: An interconnect layout structure having air gaps includes a plurality of air gaps extended along a direction, and at least a first interconnect unit disposed in between the air gaps. The first interconnect unit includes a first conductive line, a first landing mark situated on the first conductive line and a first via structure situated on the first landing mark. The first via structure penetrates the first landing mark and is electrically connected to the first conductive line. And the first landing mark physically separates the air gaps arranged in a straight line.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Chia-Fang Lin
  • Patent number: 10249367
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 2, 2019
    Assignee: SK hynix Inc.
    Inventors: Jung Hyuk Yoon, Yoon Jae Shin
  • Patent number: 10229900
    Abstract: A semiconductor memory device includes a memory structure including a first integrated circuit chip and a plurality of second integrated circuit chips stacked on each other, the first integrated circuit chip is interposed between a pair of the plurality of second integrated circuit chips, an interface unit disposed on the first integrated circuit chip, the memory structure is connected to a third circuit through the interface unit, and the interface unit transfers operation signals to the first integrated circuit chip and the plurality of second integrated circuit chips, at least one inter-chip interconnector connected with the interface unit and the first integrated circuit chip and the plurality of second integrated circuit chips, and an external interconnector connected with the interface unit and the third circuit.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Wan Kim, Sung-Chul Park, Won-Il Bae
  • Patent number: 10204662
    Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 12, 2019
    Assignee: Rambus Inc.
    Inventor: Thomas Vogelsang
  • Patent number: 10199096
    Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: February 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10192598
    Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: January 29, 2019
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
  • Patent number: 10163886
    Abstract: A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10147658
    Abstract: A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips includes a delay chain. Each of the plurality of stacked chips comprises a plurality of Through-Vias, wherein one of the plurality of Through-Vias formed in a first one of the plurality of stacked chips and electrically coupled to a predetermined location of a first delay chain on the first one of the plurality of stacked chips and one of the plurality of Through-Vias formed in a neighboring one of the plurality of stacked chips and electrically coupled to a predetermined location of a delay chain on the neighboring one of the plurality of stacked chips are configured to electrically couple the first one of the plurality of stacked chips to the neighboring one of the plurality of stacked chips. A signal transmitted from a first one of the plurality of stacked chips generates a feedback signal to the first one of the plurality of stacked chips through one or more of the plurality of Through-Vias.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 4, 2018
    Assignee: SK hynix Inc.
    Inventor: Sang Ho Lee
  • Patent number: 10147479
    Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: December 4, 2018
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventors: Yoshinori Matsui, Toshio Sugano, Hiroaki Ikeda
  • Patent number: 10140234
    Abstract: A storage apparatus includes a printed circuit board (PCB) and multiple memory chips symmetrically arranged on two sides of the PCB, where multiple memory chips on one side of the PCB form a rank, and multiple memory chips on the other side of the PCB form a rank; a memory chip includes multiple pins; multiple cables are disposed in the PCB; and one cable of the multiple cables is connected to two pins in a same position on the two sides of the PCB.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: November 27, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Rangliang Wu, Yuzhu Chen
  • Patent number: 10115680
    Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a first stacked body, a columnar part, a second insulating film, and a second stacked body. The first stacked body is provided in a first region on the substrate. The second insulating film is provided in a second region on the substrate, and has a first thickness in a stacking direction of the first stacked body. The second stacked body is provided on the second insulating film. The second stacked body includes a first film and a third insulating film stacked alternately on one another. The uppermost first film in the first films of the second stacked body is located at a first distance in the stacking direction from the upper surface of the substrate. The first thickness is a thickness not less than 30 percent of the first distance.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: October 30, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Takeshi Kusakabe
  • Patent number: 10114548
    Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: October 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Jun Shin, Tae-Young Oh
  • Patent number: 10067539
    Abstract: A stackable layer is provided for 3-Dimensional multi-layered modular computers. The stackable layer comprises at least one encapsulated chip die. Sets of electrical contacts are provided on each one of the large surfaces of the layer. The encapsulated chip die and the two large opposite surfaces of the layer are substantially parallel.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 4, 2018
    Assignee: BEYOND BLADES LTD.
    Inventor: Aviv Soffer
  • Patent number: 10056119
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 21, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masato Sugita, Naoki Kimura, Daisuke Kimura
  • Patent number: 10056120
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: August 21, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H. S. Tang
  • Patent number: 10043781
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; at least one connection from the plurality of first transistors to a plurality of through silicon vias (TSVs); a plurality of third transistors overlaying the plurality of second transistors, where the plurality of second transistors are self-aligned to the plurality of third transistors having been processed following the same lithography step; and a first memory array and a second memory array, where the first memory array includes the plurality of second transistors and the second memory array includes the plurality of third transistors.
    Type: Grant
    Filed: February 25, 2018
    Date of Patent: August 7, 2018
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • Patent number: 10044123
    Abstract: A backplane system, which includes a backplane board and a backplane controller module having a backplane controller. The backplane controller module is configured to be detachably connected to the backplane board via a small outline dual in-line memory module (SODIMM) connector interface to enable communications between the backplane controller and the backplane board via the SODIMM connector interface, such that the backplane controller is configured to control a plurality of components on the backplane board. Specifically, the SODIMM connector interface may include a SODIMM connector socket disposed on the backplane board, and a SODIMM connector pin set provided on the backplane controller module to be detachably inserted into the SODIMM connector socket. The SODIMM connector pin set may be a 144-pin SODIMM connector having 144 contact pins.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: August 7, 2018
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventor: Shibu Abraham
  • Patent number: 10014037
    Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: July 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyo-min Sohn
  • Patent number: 9991894
    Abstract: A layout arrangement for a resistive random access memory cell includes an active area, a polysilicon row address line over the active region, a metal column address line running orthogonal to the row address line and having an active region contact portion extending over the active region and having a contact to the active region. A metal output line runs parallel to the column address line over the active region. A first cell contact region intersects with the output line and has a contact to the active region. A first metal cell contact region forms an intersection with the first cell contact region. A first resistive random access memory device is formed at the intersection of the first cell contact region and the output line. A second resistive random access memory device is formed at the intersection of the first cell contact region and the first cell contact region.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: June 5, 2018
    Assignee: Microsemi SoC Corp.
    Inventors: Jonathan Greene, Frank Hawley, John L. McCollum
  • Patent number: 9984741
    Abstract: A system includes a memory device and a memory controller. The memory device has a data pin and a first available pin. The memory controller has a data pin coupled to the data pin of the memory device, and has a first available pin coupled to the first available pin of the memory device. The memory controller transfers memory data on the first available pin of the memory controller, and the memory device receives memory data on the first available pin of the memory device.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: May 29, 2018
    Assignee: DELL PRODUCTS, LP
    Inventors: Vadhiraj Sankaranarayanan, Stuart Allen Berke, Bhyrav M. Mutnury
  • Patent number: 9974176
    Abstract: An apparatus includes a motherboard, a storage module, a first socket arranged on the motherboard, a second socket also arranged on the motherboard, and an interface. A processor is arranged within the first socket and a storage module is arranged within the second socket. The interface is configured to provide intercommunication between the processor and the storage module. The storage module contains a plurality of nonvolatile memory cards.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: May 15, 2018
    Assignee: Cisco Technology, Inc.
    Inventor: Charles Calvin Byers
  • Patent number: 9934179
    Abstract: A wafer-level package has a first input/output (I/O) port, a second I/O port, a first semiconductor die, and a second semiconductor die. The first I/O port and the second I/O port of the wafer-level package are arranged to connect at least one management bus. The first semiconductor die and the second semiconductor die assembled in the wafer-level package are arranged to receive commands from the first I/O port and the second I/O port, respectively.
    Type: Grant
    Filed: February 14, 2016
    Date of Patent: April 3, 2018
    Assignee: MEDIATEK INC.
    Inventor: Yao-Chun Su
  • Patent number: 9922716
    Abstract: Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 20, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chia-Lin Hsiung, Yanbin An, Alexander Chu, Fumiaki Toyama
  • Patent number: 9917049
    Abstract: According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(?/NA) or less when an exposure wavelength of an exposure device is ?, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: March 13, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Fumiharu Nakajima, Toshiya Kotani, Hiromitsu Mashita, Takafumi Taguchi, Ryota Aburada, Chikaaki Kodama
  • Patent number: 9897860
    Abstract: A first photo-alignment film (12) of a liquid crystal display device (100) includes a first and a second pre-tilt region (12a, 12b) defining pre-tilt directions (PD1, PD2) that are anti-parallel to each other, and a second photo-alignment film (22) thereof includes a third and a fourth pre-tilt region (22a, 22b) defining pre-tilt directions (PD3, PD4) that are anti-parallel to each other. The entire boundary (BD1) between the first and second pre-tilt regions and the entire boundary (BD2) between the third and fourth pre-tilt regions are aligned with each other, as seen from the display plane normal direction. A pixel electrode (11) includes a first and a second cut-off portion (11a1, 11a2) provided by cutting off at least a part of a particular edge portion (11e1, 11e2) of the outer perimeter thereof.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: February 20, 2018
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ken Kuboki, Tsuyoshi Okazaki, Yusuke Nishihara