Magnetic Patents (Class 365/66)
  • Patent number: 10755780
    Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, LTD.
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng
  • Patent number: 10573810
    Abstract: A semiconductor memory device includes a first select line and a second select line. A first memory element among a plurality of memory elements has a first top electrode and a first bottom electrode. The first top electrode is connected to the first select line and the first bottom electrode is connected to the second select line. A second memory element among the plurality of memory elements, which is disposed adjacent to the first memory element, has a second top electrode and a second bottom electrode. The second top electrode is connected to the first select line, and the second bottom electrode is connected to the first select line without passing a resistive element of a memory element other than the second memory element.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 25, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoshiaki Nakao, Kazuyuki Kouno
  • Patent number: 9805790
    Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Nathaniel J. August, Pulkit Jain, Stefan Rusu, Fatih Hamzaoglu, Rangharajan Venkatesan, Muhammad Khellah, Charles Augustine, Carlos Tokunaga, James W. Tschanz, Yih Wang
  • Patent number: 9761293
    Abstract: According to one embodiment, a semiconductor storage device includes a first semiconductor storage area; a second semiconductor storage area; a reference circuit; a sense amplifier senses data stored in the first semiconductor storage area and the second semiconductor storage area; and a control circuit.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akira Katayama
  • Patent number: 9496272
    Abstract: A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 15, 2016
    Assignee: SanDisk Technologies LLC
    Inventor: Raul Adrian Cernea
  • Patent number: 9244853
    Abstract: A multi-core processor is presented. The multi-core processor includes a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache associated with a first core of the multi-core processor and tuned according to first attributes and a second STT-MRAM cache associated with a second core of the multi-core processor and tuned according to second attributes.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: January 26, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Seung H. Kang, Xiaochun Zhu, Xiaoxia Wu
  • Patent number: 9030865
    Abstract: In various embodiments, a circuit arrangement may be provided including a data cell. The circuit arrangement may further include a first transistor and a second transistor. The first controlled electrode of the first transistor and the first controlled electrode of the second transistor may be coupled to the first electrode of the data cell. The second controlled electrode of the first transistor may be configured to electrically connect to a first reference voltage such that the first electrode of the data cell is electrically connected to the first reference voltage when the first transistor is activated. The second controlled electrode of the second transistor may be configured to electrically connect to a second reference voltage, such that the first electrode of the data cell is electrically connected to the second reference voltage when the second transistor is activated.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: May 12, 2015
    Assignee: Agency for Science, Technology and Research
    Inventors: Kit Ho Melvin Chow, Fei Li
  • Publication number: 20150117081
    Abstract: A memory cell with a decoupled read/write path, the memory cell includes a switch comprising a gate, a first terminal and a second terminal, a resistive switching device connected to the gate of the switch, and a conductive path between the gate of the switch and the second terminal.
    Type: Application
    Filed: January 9, 2015
    Publication date: April 30, 2015
    Inventors: Yu-Wei Ting, Kuo-Ching Huang, Chun-Yang Tsai
  • Patent number: 9019768
    Abstract: A semiconductor device includes active strips. Active strip stack selection structures electrically couple to the active strip stacks at positions between the first and second ends, and select particular ones of the active strip stacks for operations. In one embodiment, different pads coupled to opposite pads have a higher voltage, depending on the memory cell selected for read. The same active strip stack selection structure can act as a pair of side gates for opposite sides of a first active strip stack, and as one side gate for each of the adjacent active strip stacks. Each active strip stack can have: a first structure from a first set acting as first and second side gates on a first side of word lines; and a second structure and a third structure from a second set respectively acting as third and fourth side gates on the second side of word lines.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: April 28, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Guan-Ru Lee
  • Publication number: 20150109846
    Abstract: To provide a memory apparatus capable of operating at high speed with less current and inhibiting a decrease in an amplitude of a readout signal. A memory apparatus includes a memory device at least including a memory layer, a magnetic fixed layer, and an intermediate layer made of a non-magnetic body disposed between the memory layer and the magnetic fixed layer; current being capable of flowing in a lamination direction; a wiring for supplying current flowing to the lamination direction; and a memory control unit for storing information by flowing standby current at a predetermined level to the memory device via the wiring to incline the magnetization direction of the memory layer from the direction perpendicular to a film surface and flowing recording current that is higher than the standby current via the wiring to change the magnetization direction of the memory layer.
    Type: Application
    Filed: March 6, 2013
    Publication date: April 23, 2015
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Publication number: 20150070961
    Abstract: A semiconductor storage device includes a first bit line and a second bit line. A nonvolatile memory element and a first cell transistor are connected in series between the first bit line and the second bit line. A sense transistor has a gate connected to a sense node which is provided between the first bit line and the memory element. A read bit line is connected to a source or a drain of the sense transistor. The read bit line is configured to transmit data of the memory element. A sense amplifier is configured to detect the logic of data transmitted from the read bit line.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 12, 2015
    Inventors: Akira KATAYAMA, Masahiro TAKAHASHI
  • Publication number: 20150036409
    Abstract: An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM Incorporated
    Inventors: Seong-Ook Jung, Taehui Na, Jisu Kim, Jung Pill Kim, Seung H. Kang
  • Patent number: 8942040
    Abstract: According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a drive circuit. When a failure exists within a corresponding first logical block, the latch circuits store a flag indicating the failure. The drive circuit inhibits driving of the word lines belonging to the first logical block when the flag is stored in the latch circuit corresponding to the first logical block to which the selected word lines belong, and allows the driving of the word lines belonging to the physical block including the first logical block when the flag is not stored in the latch circuit corresponding to the first logical block to which the selected word lines belong.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: January 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masanobu Shirakawa
  • Publication number: 20150023085
    Abstract: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.
    Type: Application
    Filed: October 2, 2014
    Publication date: January 22, 2015
    Inventor: Tsuneo Inaba
  • Patent number: 8913424
    Abstract: Magnetic memory cell comprising two conductors and a magnetic storage element between the two conductors, wherein a magnetic enhancement layer (MEL) is provided in the proximity of at least along a partial length of at least one of the two conductors. The MEL is for enhancing a magnetic field in the element when the two conductors are energized. Methods for operation and fabrication process for the memory cell are also disclosed. The memory cell is particularly for use in magnetic random access memory (MRAM) circuits, when using magnetic tunnel junction (MTJ) stacks as the magnetic storage elements.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: December 16, 2014
    Assignee: III Holdings 1, LLC
    Inventor: Krishnakumar Mani
  • Patent number: 8891276
    Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: November 18, 2014
    Assignee: Unity Semiconductor Corporation
    Inventors: Chang Hua Siau, Bruce Bateman
  • Patent number: 8879307
    Abstract: A magnetoresistive device of an embodiment includes: first and second devices each including, a first magnetic layer having a changeable magnetization perpendicular to a film plane, a second magnetic layer having a fixed and perpendicular magnetization, and a nonmagnetic layer interposed between the first and second magnetic layers, the first and second devices being disposed in parallel on a first face of an interconnect layer; and a TMR device including a third magnetic layer having perpendicular magnetic anisotropy and having a changeable magnetization, a fourth magnetic layer having a fixed magnetization parallel to a film plane, and a tunnel barrier layer interposed between the third and fourth magnetic layers, the TMR device being disposed on a second face of the interconnect layer, and the third magnetic layer being magnetostatically coupled to the first magnetic layers of the first and second devices.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Kitagawa, Naoharu Shimomura, Hiroaki Yoda, Junichi Ito, Minoru Amano, Chikayoshi Kamata, Keiko Abe
  • Patent number: 8854871
    Abstract: A method for the control of the magnetic states of interacting magnetic elements comprising providing a magnetic structure with a plurality of interacting magnetic elements. The magnetic structure comprises a plurality of magnetic states based on the state of each interacting magnetic element. The desired magnetic state of the magnetic structure is determined. The active resonance frequency and amplitude curve of the desired magnetic state is determined. Each magnetic element of the magnetic structure is then subjected to an alternating magnetic field or electrical current having a frequency and amplitude below the active resonance frequency and amplitude curve of said desired magnetic state and above the active resonance frequency and amplitude curve of the current state of the magnetic structure until the magnetic state of the magnetic structure is at the desired magnetic state.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: October 7, 2014
    Assignee: U.S. Department of Energy
    Inventors: Shikha Jain, Valentyn Novosad
  • Publication number: 20140286075
    Abstract: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.
    Type: Application
    Filed: September 4, 2013
    Publication date: September 25, 2014
    Inventors: Akira KATAYAMA, Masahiro TAKAHASHI, Tsuneo INABA, Hyuck Sang YIM, Dong Keun KIM, Byoung Chan OH, Ji Wang LEE
  • Patent number: 8836056
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Mark L. Doczy, Brian Doyle, Uday Shah, David L. Kencke, Roksana Golizadeh Mojarad, Robert S. Chau
  • Patent number: 8830742
    Abstract: A magnetic memory according to an embodiment includes: a magnetic structure extending in a first direction and having a circular ring-like shape in cross-section in a plane perpendicular to the first direction; a nonmagnetic layer formed on an outer surface of the magnetic structure, the outer surface extending in the first direction; and at least one reference portion formed on part of a surface of the nonmagnetic layer, the surface being on the opposite side from the magnetic structure, the at least one reference portion containing a magnetic material.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Kondo, Hirofumi Morise, Shiho Nakamura
  • Publication number: 20140233294
    Abstract: A memory cell with a decoupled read/write path includes a switch comprising a first terminal connected to a first line and a second terminal connected to a second line, a resistive switching device connected between a gate of the switch and a third line, and a conductive path between the gate of the switch and the second line.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Patent number: 8755220
    Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: John F. Bulzacchelli, William J. Gallagher, Mark B. Ketchen
  • Publication number: 20140153311
    Abstract: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.
    Type: Application
    Filed: February 4, 2014
    Publication date: June 5, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Inaba
  • Patent number: 8743578
    Abstract: Hydro-carbon nanorings may be used in storage. Sufficiently cooled, an externally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of electrons. Similarly, an internally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of positrons. When matched streams of positrons and electrons are sufficiently compressed they may form Cooper pairs with magnetic moments aligned to the movement of the stream. Matched adjacent Cooper pairs of electrons and positrons may contain information within their magnetic moments, and as such, may transmit and store information with little or no energy loss.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: June 3, 2014
    Inventor: Laurence H. Cooke
  • Patent number: 8741664
    Abstract: A method of fabricating a self-aligning magnetic tunnel junction the method includes patterning a lithographic strip on a second magnetic material deposited on a first magnetic material that is disposed on a substrate, forming a top magnetic strip by etching an exposed portion of the second magnetic material, patterning a nanowire and a magnetic reference layer island over the substrate and forming the nanowire and the magnetic reference layer island by etching an exposed portion of the first magnetic layer and an exposed portion of the top magnetic strip, wherein an interface between the magnetic nanowire and the magnetic reference layer island is an magnetic tunnel junction aligned with a width of the nanowire.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Michael C. Gaidis
  • Publication number: 20140104920
    Abstract: According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit. An address and data are transferred between the processor chip and the memory chip by use of shared bumps of the bumps.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 17, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Hiroki Noguchi, Shinobu Fujita
  • Publication number: 20140063891
    Abstract: According to one or more embodiments of the present invention, the semiconductor memory device of this disclosure includes the first bit line and the second bit line. Each of the multiple memory cells includes a memory element and a transistor, which are connected in series between the first and the second bit lines. Multiple memory cells are connected in parallel between the first and the second bit lines. In the first memory cell, its memory element is connected to the first bit line, and its transistor is connected to the second bit line. In the second memory cell, its memory element is connected to the second bit line, and its transistor is connected to the first bit line.
    Type: Application
    Filed: March 5, 2013
    Publication date: March 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki ASAO
  • Publication number: 20130314969
    Abstract: Each of m word lines is connected to n memory cells in a corresponding one of rows of m×n memory cells. Each of n bit lines is connected to m memory cells in a corresponding one of columns of m×n memory cells, and each of n source lines is connected to m memory cells in a corresponding one of columns of m×n memory cells. N first switching elements switch connection states between a reference node and the n bit lines, and n second switching elements switch connection states between the reference node and the n source lines. N third switching elements switch connection states between the write driver and the n bit lines, and n fourth switching elements switch connection states between the write driver and the n source lines.
    Type: Application
    Filed: August 1, 2013
    Publication date: November 28, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: Kazuyuki KOUNO
  • Patent number: 8587982
    Abstract: Embodiments include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 19, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Jung Pill Kim, Hari M. Rao, Xiaochun Zhu, Xia Li, Seung H. Kang
  • Publication number: 20130294136
    Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.
    Type: Application
    Filed: July 3, 2013
    Publication date: November 7, 2013
    Inventors: Chang Hua Siau, Bruce Lynn Bateman
  • Patent number: 8575667
    Abstract: A magnetic memory device includes a free layer and a guide layer on a substrate. An insulating layer is interposed between the free layer and the guide layer. At least one conductive bridge passes through the insulating layer and electrically connects the free layer and the guide layer. A diffusion barrier may be interposed between the guide layer and the insulating layer. The device may further include a reference layer having a fixed magnetization direction on a side of the free layer opposite the insulating layer and a tunnel barrier between the reference layer and the free layer. Related fabrication methods are also described.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: November 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: KyungTae Nam, Jangeun Lee, Sechung Oh, Woojin Kim, Dae Kyom Kim, Junho Jeong
  • Patent number: 8565012
    Abstract: Magnetic memory cell comprising two conductors and a magnetic storage element between the two conductors, wherein a magnetic enhancement layer (MEL) is provided in the proximity of at least along a partial length of at least one of the two conductors. The MEL is for enhancing a magnetic field in the element when the two conductors are energized. Methods for operation and fabrication process for the memory cell are also disclosed. The memory cell is particularly for use in magnetic random access memory (MRAM) circuits, when using magnetic tunnel junction (MTJ) stacks as the magnetic storage elements.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: October 22, 2013
    Assignee: Magsil Corporation
    Inventor: Krishnakumar Mani
  • Publication number: 20130265814
    Abstract: A magnetic random access memory includes multiple gate lines that are divided into a first gate line group and a second gate line group and arranged to be parallel to one another; multiple magnetic random access memory cells that are bonded to the gate lines in a direction intersected with the gate lines, respectively; multiple source lines that are bonded to one ends of switching devices included in the magnetic random access memory cells and arranged to be parallel to one another; and multiple bit lines that are bonded to one ends of magnetic tunnel junction devices included in the magnetic random access memory cells and arranged to be parallel to one another.
    Type: Application
    Filed: April 9, 2013
    Publication date: October 10, 2013
    Applicant: EWHA UNIVERSITY - INDUSTRY COLLABORATION FOUNDATION
    Inventor: EWHA UNIVERSITY - INDUSTRY COLLABORATION FOUNDATION
  • Patent number: 8553451
    Abstract: Techniques are provided for programming a spin torque transfer magnetic random access memory (STT-MRAM) cell using a unidirectional and/or symmetrical programming current. A unidirectional programming current flows through the free region of the STT-MRAM cell in one direction to switch the magnetization of the free region in at least two different directions. A symmetrical programming current switches the magnetization of the free region to either of the two different directions using a substantially similar current magnitude. In some embodiments, the STT-MRAM cell includes two fixed regions, each having fixed magnetizations in opposite directions and a free region configured to be switched in magnetization to be either parallel with or antiparallel to the magnetization of one of the fixed regions. Switching the free region to different magnetization directions may involve directing the programming current through one of the two oppositely magnetized fixed regions.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 8, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8547732
    Abstract: In one embodiment, the invention is a hybrid superconducting-magnetic memory cell and array. One embodiment of a memory cell includes a magnetoresistive element and at least one superconducting element wired in parallel with the magnetoresistive element. In a further embodiment, memory cells of the disclosed configuration are arranged to form a memory array.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: John F Bulzacchelli, William J Gallagher, Mark B Ketchen
  • Patent number: 8514605
    Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: August 20, 2013
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
  • Patent number: 8514617
    Abstract: A magnetic memory element capable of maintaining high thermal stability (retention characteristics) while reducing a writing current. The magnetic memory element includes a magnetic tunnel junction having a first magnetic body including a perpendicular magnetization film, an insulating layer, and a second magnetic body serving as a storage layer including a perpendicular magnetization film, which are sequentially stacked. A thermal expansion layer is disposed in contact with the magnetic tunnel junction portion. The second magnetic body is deformed in a direction in which the cross section thereof increases or decreases by the thermal expansion or contraction of the thermal expansion layer due to the flow of a current, thereby reducing a switching current threshold value required to change the magnetization direction.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: August 20, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Michiya Yamada, Yasushi Ogimoto
  • Patent number: 8488357
    Abstract: Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: July 16, 2013
    Assignee: MagIC Technologies, Inc.
    Inventors: Toshio Sunaga, Lejan Pu, Perng-Fei Yuh, Chao-Hung Chang
  • Patent number: 8456882
    Abstract: A method and system for providing a magnetic junction usable in a magnetic memory are described. The magnetic junction includes first and second pinned layers, first and second nonmagnetic spacer layers, and a free layer. The first pinned layer has a first pinned layer magnetic moment and is nonmagnetic layer-free. The first nonmagnetic spacer layer resides between the first pinned and free layers. The free layer resides between the first and second nonmagnetic spacer layers. The second pinned layer has a second pinned layer magnetic moment and is nonmagnetic layer-free. The second nonmagnetic spacer layer resides between the free and second pinned layers. The first and second pinned layer magnetic moments are antiferromagnetically coupled and self-pinned. The magnetic junction is configured to allow the free layer to be switched between stable magnetic states when a write current is passed through the magnetic junction.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: June 4, 2013
    Assignee: Grandis, Inc.
    Inventors: Dmytro Apalkov, Vladimir Nikitin, David Druist, Steven M. Watts
  • Patent number: 8456883
    Abstract: CMOS devices are provided in a substrate having a topmost metal layer comprising metal landing pads and metal connecting pads. A plurality of magnetic tunnel junction (MTJ) structures are provided over the CMOS devices and connected to the metal landing pads. The MTJ structures are covered with a dielectric layer that is polished until the MTJ structures are exposed. Openings are etched in the dielectric layer to the metal connecting pads. A seed layer is deposited over the dielectric layer and on inside walls and bottom of the openings. A copper layer is plated on the seed layer until the copper layer fills the openings. The copper layer is etched back and the seed layer is removed. Thereafter, an aluminum layer is deposited over the dielectric layer, contacting both the copper layer and the MTJ structures, and patterned to form a bit line.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: June 4, 2013
    Assignee: Headway Technologies, Inc.
    Inventor: Daniel Liu
  • Patent number: 8450818
    Abstract: Methods of forming spin torque microelectronic devices are described. Those methods may include forming a free FM layer on a substrate, forming a non-magnetic layer on the free FM layer, forming at least three input pillars on the non-magnetic layer, and forming an output pillar on the non-magnetic layer to form a majority gate device.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: May 28, 2013
    Inventors: Dmitri E. Nikonov, George I. Bourianoff, Ajey P. Jacob
  • Patent number: 8432731
    Abstract: A method, system, and apparatus magnetically coupled electrostatically shiftable memory device and method are disclosed. In one embodiment, a method includes electrostatically decoupling a separate structure and a surface that are magnetically coupled (e.g., an electrostatic force to decouple the separate structure and the surface is generated with an electrode), shifting the separate structure between the surface and a other surface with the electrostatic force (e.g., shifting the separate structure moves the entire separate structure), and magnetically coupling the separate structure to the other surface.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: April 30, 2013
    Inventors: Sridhar Kasichainula, Kishore Kasichainula, Mike Daneman
  • Patent number: 8391041
    Abstract: The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: March 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Shota Okayama
  • Patent number: 8374020
    Abstract: A system includes a continuous thin-film ferromagnetic layer, N magnetic tunnel junction (MTJ) devices, and N write structures. The continuous thin-film ferromagnetic layer includes N modified regions. Each of the N modified regions is configured to stabilize a magnetic domain wall located in the continuous thin-film ferromagnetic layer. Each of the N MTJ devices includes one of N portions of the continuous thin-film ferromagnetic layer. Adjacent MTJ devices of the N MTJ devices are separated by one of the N modified regions. Each of the N write structures is configured to receive current and generate a magnetic field that magnetizes a different one of the N portions of the continuous thin-film ferromagnetic layer. N is an integer greater than 2.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: February 12, 2013
    Assignee: Honeywell International Inc.
    Inventor: Romney R. Katti
  • Publication number: 20120314468
    Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 13, 2012
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Chang Hua Siau, Bruce Bateman
  • Publication number: 20120287696
    Abstract: A storage element includes a storage layer having a magnetization perpendicular to a layer surface and storing information according to a magnetization state of a magnetic material; a fixed magnetization layer having the magnetization as a reference of the information of the storage layer and perpendicular to the layer surface; an interlayer formed of a nonmagnetic material and interposed between the storage layer and the fixed magnetization layer; a coercive force enhancement layer adjacent to the storage layer, opposite to the interlayer, and formed of Cr, Ru, W, Si, or Mn; and a spin barrier layer formed of an oxide, adjacent to the coercive force enhancement layer, and opposite to the storage layer.
    Type: Application
    Filed: April 19, 2012
    Publication date: November 15, 2012
    Applicant: SONY CORPORATION
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida, Tetsuya Asayama
  • Patent number: 8289746
    Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: October 16, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
  • Patent number: 8279667
    Abstract: Provided are nonvolatile memory devices and program methods thereof, an integrated circuit memory system includes a memory array comprising at least one magnetic track, each of the at least one magnetic track including a plurality of magnetic domains and at least one read/write unit coupled thereto, decoding circuitry coupled to the memory array that is operable to select at least one of the magnetic domains, a read/write controller coupled to the memory array that is operable to read data from at least one of the plurality of magnetic domains and to write data to at least one of the plurality of magnetic domains via the at least one read/write unit coupled to each of the at least one magnetic track, and a domain controller coupled to memory array that is operable to move data between the magnetic domains on each of the at least one magnetic track.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: October 2, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Jung Kim, Sang Beom Kang, Chul Woo Park, Hyun Ho Choi, Jong Wan Kim, Young Pill Kim, Sung Chul Lee
  • Patent number: 8279666
    Abstract: A magnetic device includes a magnetic reference layer with a fixed magnetization direction located either in the plane of the layer or perpendicular to the plane of the layer, a magnetic storage layer with a variable magnetization direction, a non-magnetic spacer separating the reference layer and the storage layer and a magnetic spin polarizing layer with a magnetization perpendicular to that of the reference layer, and located out of the plane of the spin polarizing layer if the magnetization of the reference layer is directed in the plane of the reference layer or in the plane of the spin polarizing layer if the magnetization of the reference layer is directed perpendicular to the plane of the reference layer. The spin transfer coefficient between the reference layer and the storage layer is higher than the spin transfer coefficient between the spin polarizing layer and the storage layer.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: October 2, 2012
    Assignees: Institut Polytechnique de Grenoble, Le Centre National de la Recherche Scientifique, Le Commissariat a l'Energie Atomique et aux Energies Altenatives
    Inventors: Bernard Dieny, Cristian Papusoi, Ursula Ebels, Dimitri Houssameddine, Liliana Buda-Prejbeanu, Ricardo Sousa