Fusible Patents (Class 365/96)
  • Patent number: 11379580
    Abstract: An array of non-volatile memory cells includes rows and columns. A volatile storage circuit provides addressable units of storage. A control circuit reads first type data and second type data from one or more of the rows and multiple ones of the columns of the array of non-volatile memory cells. The control circuit stores the first type data and second type data read from each row in one or more addressable units of storage of the volatile storage. A security circuit reads first data from the one or more of the addressable units of the volatile storage and selects from the first data, the second type data that includes one or more bits of each of the one or more of the addressable units. The security circuit performs an integrity check on the selected second type data, and generates an alert signal that indicates a security violation in response to failure of the integrity check.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: July 5, 2022
    Assignee: XILINX, INC.
    Inventors: James D. Wesselkamper, Edward S. Peterson, Jason J. Moore, Steven E. McNeil, Roger D. Flateau, Jr., Danny Tsung-Heng Wu, Boon Y. Ang
  • Patent number: 11362097
    Abstract: A semiconductor memory device includes at least an OTP cell having a transistor and a PN junction diode. The OTP cell further includes a substrate having a first conductivity type, and a source and a drain in the substrate. The source includes a source doping region having the first conductivity type. The drain includes a drain doping region having a second conductivity type opposite to the first conductivity type. A gate is disposed on the substrate between the source and the drain. The source further includes a pocket doping region having the second conductivity type under the gate. The pocket doping region and the source doping region constitute the PN junction diode.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: June 14, 2022
    Assignee: HeFeChip Corporation Limited
    Inventor: Geeng-Chuan Chern
  • Patent number: 11335424
    Abstract: A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Yao-Jen Yang, Min-Shin Wu
  • Patent number: 11335636
    Abstract: The disclosed embodiments provide gradual breakdown memory cell having multiple different dielectrics. In some embodiments, a multi-level one-time-programmable memory cell, comprises: a top electrode; a bottom electrode; and a plurality of dielectric layers disposed between the top and bottom electrodes, wherein at least one of the following is true: at least two of the dielectric layers are of different dielectric materials; and the multi-level one-time-programmable memory cell comprises at least one metal layer, wherein each metal layer is disposed between two of the dielectric layers.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 17, 2022
    Assignee: Hefei Reliance Memory Limited
    Inventor: Liang Zhao
  • Patent number: 11328783
    Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: May 10, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Jong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
  • Patent number: 11328784
    Abstract: A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 10, 2022
    Assignee: NXP USA, INC.
    Inventors: Padmaraj Sanjeevarao, Jon Scott Choy
  • Patent number: 11322546
    Abstract: A single memory cell array is formed to maintain current delivery and mitigate current spike through the deposition of resistive materials in two or more regions of the array, including at least one region of memory cells nearer to contacts on the conductive lines and at least one region of memory cells farther from the contacts, where the contacts connect the conductive lines to the current source. Higher and lower resistive materials are introduced during the formation of the memory cells and the conductive lines based on the boundaries and dimensions of the two or more regions using a photo mask. Multiple memory cell arrays formed to maintain current delivery and mitigate current spike can be arranged into a three-dimensional memory cell array. The regions of memory cells in each memory cell array can vary depending on resistance at the contacts on the conductive lines that provide access to the memory cells, where the resistance can vary from one memory cell array to another.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Shafqat Ahmed, Kiran Pangal
  • Patent number: 11302735
    Abstract: An image sensor includes a substrate configured to include a plurality of pixels, each pixel including a photodiode formed in the substrate, a plurality of deep trench isolation (DTI) structures formed in the substrate to optically isolate each of the plurality of pixels from neighboring pixels, and a transparent electrode layer arranged over the photodiode and electrically connected to the plurality of DTI structures.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: April 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Yun Hui Yang
  • Patent number: 11295826
    Abstract: A method and apparatus are described for OTP control logic with randomization for sensing and writing fuse values. In an embodiment, OTP control logic has an address counter to determine an address of a fuse to be read from an OTP fuse box and a corresponding address of a shadow register, a fuse box addressing circuit to read a fuse value from a fuse of the fuse box, a clock circuit coupled to the address counter to provide a clock signal to the address counter, and a randomization circuit to interrupt the clock signal at random times to prevent the address counter from determining a next address in response to the clock signal.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: April 5, 2022
    Assignee: NXP B.V.
    Inventors: Jorge Ernesto Perez Chamorro, Michael Elsasser
  • Patent number: 11257557
    Abstract: A one-time programmable (OTP) memory cell is disclosed, which comprises an electric fuse structure, an anti-fuse transistor and a word select transistor. One end of the electric fuse structure is electrically connected to a gate of the anti-fuse transistor to form a first port of the OTP memory cell, the other end of the electric fuse structure is electrically connected to a source of the anti-fuse transistor and is connected to a drain of the word select transistor, and a gate and a source of the word select transistor form a second port and a third port of the OTP memory cell respectively. The operation method of the OTP memory cell has the capability of one-time correction, expanding the practicability of the OTP memory cell.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: February 22, 2022
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Ying Yan, Jianming Jin
  • Patent number: 11250924
    Abstract: An OTP memory cell circuit includes a read access switch coupled to a fuse in a read current path to allow a read current to flow through the fuse during a read operation. The read access switch, which can be shut off in a write operation, is sized according to the read current to reduce leakage currents that can cause unreliable results. A diode circuit coupled to a node between the read access switch and the fuse provides a write current path through the fuse different from the read current path in the OTP memory cell circuit. The diode circuit is configured to drive, through the write current path including the fuse, a write current sufficient to blow the fuse in a write operation. The diode circuit occupies a smaller area than a write access transistor of comparable drive strength in the OTP memory cell circuit.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: February 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Hochul Lee, Anil Chowdary Kota, Anne Srikanth
  • Patent number: 11243828
    Abstract: A semiconductor system according to an embodiment includes: a semiconductor system including a normal memory cell array and a redundancy memory cell array for repairing a defective cell among memory cells within the normal memory cell array, and configured to output to an external a fail flag generated according to a number of fail bits within read data output from the redundancy memory cell array; and a host configured to store an address corresponding to the read data into a selected register group from among a plurality of register groups, the selected register group being matched to the fail flag.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Jae Yong Kang
  • Patent number: 11222921
    Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey, Willy Rachmady
  • Patent number: 11222706
    Abstract: An OTP memory cell circuit includes a read access switch coupled to a fuse in a read current path to allow a read current to flow through the fuse during a read operation. The read access switch, which can be shut off in a write operation, is sized according to the read current to reduce leakage currents that can cause unreliable results. A diode circuit coupled to a node between the read access switch and the fuse provides a write current path through the fuse different from the read current path in the OTP memory cell circuit. The diode circuit is configured to drive, through the write current path including the fuse, a write current sufficient to blow the fuse in a write operation. The diode circuit occupies a smaller area than a write access transistor of comparable drive strength in the OTP memory cell circuit.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: January 11, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Hochul Lee, Anil Chowdary Kota, Anne Srikanth
  • Patent number: 11201161
    Abstract: An eFuse memory cell, an eFuse memory array and a using method thereof, and an eFuse system are provided.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: December 14, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Xiaohua Li
  • Patent number: 11183257
    Abstract: The present application discloses a programmable memory, wherein an anti-fuse unit thereof is formed by adding an efuse between an anti-fuse programming transistor and a control transistor of a conventional anti-fuse unit such that the anti-fuse unit can be programmed twice, that is, normal programming can be implemented by breaking down a gate-source insulation layer of the anti-fuse programming transistor, and correction programming can be further implemented by fusing the efuse such that correction programming can be performed on a normal programming result, thereby changing a logical state of the normally programmed anti-fuse unit. For the programmable memory, a reprogramming method can be directly used to correct an error bit, thereby simplifying circuit and layout designs, resulting in a smaller layout area and higher reliability, increasing the applicability and flexibility, while retaining original features of reliable and safe data of the anti-fuse unit.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: November 23, 2021
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Ying Yan, Jianming Jin
  • Patent number: 11145379
    Abstract: An eFuse cell array includes a first unit cell and a second unit cell, each including a PN diode, a cell read transistor, and a fuse element. A first placement order of the PN diode, the cell read transistor, and the fuse element in the first unit cell is reversed with respect to a second placement order of the PN diode, the cell read transistor, and the fuse element in the second unit cell.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: October 12, 2021
    Assignee: Key Foundry Co., Ltd.
    Inventors: Jong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
  • Patent number: 11145387
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Alan J. Wilson
  • Patent number: 11114176
    Abstract: A One Time Programmable (OTP) memory, includes: a first driver coupled to a reference cell by a first bit line; a second driver coupled to an OTP cell by a second bit line; and a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to a logic circuit configured to control the first driver and the second driver.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 7, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Hochul Lee, Anil Chowdary Kota, Keejong Kim
  • Patent number: 11114140
    Abstract: A semiconductor device includes at least a one-time programmable (OTP) physically unclonable function (PUF) unit cell with the PUF unit cell coupled to a bit line and a source line and includes an encode transistor is proposed. An encode enable transistor directly couples the bit line and the source line. A path programming the encode transistor is different from a path reading the encode transistor.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: September 7, 2021
    Assignee: HeFeChip Corporation Limited
    Inventor: Geeng-Chuan Chern
  • Patent number: 11049539
    Abstract: A magnetoresistive random access memory (MRAM) array has a corresponding MRAM cell, including a Magnetic Tunnel Junction (MTJ), at an intersection of each row and column. A first row of the array is configured as a single one-time-programmable (OTP) row, wherein a first MRAM cell in a first column is connected to a second MRAM cell in a second column. A first MTJ of the first MRAM cell is connected to a first bit line of the first column, and a second MTJ of the second MRAM cell is not connected to a second bit line of the second column. During a write to the first MRAM cell, write circuitry is configured to connect the first and second bit lines and the corresponding source lines such that the select transistors in the first and second MRAM cells are connected in parallel to drive a write current through the first MTJ.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: June 29, 2021
    Assignee: NXP USA, Inc.
    Inventors: Padmaraj Sanjeevarao, Jon Scott Choy, Anirban Roy
  • Patent number: 11024398
    Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: June 1, 2021
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Jong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
  • Patent number: 11011250
    Abstract: Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, Alan J. Wilson
  • Patent number: 10991442
    Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-Yu Chou, Yu-Ti Su
  • Patent number: 10984878
    Abstract: A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a first signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a second signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the first signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the second signal; a first word line to selectively provide the first signal; a second word line to selectively provide the second signal; and a bit line for sensing the first state or the second state.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: April 20, 2021
    Inventors: Meng-Sheng Chang, Yao-Jen Yang, Min-Shin Wu
  • Patent number: 10929588
    Abstract: A method of generating an IC layout diagram includes intersecting an active region with first and second gate regions to define locations of first and second anti-fuse structures, overlying the first gate region with a first conductive region to define a location of an electrical connection between the first conductive region and first gate region, and overlying the second gate region with a second conductive region to define a location of an electrical connection between the second conductive region and second gate region. The first and second conductive regions are aligned along a direction perpendicular to a direction along which the first and second gate regions extend, and at least one of intersecting the active region with the first gate region, intersecting the active region with the second gate region, overlying the first gate region, or overlying the second gate region is executed by a processor of a computer.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Chen-Ming Hung, Shao-Yu Chou, Yao-Jen Yang
  • Patent number: 10894403
    Abstract: An apparatus includes a substrate, a transistor provided on the substrate and connected to a first terminal supplied with a first voltage, an anti-fuse element provided on the substrate and connected between the transistor and a second terminal supplied with a second voltage, a first resistive element provided on the substrate and connected in parallel to the anti-fuse element and between the transistor and the second terminal, and an adjusting unit provided on the substrate and configured to function so as to reduce an influence of variation in resistance of the first resistive element in reading out of information from the anti-fuse element.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: January 19, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazunari Fujii, Naoki Isoda, Toshio Negishi, Wataru Endo
  • Patent number: 10879171
    Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: December 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang
  • Patent number: 10861524
    Abstract: A magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, wherein each MRAM cell has a select transistor and a Magnetic Tunnel Junction (MTJ). A plurality of rows of the MRAM array is configured as a single one-time-programmable (OTP) row having OTP cells, wherein the corresponding word lines of each row of the plurality of rows are electrically connected. In each column of the single OTP row, source electrodes of the select transistors in the corresponding MRAM cells in the column of the single OTP row are coupled to the corresponding source line, drain electrodes of the select transistors in the corresponding MRAM cells in the column of the single OTP row are electrically connected, and only a first MTJ of a first MRAM cell in the corresponding MRAM cells in the column of the single OTP row is connected to the corresponding bit line.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Anirban Roy, Jon Scott Choy
  • Patent number: 10847236
    Abstract: A memory cell includes a first anti-fuse element, a first select transistor, a second anti-fuse element, a second select transistor, and a sensing control circuit. The first anti-fuse element is coupled to an anti-fuse control line, and the first select transistor transmits a voltage between a first bit line and the first anti-fuse element according to a voltage on the word line. The second anti-fuse element is coupled to the anti-fuse control line. The second select transistor transmits a voltage between a second bit line and the second anti-fuse element according to the voltage on the word line. The sensing control circuit provides a discharging path to a system voltage terminal from the first select transistor or the second select transistor according to states of the first anti-fuse element and the second anti-fuse element during a read operation.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 24, 2020
    Assignee: eMemory Technology Inc.
    Inventor: Dung Le Tan Hoang
  • Patent number: 10841523
    Abstract: Disclosed are devices, systems and methods for reading out data at a high speed. The data output circuit includes a line memory configured to latch a digital signal, and output the latched digital signal to a pair of column lines in response to an output control signal, a precharge circuit configured to precharge the pair of column lines with a first precharge voltage level in response to a first precharge signal, a charge circuit configured to charge the pair of column lines with a voltage, a charge controller configured to charge the charge circuit with a second precharge voltage level in response to a second precharge signal, and a sense amplifier configured to amplify an output voltage of the charge circuit in response to a sensing enable signal.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Tae Gyu Kim
  • Patent number: 10839885
    Abstract: Steering logic circuitry includes bit-flipping logic that determines a first neighboring redundant word line adjacent to a redundant word line of a memory bank, which also includes normal word lines. Redundant word lines include main word lines, each of which includes paired word lines. Each paired word line includes two redundant word lines. The steering logic circuitry also includes border determination logic that determines whether the redundant word line is on a border between the redundant word lines and an end of the memory bank or the normal word lines. The steering logic circuitry further includes main word line steering logic that determines a neighboring main word line that a second neighboring redundant word line adjacent to the redundant word line is disposed in, and paired word line steering logic that determines a neighboring paired word line that the second neighboring redundant word line is disposed in.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Joosang Lee
  • Patent number: 10832791
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Alan J. Wilson
  • Patent number: 10825536
    Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for programming a device having one or more programmable circuits to implement, for example, a machine learning model. One example apparatus generally includes a plurality of word lines, a plurality of bit lines, and an array of programmable circuits. Each programmable circuit is coupled to a corresponding word line in the plurality of word lines and to a corresponding bit line in the plurality of bit lines and comprises: a main resistor coupled between the corresponding word line and the corresponding bit line, an auxiliary resistor, a fuse coupled in series with the auxiliary resistor, wherein the auxiliary resistor and the fuse are coupled between the corresponding word line and the corresponding bit line, and a programming circuit configured to selectively blow the fuse.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 3, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Haining Yang, Periannan Chidambaram
  • Patent number: 10818336
    Abstract: The apparatus includes a row hammer refresh (RHR) circuit configured to steal a first refresh cycle to implement a first RHR segment; and steal a second refresh cycle after one or more operating cycles, the second refresh cycle to implement a second RHR segment.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Joshua E. Alzheimer
  • Patent number: 10811119
    Abstract: A post package repair (PPR) method is disclosed. The PPR method includes the following operations: receiving a first PPR signal and a second PPR signal, in which the first PPR signal corresponds to a first PPR mode, and the second PPR signal corresponds to a second PPR mode; generating a first valid signal and a second valid signal according to the first PPR signal and the second PPR signal, in which only one of the first valid signal and the second valid signal comprises a valid information when both of the first PPR signal and the second PPR signal comprise an enabled information; in which when the first valid signal comprises the valid information, the first PPR mode is executed, and when the second valid signal comprises the valid information, the second PPR mode is executed.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: October 20, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Wei Shen
  • Patent number: 10803967
    Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-Yu Chou, Yu-Ti Su
  • Patent number: 10770159
    Abstract: An antifuse device is disclosed. The antifuse device includes a plurality of active regions, a plurality of word lines extending along a first direction and cut through the active regions, a plurality of bit lines and a plurality of source lines extending along a second direction and stride across the active regions. The bit lines and the source lines are arranged alternatively along the first direction. Plural antifuse capacitors are disposed along the source lines and connected between the source lines and the active regions.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: September 8, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tsai-Yu Huang, Pin-Yao Wang
  • Patent number: 10741246
    Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: August 11, 2020
    Assignee: Arm Limited
    Inventors: Mudit Bhargava, Brian Tracy Cline, George McNeil Lattimore, Bal S. Sandhu
  • Patent number: 10714242
    Abstract: An electrical resistor element, system, and method related thereto, wherein the electrical resistor element includes a tunable resistance. The electrical resistor element comprises a first contact electrode, a second contact electrode and a ferroelectric layer arranged between the first contact electrode and the second contact electrode. The ferroelectric layer comprises a first area having a first polarization direction and a second area having a second polarization direction. The first polarization direction is different to the second polarization direction. The ferroelectric layer further comprises a domain wall between the first area and the second area. The electrical resistor element further comprises a first pinning element configured to stabilize the first polarization direction of the ferroelectric layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Stefan Abel, Jean Fompeyrine, Johannes Gooth, Bernd Gotsmann, Fabian Menges
  • Patent number: 10685690
    Abstract: A memory device includes a bank that includes first memory cells connected to a first column selection line and second memory cells connected to a second column selection line, a first column decoder that selects the first memory cells by transmitting a first column selection signal in a first direction through the first column selection line, and a second column decoder that selects the second memory cells by transmitting a second column selection signal in a second direction opposite to the first direction through the second column selection line. The first column decoder includes a first register that stores a first fail column address of the first memory cells, and a second register that stores a second fail column address of the second memory cells.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-Jin Kim, Huikap Yang
  • Patent number: 10643726
    Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-yu Chou, Yu-Ti Su
  • Patent number: 10636510
    Abstract: A semiconductor device includes a fuse array circuit including a plurality of fuse cell arrays, and configured to output fuse data based on one or more fuses that have been ruptured or not within a fuse cell array; and a fuse control circuit configured to compare the fuse data and one or more failure addresses, and re-perform a rupture operation for the fuse cell array when the fuse data and the failure addresses indicate a difference between the fuse data and the failure addresses.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventor: Joohyeon Lee
  • Patent number: 10623192
    Abstract: Gate oxide breakdown in the programming element of an OTP (One-Time Programmable) memory cell can vary widely. The resulting large variations in the conductivity of the programmed memory cells in an OTP memory cell array is used for a PUF (Physically Unclonable Function). A method of obtaining a PUF value from an OTP memory cell array is described.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 14, 2020
    Assignee: Synopsys, Inc.
    Inventor: Larry Wang
  • Patent number: 10607686
    Abstract: An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a fast detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hiroshi Akamatsu
  • Patent number: 10535602
    Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Sheng Chang, Shao-Tung Peng, Shao-Yu Chou, Liang Chuan Chang, Yao-Jen Yang
  • Patent number: 10510427
    Abstract: The present invention relates to the technical field of integrated circuits. Disclosed is a one-time programmable memory with a high reliability and a low reading voltage, comprising: a first MOS transistor, a second MOS transistor, and an antifuse component. A gate terminal of the first MOS transistor is connected to a second connecting line (WS), a first connection terminal of the first MOS transistor is connected to the antifuse component, the antifuse component is connected to a first connecting line (WP), and a second connection terminal of the first MOS transistor is connected to a third connecting line (BL). A first connection terminal of the second MOS transistor is connected to a fourth connecting line (BR), and a second connection terminal of the second MOS transistor is connected to a third connecting line (BL). The invention further comprises a voltage limiting device with a control terminal and two connection terminals.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: December 17, 2019
    Assignee: SICHUAN KILOWAY ELECTRONICS INC.
    Inventors: Xuyang Liao, Junhua Mao, Jack Z. Peng
  • Patent number: 10438675
    Abstract: Memory programming methods and memory systems are described. One example memory programming method includes programming a plurality of main cells of a main memory and erasing a plurality of second main cells of the main memory. The memory programming method further includes first re-writing one-time programmed data within a plurality of first one-time programmed cells of a one-time programmed memory during the programming and second re-writing one-time programmed data within a plurality of second one-time programmed cells of a one-time programmed memory during the erasing. Additional method and apparatus are described.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Takafumi Kunihiro
  • Patent number: 10283210
    Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-Yu Chou, Yu-Ti Su
  • Patent number: 10109338
    Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs pre-order address signals, post-order address signals, and an update signal including pulses periodically generated. The semiconductor device generates internal address signals counted by a predetermined number of times according to a combination of the pre-order address signals and a combination of the post-order address signals in response to a pulse of the update signal. The semiconductor device also performs a refresh operation according to a combination of the internal address signals.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: October 23, 2018
    Assignee: SK hynix Inc.
    Inventor: Haeng Seon Chae