Fusible Patents (Class 365/96)
  • Patent number: 12090757
    Abstract: A heater device with a memory unit includes a first transistor, a second transistor, a memory unit and a heater. The first terminal of the second transistor and the first terminal of the first transistor are electrically connected to each other. The memory unit is electrically connected to the second terminal of the first transistor. The heater is electrically connected to the second terminal of the second transistor.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: September 17, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Po-Han Huang, Tao-Sheng Chang, Te-Yu Lee
  • Patent number: 12094818
    Abstract: A fuse structure and a method for manufacturing the same are provided. The fuse structure includes a substrate; a fin, located on the substrate and including a first fin region; and a gate stack structure, surrounding the top and side walls of the first fin region. The gate stack structure includes a first gate stack and a second gate stack. The first gate stack covers the first fin region, the second gate stack covers the first gate stack. The first gate stack is configured to receive a first gate voltage, the second gate stack is configured to receive a second gate voltage, and the first gate voltage is greater than the second gate voltage. The fuse structure reduces the area of the fuse unit and increase the integration level of the fuse circuit.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: September 17, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xiong LI
  • Patent number: 12087378
    Abstract: Systems, devices, and methods are described herein for a programmable memory array. A programmable memory system includes an array of programmable memory bit cells. A memory bit cell of the array includes a first transistor of a first type controlled by a bit line, a second transistor of a second type responsive to a first word line and a second word line via a logic gate, and a third transistor of the second type responsive to the word line. The first word line is positioned substantially perpendicular to the bit line, and the second word line is positioned substantially parallel to the bit line. The first word line is activated via an X portion of an address. While the second word line is activated via a Y portion of the address.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Sheng Chang, Yoshitaka Yamauchi, Perng-Fei Yuh
  • Patent number: 12027204
    Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
  • Patent number: 11983417
    Abstract: A power-on read circuit includes a power voltage detector, a first voltage booster, a voltage selector, a reference voltage generator and a read voltage generator. The power voltage detector detects a power voltage to generate a control signal. The first voltage booster generates a first boosted voltage according to the control signal. The voltage selector selects the power voltage or the first boosted voltage to generate a selected voltage. The reference voltage generator receives the selected voltage as an operating power source, and generates a reference voltage based on the selected voltage according to the control signal. The read voltage generator generates a second boosted voltage according to the reference voltage and a clock signal, and generate a read voltage based on the second boosted voltage according to the control signal. The read voltage is provided to a memory cell array to perform a data reading operation.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: May 14, 2024
    Assignee: Winbond Electronics Corp.
    Inventor: Chung-Zen Chen
  • Patent number: 11975536
    Abstract: An element substrate including a liquid discharge element, comprising a memory element capable of storing individual information of the element substrate by a write, the memory element being configured to change an impedance value by the write, a plurality of current supply elements capable of supplying a current to the memory element, and a determination unit configured to determine presence/absence of the write based on a voltage generated in the memory element by the current selectively supplied from the plurality of current supply elements, wherein the plurality of current supply elements constitute a part of a current mirror circuit and each supply the current in an amount according to a size ratio to the memory element.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: May 7, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshio Negishi, Yasuhiro Soeda
  • Patent number: 11978521
    Abstract: Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods are disclosed. An apparatus includes a fuse, a first driver circuit, and a second driver circuit. The fuse is configured to store a bit of information. The first driver circuit includes a first input terminal electrically connected to the fuse and a first output terminal electrically connected to a first latch input terminal. The second driver circuit includes a second input terminal electrically connected to the fuse and a second output terminal electrically connected to a second latch input terminal. The second latch input terminal is electrically isolated from the first latch input terminal by the first driver circuit and the second driver circuit.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: May 7, 2024
    Assignee: Micron Technologies, Inc.
    Inventor: Liang Liu
  • Patent number: 11955476
    Abstract: A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: April 9, 2024
    Assignee: SCHOTTKY LSI, INC.
    Inventor: Augustine Wei-Chun Chang
  • Patent number: 11930636
    Abstract: Transistor antifuses are disclosed. An apparatus may include an antifuse that may be configurable either as a short between a first node and a second node or as an open between the first node and the second node. The antifuse may include a selection transistor and an antifuse transistor. A source or drain of the selection transistor may be electrically coupled to the first node. A gate of the selection transistor may be configured to receive a selection voltage. A gate of the antifuse transistor may be electrically coupled the other of the source or drain of the selection transistor. A source or drain of the antifuse transistor may be electrically coupled to the second node. Associated devices, systems, and methods are also disclosed.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, James S. Rehmeyer, Toshihiko Miyashita
  • Patent number: 11894082
    Abstract: Embodiments of the present disclosure relate to the field of semiconductor technology, and provide an anti-fuse memory and a control method thereof. The anti-fuse memory is configured to generate a programming pulse signal based on a row strobe signal, a word line of the anti-fuse memory array is configured to receive the row strobe signal, and the anti-fuse memory array is programmed in response to the programming pulse signal. The embodiments of the present disclosure are at least advantageous to improving accuracy of reading data from the anti-fuse memory array and improving yield of the anti-fuse memory.
    Type: Grant
    Filed: April 2, 2022
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Rumin Ji
  • Patent number: 11869608
    Abstract: An anti-fuse unit and an anti-fuse array. The anti-fuse unit includes an anti-fuse device and a diode. An anode of the anti-fuse device is electrically connected with a bit line, a cathode of the anti-fuse device is electrically connected with an anode of the diode, and a cathode of the diode is electrically connected with a word line.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: ChihCheng Liu
  • Patent number: 11862264
    Abstract: A memory circuit includes a sense amplifier coupled to a non-volatile memory cell, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The sense amplifier includes a comparator. The comparator includes a first input terminal coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage, a second input terminal configured to receive a second voltage, and a first output terminal configured to output a first output signal. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier. The detection circuit includes a first inverter. A first input terminal of the first inverter is configured to receive the first output signal. A first output terminal of the first inverter is configured to generate an inverted first output signal.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hao Chang, Gu-Huan Li, Shao-Yu Chou
  • Patent number: 11854622
    Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 26, 2023
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Seong Jun Park, Jong Min Cho, Sung Bum Park, Kee Sik Ahn
  • Patent number: 11854633
    Abstract: A state detection circuit of an anti-fuse memory cell includes a first switching element, having a first end connected to a power supply, a second end connected to a first node, and a control end connected to a controller; an anti-fuse memory cell array including a plurality of anti-fuse memory cell sub-arrays, bit lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the first node, and word lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the controller; and a comparator, having a first input end connected to the first node, and a second input end connected to a reference voltage.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: December 26, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Rumin Ji
  • Patent number: 11848061
    Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: December 19, 2023
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Seong Jun Park, Sung Bum Park, Kee Sik Ahn
  • Patent number: 11842780
    Abstract: A semiconductor device capable of efficiently increasing a capacity of a mounted storage element while achieving space saving, and an electronic apparatus including this semiconductor device are provided. The semiconductor device includes a storage element including a filament that has a first conductive layer, a second conductive layer, and an insulation layer. The first conductive layer and the second conductive layer are stacked with at least the insulation layer interposed between the first conductive layer and the second conductive layer. The filament obtains at least three identifiable resistance states by changing a combination of a state of the first conductive layer, a state of the second conductive layer, and a state of the insulation layer. The semiconductor device further includes a writing unit that produces the at least three identifiable resistance states by applying a blow current to the storage element.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: December 12, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Mikio Oka, Yasuo Kanda, Kenji Noguchi
  • Patent number: 11837300
    Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: December 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou, Yih Wang
  • Patent number: 11823948
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: November 21, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Uzma Rana, Anthony K. Stamper, Steven M. Shank, Brett T. Cucci
  • Patent number: 11804281
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: October 31, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Donald M. Morgan, Alan J. Wilson, Bryan D. Kerstetter, John D. Porter
  • Patent number: 11791006
    Abstract: A memory circuit includes a bank of non-volatile memory (NVM) devices, a plurality of high-voltage (HV) drivers, a global HV power switch configured to generate a HV power signal, and a plurality of HV power switches coupled to the global HV switch. A first HV power switch of the plurality of HV power switches is coupled to each HV driver of the plurality of HV drivers, the first HV power switch of the plurality of HV power switches is configured to output a power signal responsive to the HV power signal, and each HV driver of the plurality of HV drivers is configured to output a HV activation signal to a corresponding column of the bank of NVM devices responsive to the power signal.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gu-Huan Li, Chen-Ming Hung, Yu-Der Chih
  • Patent number: 11783905
    Abstract: When a driving circuit of an anti-fuse memory device programs a selected anti-fuse memory cell, voltage differences between unselected bit lines and unselected anti-fuse control lines would be eliminated or decreased to an acceptable value by floating unselected anti-fuse control lines or by applying a second control line voltage to the unselected anti-fuse control lines. Leakage currents flowing from unselected bit lines through ruptured anti-fuse transistors of the anti-fuse memory device to the unselected anti-fuse control lines would be decreased or eliminated, and program disturbance would be avoided.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: October 10, 2023
    Assignee: eMemory Technology Inc.
    Inventors: Chieh-Tse Lee, Ting-Yang Yen, Cheng-Da Huang, Chun-Hung Lin
  • Patent number: 11756647
    Abstract: Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yu Huang, Chia-En Huang, Cheng Hung Lee, Hua-Tai Shieh
  • Patent number: 11758714
    Abstract: A semiconductor structure includes first and second transistors each having a source terminal, a drain terminal, and a gate terminal. The semiconductor structure further includes a program line; a first metal plate over the first and the second transistors; a first insulator over the first metal plate; a second metal plate over the first insulator; a second insulator over the second metal plate; and a third metal plate over the second insulator. The first metal plate, the first insulator, and the second metal plate form a first anti-fuse element. The second metal plate, the second insulator, and the third metal plate form a second anti-fuse element. The source terminal of the first transistor is electrically connected to the first metal plate. The source terminal of the second transistor is electrically connected to the third metal plate. The program line is electrically connected to the second metal plate.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11744064
    Abstract: A semiconductor circuit according to the present disclosure includes: a first memory element including a first terminal, a second terminal coupled to a first node, and a tunnel barrier film, and configured to store information by breaking the tunnel barrier film; a first transistor including a drain coupled to the first node, a source, a gate, and a back gate coupled to a second node; and a second transistor including a drain, a source coupled to the second node, and a gate coupled to the first node.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: August 29, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yasuo Kanda
  • Patent number: 11699993
    Abstract: Methods, systems, and devices for signal sampling with offset calibration are described. For example, sampling circuitry may include an input pair of transistors where input signals may be provided to gate nodes of the transistors, and an output signal may be generated based on a comparison of voltages of drain nodes of the transistors. In some examples, source nodes of the transistors may be coupled with each other, such as via a resistance, and each source node may be configured to be coupled with a ground node. In some examples, a conductive path between the source nodes may be coupled with one or more switching components configurable for further coupling of the source nodes with the ground node. In some examples, enabling such switching components may add an electrical characteristic (e.g., capacitance) to the conductive path between the source nodes, which may be configurable to mitigate sampling circuitry imbalances.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Martin Brox, Thomas Hein, Mani Balakrishnan
  • Patent number: 11670390
    Abstract: A re-programmable integrated circuit (IC) includes a plurality of non-volatile memory elements, each including a fuse portion initially configured to have either a first resistance value or a second resistance value. Re-programming circuitry includes a controllable element coupled to each fuse portion and selectively operable to cause an electrical current to flow through the fuse portion sufficient to cause that fuse portion to transition to an altered state having a resistance value greater than the first and second resistance values. Reference resistance circuitry is configurable between an initial state and a re-programmed state.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: June 6, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Allen Ball, Anand Seshadri
  • Patent number: 11626177
    Abstract: An anti-fuse sensing device and an operation method thereof are provided. The anti-fuse sensing device is adapted for sensing a resistance state of an anti-fuse. The anti-fuse sensing device includes a voltage generating circuit, a comparison circuit, and a sensing circuit. The voltage generating circuit is configured to generate a comparison voltage that changes with temperature. The comparison circuit is coupled to the voltage generating circuit to receive the comparison voltage. The comparison circuit is configured to compare the comparison voltage with a reference voltage, and convert a difference between the comparison voltage and the reference voltage into a bias voltage that changes with temperature. The sensing circuit is coupled to the comparison circuit to receive the bias voltage. The sensing circuit is configured to sense the resistance state of the anti-fuse according to the bias voltage.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 11, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Hang Chang
  • Patent number: 11615859
    Abstract: An OTP with ultra-low power read can be programmed with a minimum and a maximum program voltage. When programming within the range, the post-program OTP to pre-program resistance ratio can be larger than N, where N>50, so that more sensing techniques, such as single-end sensing, can be used to reduce read current. At least one of the OTP cells can be coupled to a common bitline, which can be further coupled to a first supply voltage lines via a plurality of datalines. The resistance in the at least one OTP cell can be evaluated by strobing at least one comparator output of the discharging bitline/dataline.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: March 28, 2023
    Assignee: Attopsemi Technology Co., LTD
    Inventor: Shine C. Chung
  • Patent number: 11574684
    Abstract: The present invention relates to a dynamic random access memory and a programming method therefor with two stages. In a first stage, a capacitor of a memory cell of the dynamic random access memory is broken down, so that the dynamic random access memory becomes a one-time programmable memory. In a second stage, a resistance of the capacitor that is broken down is reduced, so that state data of the memory cell can be more easily interpreted.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: February 7, 2023
    Assignee: NS Poles Technology Corp.
    Inventors: Chao Yang Chen, Ming Sheng Tung
  • Patent number: 11551770
    Abstract: An electronic device includes a row control circuit and a programming circuit. The row control circuit is suitable for activating a synthesis word line selection signal for enabling a first fuse cell and a second fuse cell in a first mode. In addition, the row control circuit is suitable for activating one of a first fuse access signal for storing fuse data in the first fuse cell or outputting the fuse data from the first fuse cell and a second fuse access signal for storing the fuse data in the second fuse cell or outputting the fuse data from the second fuse cell. The programming circuit is configured to store the fuse data in one of the first and second fuse cells based on the synthesis word line selection signal and the first and second fuse access signals in the first mode.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: January 10, 2023
    Assignee: SK hynix Inc.
    Inventor: Myung Ho Yang
  • Patent number: 11501051
    Abstract: A memory device includes at least one bit line, at least one word line, and at least one memory cell comprising a capacitor and a transistor. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The insulating material is configured to break down under a predetermined break-down voltage or higher applied between the first end and the second end.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Chien-Ying Chen
  • Patent number: 11444026
    Abstract: Circuits, methods, and devices for protecting against accidental fuse programming are discussed herein. For example, a fuse circuit may include a first switch electrically connected to a first point, a fuse electrically connected in series with the first switch, a first biasing circuit to control the first switch to enable programming of the fuse in response to a fuse programming event, a second switch electrically connected in series with the fuse between the fuse and a second point, and a second biasing circuit to control the second switch to enable programming of the fuse in response to the fuse programming event.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: September 13, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventors: Bo Zhou, Guillaume Alexandre Blin
  • Patent number: 11417668
    Abstract: An antifuse One-Time-Programmable memory cell includes a substrate, and a hybrid select transistor and a hybrid antifuse capacitor formed on the substrate. The hybrid select transistor includes a first gate dielectric layer formed on the substrate, wherein the first gate dielectric layer is thinner than 40 nm, a first high-voltage junction formed in the substrate, and a low-voltage junction formed in the substrate. The hybrid antifuse capacitor includes a second gate dielectric layer, wherein the second gate dielectric layer is thinner than 40 nm, which enables a low-voltage antifuse capacitor device, a second gate formed on the gate dielectric layer, a second high-voltage junction formed in the substrate, and a third high-voltage junction formed in the substrate.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: August 16, 2022
    Assignee: Zhuhai Chuangfeixin Technology Co., Ltd.
    Inventors: Li Li, Zhigang Wang
  • Patent number: 11379580
    Abstract: An array of non-volatile memory cells includes rows and columns. A volatile storage circuit provides addressable units of storage. A control circuit reads first type data and second type data from one or more of the rows and multiple ones of the columns of the array of non-volatile memory cells. The control circuit stores the first type data and second type data read from each row in one or more addressable units of storage of the volatile storage. A security circuit reads first data from the one or more of the addressable units of the volatile storage and selects from the first data, the second type data that includes one or more bits of each of the one or more of the addressable units. The security circuit performs an integrity check on the selected second type data, and generates an alert signal that indicates a security violation in response to failure of the integrity check.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: July 5, 2022
    Assignee: XILINX, INC.
    Inventors: James D. Wesselkamper, Edward S. Peterson, Jason J. Moore, Steven E. McNeil, Roger D. Flateau, Jr., Danny Tsung-Heng Wu, Boon Y. Ang
  • Patent number: 11362097
    Abstract: A semiconductor memory device includes at least an OTP cell having a transistor and a PN junction diode. The OTP cell further includes a substrate having a first conductivity type, and a source and a drain in the substrate. The source includes a source doping region having the first conductivity type. The drain includes a drain doping region having a second conductivity type opposite to the first conductivity type. A gate is disposed on the substrate between the source and the drain. The source further includes a pocket doping region having the second conductivity type under the gate. The pocket doping region and the source doping region constitute the PN junction diode.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: June 14, 2022
    Assignee: HeFeChip Corporation Limited
    Inventor: Geeng-Chuan Chern
  • Patent number: 11335636
    Abstract: The disclosed embodiments provide gradual breakdown memory cell having multiple different dielectrics. In some embodiments, a multi-level one-time-programmable memory cell, comprises: a top electrode; a bottom electrode; and a plurality of dielectric layers disposed between the top and bottom electrodes, wherein at least one of the following is true: at least two of the dielectric layers are of different dielectric materials; and the multi-level one-time-programmable memory cell comprises at least one metal layer, wherein each metal layer is disposed between two of the dielectric layers.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 17, 2022
    Assignee: Hefei Reliance Memory Limited
    Inventor: Liang Zhao
  • Patent number: 11335424
    Abstract: A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Yao-Jen Yang, Min-Shin Wu
  • Patent number: 11328783
    Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: May 10, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Jong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
  • Patent number: 11328784
    Abstract: A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 10, 2022
    Assignee: NXP USA, INC.
    Inventors: Padmaraj Sanjeevarao, Jon Scott Choy
  • Patent number: 11322546
    Abstract: A single memory cell array is formed to maintain current delivery and mitigate current spike through the deposition of resistive materials in two or more regions of the array, including at least one region of memory cells nearer to contacts on the conductive lines and at least one region of memory cells farther from the contacts, where the contacts connect the conductive lines to the current source. Higher and lower resistive materials are introduced during the formation of the memory cells and the conductive lines based on the boundaries and dimensions of the two or more regions using a photo mask. Multiple memory cell arrays formed to maintain current delivery and mitigate current spike can be arranged into a three-dimensional memory cell array. The regions of memory cells in each memory cell array can vary depending on resistance at the contacts on the conductive lines that provide access to the memory cells, where the resistance can vary from one memory cell array to another.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Shafqat Ahmed, Kiran Pangal
  • Patent number: 11302735
    Abstract: An image sensor includes a substrate configured to include a plurality of pixels, each pixel including a photodiode formed in the substrate, a plurality of deep trench isolation (DTI) structures formed in the substrate to optically isolate each of the plurality of pixels from neighboring pixels, and a transparent electrode layer arranged over the photodiode and electrically connected to the plurality of DTI structures.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: April 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Yun Hui Yang
  • Patent number: 11295826
    Abstract: A method and apparatus are described for OTP control logic with randomization for sensing and writing fuse values. In an embodiment, OTP control logic has an address counter to determine an address of a fuse to be read from an OTP fuse box and a corresponding address of a shadow register, a fuse box addressing circuit to read a fuse value from a fuse of the fuse box, a clock circuit coupled to the address counter to provide a clock signal to the address counter, and a randomization circuit to interrupt the clock signal at random times to prevent the address counter from determining a next address in response to the clock signal.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: April 5, 2022
    Assignee: NXP B.V.
    Inventors: Jorge Ernesto Perez Chamorro, Michael Elsasser
  • Patent number: 11257557
    Abstract: A one-time programmable (OTP) memory cell is disclosed, which comprises an electric fuse structure, an anti-fuse transistor and a word select transistor. One end of the electric fuse structure is electrically connected to a gate of the anti-fuse transistor to form a first port of the OTP memory cell, the other end of the electric fuse structure is electrically connected to a source of the anti-fuse transistor and is connected to a drain of the word select transistor, and a gate and a source of the word select transistor form a second port and a third port of the OTP memory cell respectively. The operation method of the OTP memory cell has the capability of one-time correction, expanding the practicability of the OTP memory cell.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: February 22, 2022
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Ying Yan, Jianming Jin
  • Patent number: 11250924
    Abstract: An OTP memory cell circuit includes a read access switch coupled to a fuse in a read current path to allow a read current to flow through the fuse during a read operation. The read access switch, which can be shut off in a write operation, is sized according to the read current to reduce leakage currents that can cause unreliable results. A diode circuit coupled to a node between the read access switch and the fuse provides a write current path through the fuse different from the read current path in the OTP memory cell circuit. The diode circuit is configured to drive, through the write current path including the fuse, a write current sufficient to blow the fuse in a write operation. The diode circuit occupies a smaller area than a write access transistor of comparable drive strength in the OTP memory cell circuit.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: February 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Hochul Lee, Anil Chowdary Kota, Anne Srikanth
  • Patent number: 11243828
    Abstract: A semiconductor system according to an embodiment includes: a semiconductor system including a normal memory cell array and a redundancy memory cell array for repairing a defective cell among memory cells within the normal memory cell array, and configured to output to an external a fail flag generated according to a number of fail bits within read data output from the redundancy memory cell array; and a host configured to store an address corresponding to the read data into a selected register group from among a plurality of register groups, the selected register group being matched to the fail flag.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Jae Yong Kang
  • Patent number: 11222706
    Abstract: An OTP memory cell circuit includes a read access switch coupled to a fuse in a read current path to allow a read current to flow through the fuse during a read operation. The read access switch, which can be shut off in a write operation, is sized according to the read current to reduce leakage currents that can cause unreliable results. A diode circuit coupled to a node between the read access switch and the fuse provides a write current path through the fuse different from the read current path in the OTP memory cell circuit. The diode circuit is configured to drive, through the write current path including the fuse, a write current sufficient to blow the fuse in a write operation. The diode circuit occupies a smaller area than a write access transistor of comparable drive strength in the OTP memory cell circuit.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: January 11, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Hochul Lee, Anil Chowdary Kota, Anne Srikanth
  • Patent number: 11222921
    Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey, Willy Rachmady
  • Patent number: 11201161
    Abstract: An eFuse memory cell, an eFuse memory array and a using method thereof, and an eFuse system are provided.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: December 14, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Xiaohua Li
  • Patent number: 11183257
    Abstract: The present application discloses a programmable memory, wherein an anti-fuse unit thereof is formed by adding an efuse between an anti-fuse programming transistor and a control transistor of a conventional anti-fuse unit such that the anti-fuse unit can be programmed twice, that is, normal programming can be implemented by breaking down a gate-source insulation layer of the anti-fuse programming transistor, and correction programming can be further implemented by fusing the efuse such that correction programming can be performed on a normal programming result, thereby changing a logical state of the normally programmed anti-fuse unit. For the programmable memory, a reprogramming method can be directly used to correct an error bit, thereby simplifying circuit and layout designs, resulting in a smaller layout area and higher reliability, increasing the applicability and flexibility, while retaining original features of reliable and safe data of the anti-fuse unit.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: November 23, 2021
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Ying Yan, Jianming Jin
  • Patent number: RE50035
    Abstract: By stably separating a melting location of a fuse (3) from conductive layers (5A, 5B), reliable melting of the fuse (3) is enabled. A fuse (3) including a fuse body (3A) and two pads (3Ba, 3Bb) connected by this and two conductive layers (5A, 5B) individually connected to the two pads (3Ba, 3Bb) are formed in a multilayer structure on a semiconductor substrate (1). A length of the fuse body (3A) is defined so that the melting location of the fuse (3) becomes positioned in the fuse body (3A) away from the region overlapped on the conductive layer (5A or 5B) when an electrical stress is applied between two conductive layers (5A, 5B) and the fuse (3) is melted.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: July 9, 2024
    Assignee: Sony Group Corporation
    Inventors: Hideki Mori, Hirokazu Ejiri, Kenji Azami, Terukazu Ohno, Nobuyuki Yoshitake