Fusible Patents (Class 365/96)
  • Patent number: 10894403
    Abstract: An apparatus includes a substrate, a transistor provided on the substrate and connected to a first terminal supplied with a first voltage, an anti-fuse element provided on the substrate and connected between the transistor and a second terminal supplied with a second voltage, a first resistive element provided on the substrate and connected in parallel to the anti-fuse element and between the transistor and the second terminal, and an adjusting unit provided on the substrate and configured to function so as to reduce an influence of variation in resistance of the first resistive element in reading out of information from the anti-fuse element.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: January 19, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazunari Fujii, Naoki Isoda, Toshio Negishi, Wataru Endo
  • Patent number: 10879171
    Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: December 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang
  • Patent number: 10861524
    Abstract: A magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, wherein each MRAM cell has a select transistor and a Magnetic Tunnel Junction (MTJ). A plurality of rows of the MRAM array is configured as a single one-time-programmable (OTP) row having OTP cells, wherein the corresponding word lines of each row of the plurality of rows are electrically connected. In each column of the single OTP row, source electrodes of the select transistors in the corresponding MRAM cells in the column of the single OTP row are coupled to the corresponding source line, drain electrodes of the select transistors in the corresponding MRAM cells in the column of the single OTP row are electrically connected, and only a first MTJ of a first MRAM cell in the corresponding MRAM cells in the column of the single OTP row is connected to the corresponding bit line.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Anirban Roy, Jon Scott Choy
  • Patent number: 10847236
    Abstract: A memory cell includes a first anti-fuse element, a first select transistor, a second anti-fuse element, a second select transistor, and a sensing control circuit. The first anti-fuse element is coupled to an anti-fuse control line, and the first select transistor transmits a voltage between a first bit line and the first anti-fuse element according to a voltage on the word line. The second anti-fuse element is coupled to the anti-fuse control line. The second select transistor transmits a voltage between a second bit line and the second anti-fuse element according to the voltage on the word line. The sensing control circuit provides a discharging path to a system voltage terminal from the first select transistor or the second select transistor according to states of the first anti-fuse element and the second anti-fuse element during a read operation.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 24, 2020
    Assignee: eMemory Technology Inc.
    Inventor: Dung Le Tan Hoang
  • Patent number: 10841523
    Abstract: Disclosed are devices, systems and methods for reading out data at a high speed. The data output circuit includes a line memory configured to latch a digital signal, and output the latched digital signal to a pair of column lines in response to an output control signal, a precharge circuit configured to precharge the pair of column lines with a first precharge voltage level in response to a first precharge signal, a charge circuit configured to charge the pair of column lines with a voltage, a charge controller configured to charge the charge circuit with a second precharge voltage level in response to a second precharge signal, and a sense amplifier configured to amplify an output voltage of the charge circuit in response to a sensing enable signal.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Tae Gyu Kim
  • Patent number: 10839885
    Abstract: Steering logic circuitry includes bit-flipping logic that determines a first neighboring redundant word line adjacent to a redundant word line of a memory bank, which also includes normal word lines. Redundant word lines include main word lines, each of which includes paired word lines. Each paired word line includes two redundant word lines. The steering logic circuitry also includes border determination logic that determines whether the redundant word line is on a border between the redundant word lines and an end of the memory bank or the normal word lines. The steering logic circuitry further includes main word line steering logic that determines a neighboring main word line that a second neighboring redundant word line adjacent to the redundant word line is disposed in, and paired word line steering logic that determines a neighboring paired word line that the second neighboring redundant word line is disposed in.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Joosang Lee
  • Patent number: 10832791
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Alan J. Wilson
  • Patent number: 10825536
    Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for programming a device having one or more programmable circuits to implement, for example, a machine learning model. One example apparatus generally includes a plurality of word lines, a plurality of bit lines, and an array of programmable circuits. Each programmable circuit is coupled to a corresponding word line in the plurality of word lines and to a corresponding bit line in the plurality of bit lines and comprises: a main resistor coupled between the corresponding word line and the corresponding bit line, an auxiliary resistor, a fuse coupled in series with the auxiliary resistor, wherein the auxiliary resistor and the fuse are coupled between the corresponding word line and the corresponding bit line, and a programming circuit configured to selectively blow the fuse.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 3, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Haining Yang, Periannan Chidambaram
  • Patent number: 10818336
    Abstract: The apparatus includes a row hammer refresh (RHR) circuit configured to steal a first refresh cycle to implement a first RHR segment; and steal a second refresh cycle after one or more operating cycles, the second refresh cycle to implement a second RHR segment.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Joshua E. Alzheimer
  • Patent number: 10811119
    Abstract: A post package repair (PPR) method is disclosed. The PPR method includes the following operations: receiving a first PPR signal and a second PPR signal, in which the first PPR signal corresponds to a first PPR mode, and the second PPR signal corresponds to a second PPR mode; generating a first valid signal and a second valid signal according to the first PPR signal and the second PPR signal, in which only one of the first valid signal and the second valid signal comprises a valid information when both of the first PPR signal and the second PPR signal comprise an enabled information; in which when the first valid signal comprises the valid information, the first PPR mode is executed, and when the second valid signal comprises the valid information, the second PPR mode is executed.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: October 20, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Wei Shen
  • Patent number: 10803967
    Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-Yu Chou, Yu-Ti Su
  • Patent number: 10770159
    Abstract: An antifuse device is disclosed. The antifuse device includes a plurality of active regions, a plurality of word lines extending along a first direction and cut through the active regions, a plurality of bit lines and a plurality of source lines extending along a second direction and stride across the active regions. The bit lines and the source lines are arranged alternatively along the first direction. Plural antifuse capacitors are disposed along the source lines and connected between the source lines and the active regions.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: September 8, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tsai-Yu Huang, Pin-Yao Wang
  • Patent number: 10741246
    Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: August 11, 2020
    Assignee: Arm Limited
    Inventors: Mudit Bhargava, Brian Tracy Cline, George McNeil Lattimore, Bal S. Sandhu
  • Patent number: 10714242
    Abstract: An electrical resistor element, system, and method related thereto, wherein the electrical resistor element includes a tunable resistance. The electrical resistor element comprises a first contact electrode, a second contact electrode and a ferroelectric layer arranged between the first contact electrode and the second contact electrode. The ferroelectric layer comprises a first area having a first polarization direction and a second area having a second polarization direction. The first polarization direction is different to the second polarization direction. The ferroelectric layer further comprises a domain wall between the first area and the second area. The electrical resistor element further comprises a first pinning element configured to stabilize the first polarization direction of the ferroelectric layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Stefan Abel, Jean Fompeyrine, Johannes Gooth, Bernd Gotsmann, Fabian Menges
  • Patent number: 10685690
    Abstract: A memory device includes a bank that includes first memory cells connected to a first column selection line and second memory cells connected to a second column selection line, a first column decoder that selects the first memory cells by transmitting a first column selection signal in a first direction through the first column selection line, and a second column decoder that selects the second memory cells by transmitting a second column selection signal in a second direction opposite to the first direction through the second column selection line. The first column decoder includes a first register that stores a first fail column address of the first memory cells, and a second register that stores a second fail column address of the second memory cells.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-Jin Kim, Huikap Yang
  • Patent number: 10643726
    Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-yu Chou, Yu-Ti Su
  • Patent number: 10636510
    Abstract: A semiconductor device includes a fuse array circuit including a plurality of fuse cell arrays, and configured to output fuse data based on one or more fuses that have been ruptured or not within a fuse cell array; and a fuse control circuit configured to compare the fuse data and one or more failure addresses, and re-perform a rupture operation for the fuse cell array when the fuse data and the failure addresses indicate a difference between the fuse data and the failure addresses.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventor: Joohyeon Lee
  • Patent number: 10623192
    Abstract: Gate oxide breakdown in the programming element of an OTP (One-Time Programmable) memory cell can vary widely. The resulting large variations in the conductivity of the programmed memory cells in an OTP memory cell array is used for a PUF (Physically Unclonable Function). A method of obtaining a PUF value from an OTP memory cell array is described.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: April 14, 2020
    Assignee: Synopsys, Inc.
    Inventor: Larry Wang
  • Patent number: 10607686
    Abstract: An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a fast detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hiroshi Akamatsu
  • Patent number: 10535602
    Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Sheng Chang, Shao-Tung Peng, Shao-Yu Chou, Liang Chuan Chang, Yao-Jen Yang
  • Patent number: 10510427
    Abstract: The present invention relates to the technical field of integrated circuits. Disclosed is a one-time programmable memory with a high reliability and a low reading voltage, comprising: a first MOS transistor, a second MOS transistor, and an antifuse component. A gate terminal of the first MOS transistor is connected to a second connecting line (WS), a first connection terminal of the first MOS transistor is connected to the antifuse component, the antifuse component is connected to a first connecting line (WP), and a second connection terminal of the first MOS transistor is connected to a third connecting line (BL). A first connection terminal of the second MOS transistor is connected to a fourth connecting line (BR), and a second connection terminal of the second MOS transistor is connected to a third connecting line (BL). The invention further comprises a voltage limiting device with a control terminal and two connection terminals.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: December 17, 2019
    Assignee: SICHUAN KILOWAY ELECTRONICS INC.
    Inventors: Xuyang Liao, Junhua Mao, Jack Z. Peng
  • Patent number: 10438675
    Abstract: Memory programming methods and memory systems are described. One example memory programming method includes programming a plurality of main cells of a main memory and erasing a plurality of second main cells of the main memory. The memory programming method further includes first re-writing one-time programmed data within a plurality of first one-time programmed cells of a one-time programmed memory during the programming and second re-writing one-time programmed data within a plurality of second one-time programmed cells of a one-time programmed memory during the erasing. Additional method and apparatus are described.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Takafumi Kunihiro
  • Patent number: 10283210
    Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Chen-Ming Hung, Jen-Chou Tseng, Jam-Wem Lee, Ming-Hsiang Song, Shu-Chuan Lee, Shao-Yu Chou, Yu-Ti Su
  • Patent number: 10109338
    Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs pre-order address signals, post-order address signals, and an update signal including pulses periodically generated. The semiconductor device generates internal address signals counted by a predetermined number of times according to a combination of the pre-order address signals and a combination of the post-order address signals in response to a pulse of the update signal. The semiconductor device also performs a refresh operation according to a combination of the internal address signals.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: October 23, 2018
    Assignee: SK hynix Inc.
    Inventor: Haeng Seon Chae
  • Patent number: 10074660
    Abstract: In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 11, 2018
    Assignee: FLOADIA CORPORATION
    Inventors: Hideo Kasai, Yasuhiro Taniguchi, Yasuhiko Kawashima, Ryotaro Sakurai, Yutaka Shinagawa, Tatsuro Toya, Takanori Yamaguchi, Fukuo Owada, Shinji Yoshida, Teruo Hatada, Satoshi Noda, Takafumi Kato, Tetsuya Muraya, Kosuke Okuyama
  • Patent number: 10062444
    Abstract: An integrated circuit, that may be a part of an electronic system, may include a first set of storage cells to store settings and a second set of storage cells to store alternate settings. At least one control cell may also be included in the integrated circuit. The at least one control cell may indicate whether to use the settings stored in the first set of storage cells, or the alternate settings stored in the second set of storage cells, to control one or more operating parameters of the integrated circuit. Methods for using the alternate setting are also described.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: August 28, 2018
    Assignee: Intel Corporation
    Inventors: Julie M. Walker, Doyle Rivers
  • Patent number: 10008508
    Abstract: A non-volatile semiconductor storage device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second spaced apart doped regions formed below the gate insulating film and the gate electrode in the semiconductor substrate, wherein a grounded region of the first and second spaced apart doped regions is grounded via a contact.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 26, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Duk Ju Jeong, Sung Bum Park, Kee Sik Ahn, Young Chul Seo
  • Patent number: 10008290
    Abstract: A repair control device for memory cells divided into a plurality of banks may include a failed address storage circuit configured to sort and store a plurality of failed addresses each containing a failed bank address and a failed row address, according to the failed row address, and store the failed row address by matching the failed row address with total failed bank information representing one or more failed banks indicated by the failed row address. The repair control device also includes an address comparison circuit configured to compare an input address to a pair comprised of the failed row address and the total failed bank information, stored in the failed address storage circuit, and generate a hit signal based on the comparison result. The repair control device further includes an address generation circuit configured to generate an access target address based on the hit signal.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: June 26, 2018
    Assignee: SK hynix Inc.
    Inventors: Seol Hee Lee, Kang Seol Lee
  • Patent number: 9905309
    Abstract: A one-time programmable (OTP) memory device includes an OTP memory cell array comprising a plurality of dummy cells and a plurality of main cell groups of main cells and an access circuit configured to write data to at least two of the cells simultaneously. The arrangement of the dummy cells and the main cell groups may allow for the reliable writing of multi-bit data to the memory array. Each of the main cell groups may include a plurality of main cells which are connected to word lines, respectively, and to bit lines, respectively. Each of the main cells may be writable and each of the dummy cells may be unwritable. Each of the main cells may include a contact layer, and the dummy cells might not include the contact layer. A supply voltage may be applied to the OTP memory cell array through the contact layer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoon Jin Bang, Sang Seok Lee
  • Patent number: 9899099
    Abstract: A fuse element includes a gate; first to Nth junction regions disposed in an active region, where N is a natural number of 3 or more; and a dielectric layer interposed between the gate and the first to Nth junction regions, wherein a dielectric breakdown between the gate and each of the first to Nth junction regions is independently performed.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: February 20, 2018
    Assignee: SK HYNIX INC.
    Inventor: Hyung-Dong Lee
  • Patent number: 9876123
    Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: January 23, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Jeffrey Junhao Xu, Xiao Lu, Bin Yang, Jun Yuan, Xiaonan Chen, Zhongze Wang
  • Patent number: 9870837
    Abstract: A semiconductor memory device includes a fuse array circuit including a row fuse region and a column fuse region, and suitable for outputting fuse information from row fuse sets and from column fuse sets and outputting programmed row and column addresses as row and column fall data, during a boot-up operation; a fuse array control circuit suitable for storing a fail address based on a fail cell information during a repair operation, searching unused fuse sets from the row fuse region and the column fuse region based on the fuse information during the boot-up operation, and controlling the fail address to be programmed in the unused fuse sets during a rupture operation; and a row and column redundancy circuit suitable for performing a row or column redundancy operation in correspondence to the row and column fail data.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 16, 2018
    Assignee: SK Hynix Inc.
    Inventor: Young-Bo Shim
  • Patent number: 9754678
    Abstract: A method of testing a semiconductor integrated circuit including a one-time programmable (OTP) memory device is provided. A program command is transferred from a tester to the OTP memory device. Programming and a programming verification are performed with respect to OTP memory cells in the OTP memory device in response to the program command. The OTP device generates accumulated verification result signal by accumulating program verification results with respect to the OTP memory cells. The accumulated verification result signal is transferred from the OTP memory device to the tester.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Hoon Byun, Chang-Su Sim, Na-Rae Hong
  • Patent number: 9734879
    Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: August 15, 2017
    Assignee: RAMBUS INC.
    Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
  • Patent number: 9711237
    Abstract: A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained below the critical current, electromigration can be the sole programming mechanism and, as a result, programming can be deterministic and very reliable. In this method, fuses can be programmed in multiple shots with progressive resistance changes to determine a lower bound that all fuses can be programmed satisfactorily and an upper bound that at least one fuse can be determined failed. If programming within the lower and upper bounds, defects due to programming can be almost zero and, therefore, defects are essentially determined by pre-program defects.
    Type: Grant
    Filed: September 13, 2014
    Date of Patent: July 18, 2017
    Assignee: Attopsemi Technology Co., Ltd.
    Inventor: Shine C. Chung
  • Patent number: 9659667
    Abstract: A circuit for reading a one time programmable (OTP) memory includes a controller that receives a read input signal and generates a read delay signal, a read voltage signal, and a read latch signal; a read voltage generator that generates a read voltage based on the read voltage signal and outputs the read voltage to a detecting node; an OTP memory unit cell including a first electrode connected to the detecting node; a first detecting unit that determines a voltage at the detecting node; a determining unit that delays an output signal from the first detecting unit based on the read delay signal; and a latch unit that latches an output signal from the determining unit during a first delay time at a falling edge of the read input signal based on the read latch signal.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: May 23, 2017
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Beom Seon Ryu
  • Patent number: 9646711
    Abstract: A memory device includes first through fourth active regions arranged sequentially along a first direction, and which extend along a second direction different from the first direction; a first gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, and extending along the first direction; a second gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, extending along the second direction, and arranged so that no other gate electrodes are between the first gate electrode and the second gate electrode in the second direction; the first gate electrode extending between a first end and a second end; a first wiring line which is formed on the first gate electrode; a first strap contact, which connects the first wiring line and the first gate electrode between the first active region and the second active region; and a second strap contact, which connects the first wiring line and the firs
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: May 9, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, Shigenobu Maeda
  • Patent number: 9627026
    Abstract: A refresh control device may include a fuse array configured to store fuse data. The refresh control device may include a refresh controller including cell arrays including unit cells. The refresh controller may be configured to store position information of a word line having weak cell characteristics based on fuse data. The refresh control device may include a comparator configured to receive data from the cell arrays of a selected cell and may be configured to compare the data to determine the presence of a weak word line to either perform or skip the refresh operation on the corresponding cell.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: April 18, 2017
    Assignee: SK HYNIX INC.
    Inventors: Min Soo Kang, So Min Park
  • Patent number: 9589971
    Abstract: An anti-fuse memory cell is provided. The anti-fuse memory cell includes a programmable transistor and a selection transistor. The programmable transistor includes a gate structure, a first doped region and a lightly doped region. The first doped region is divided into a first portion doped region, a second portion doped region and a third portion doped region. The first and second portion doped regions are respectively a source and a drain of the programmable transistor, and the third portion doped region is disposed between the first and second portion doped regions. The lightly doped region is distributed around a channel region of the programmable transistor, and adjacent to the first, second and third portion doped regions. The selection transistor includes a gate structure and a second doped region, and connected in series to the programmable transistor through the first portion doped region.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: March 7, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chia-Chiuan Chang, Jui-Lung Chen, Yu-Wen Chen, Hsuan-Chi Su, Ching-Hsiang Lin
  • Patent number: 9570193
    Abstract: A method and circuit for implementing a hidden security key in Electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. The circuit includes a race condition circuit coupled to a latching structure. The race condition circuit is characterized including respective driver strengths of each stage in the race as well as a sampling clock during chip testing. The data is used to store drive strengths for each stage in eFuses and is used to get a logical one or logical zero out of the final latching stage of the race condition circuit.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Patent number: 9536883
    Abstract: According to one exemplary implementation, a dual anti-fuse structure includes a first channel in a common semiconductor fin adjacent to a first programmable gate. The dual anti-fuse structure further includes a second channel in said common semiconductor fin adjacent to a second programmable gate. A first anti-fuse is formed between the first channel and the first programmable gate. Furthermore, a second anti-fuse is formed between the second channel and the second programmable gate. The first programmable gate can be on a first sidewall of the common semiconductor fin and can comprise a first gate dielectric and a first electrode. The second programmable gate can be on a second sidewall of the common semiconductor fin and can comprise a second gate dielectric and a second electrode.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: January 3, 2017
    Assignee: BROADCOM CORPORATION
    Inventors: Frank Hui, Neal Kistler
  • Patent number: 9524795
    Abstract: A one-time programmable (OTP) memory device includes a memory cell array including a plurality of OTP memory cells, the plurality of OTP memory cells being connected to a plurality of bitlines, a plurality of voltage wordlines and a plurality of read wordlines, respectively; and a switching circuit configured to, in a program mode, detect program states of the plurality of OTP memory cells to block currents from flowing through the plurality of OTP memory cells from the voltage wordlines to the bitlines based on the detected program states.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: December 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Hyung Lee, Oh-Kyum Kwon
  • Patent number: 9519020
    Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: December 13, 2016
    Assignee: SK HYNIX INC.
    Inventors: Jae Bum Ko, Jun Gi Choi
  • Patent number: 9490261
    Abstract: A nitride read only memory (NROM) array includes a silicon substrate having trenches therein, a plurality of polysilicon bit lines deposited in the trenches and connecting columns of memory cells, a layer of (oxide nitride oxide) ONO at least within the memory cells and a plurality of polysilicon word lines to connect rows of the memory cells. An NROM array with a virtual ground architecture includes a plurality of bit lines to connect columns of NROM memory cells, a layer of ONO at least within the memory cells and a plurality of word lines to connect rows of the NROM memory cells, wherein a distance between word lines is at least twice the width of the word lines.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: November 8, 2016
    Assignee: Cypress Semiconductor Ltd.
    Inventors: Ilan Bloom, Amichai Givant, Boaz Eitan
  • Patent number: 9437322
    Abstract: An active precharge circuit for a non-volatile memory array which minimizes write disturb to non-selected memory cells during programming is disclosed. In a programming cycle, all bitlines are pre-charged to a program inhibit voltage level and held at the program inhibit voltage level with current or voltage sources coupled to each of the bitlines in a precharge operation and a following programming operation. In the programming operation, a bitline connected to a memory cell to be programmed is driven to a programming level, such as VSS, while the active precharge circuit is enabled to enable programming thereof. Because the other non-selected bitlines are held at the program inhibit voltage level, they will not be inadvertently programmed when the programming voltage is supplied by the word line.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: September 6, 2016
    Assignee: SIDENSE CORP.
    Inventor: Steven Smith
  • Patent number: 9431111
    Abstract: A one time programming memory cell includes a transistor, a first varactor, and a second varactor. The transistor has a gate terminal, a source terminal and a drain terminal. The gate terminal of the transistor is connected with a word line. The source terminal of the transistor is connected with a bit line. A first end of the first varactor is connected with the drain terminal of the transistor. A second end of the first varactor is connected with a first program line. A first end of the second varactor is connected with the drain terminal of the transistor. A second end of the second varactor is connected with a second program line.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: August 30, 2016
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Meng-Yi Wu, Hsin-Ming Chen
  • Patent number: 9373421
    Abstract: A semiconductor apparatus may include a global line configured to enable electrical coupling between a memory block and an input/output terminal, a fuse array configured to store and to transmit repair information through the global line, and a control unit configured to selectively enable or disable signal paths among the input/output terminal, the global line, and the fuse array according to an operation mode of the semiconductor apparatus.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: June 21, 2016
    Assignee: SK hynix Inc.
    Inventor: Jong Sam Kim
  • Patent number: 9336896
    Abstract: An integrated circuit is provided that allows for the use of the same supply voltage pin to receive both a normal operating voltage for the integrated circuit (IC) and a one-time-programmable (OTP) memory program voltage sufficient to program an OTP memory located on the integrated circuit. In one embodiment, when an OTP programming voltage is received at a supply voltage pin of the IC, the OTP programming voltage is provided to the OTP memory of the integrated circuit and the OTP programming voltage is regulated to the normal operating voltage level prior to providing the voltage to the internal circuitry of the integrated circuit. As such, the present invention establishes a dual-purpose supply voltage pin, thereby eliminating the need for a separate OTP programming voltage pin on the integrated circuit.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: May 10, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: John Hsu
  • Patent number: 9305973
    Abstract: Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device can have an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: April 5, 2016
    Inventor: Shine C. Chung
  • Patent number: 9293220
    Abstract: A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC can be built with at least one low-pin-count OTP memory. The low-pin-count OTP memory can be built with a serial interface such as I2C-like or SPI-like of interface. The pins of the low-pin-count OTP in at least one die can be coupled together to have only one set of low-pin-count bus for external access. With proper device ID, each die in a 3D IC can be accessed individually for soft programming, programming, erasing, or reading. This technique can improve the manufacture yield, device, circuit, or logic performance or to store configuration parameters for customization after 3D IC are built.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: March 22, 2016
    Inventor: Shine C. Chung