Including Delay Means Patents (Class 368/120)
  • Patent number: 10958412
    Abstract: Systems, methods, and circuitries are provided to perform bidirectional communication using edge timing. In one example, a method includes receiving, on a first signal line, a first signal having a first timing edge and a first data edge. The first timing edge is of a different type than the first data edge. The first data edge is an edge immediately adjacent to the first timing edge and occurs at a first elapsed time after the first timing edge. The method includes sampling the first signal at a predetermined sample time after the first timing edge to determine a first data value. A second data value is determined and a second signal is generated having a second timing edge and a second data edge. A second elapsed time between the second timing edge and the second data edge encodes a second data value. The second signal is transmitted on a second signal line.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: March 23, 2021
    Assignee: Infineon Technologies AG
    Inventor: Jens Barrenscheen
  • Patent number: 9354690
    Abstract: A system for adjusting core voltage of an integrated circuit to optimize power savings has a ring oscillator on the integrated circuit for providing a ring oscillator signal. The system also has compare logic on the integrated circuit configured to compare the ring oscillator signal with a clock signal from a clock external to the integrated circuit. The compare logic is configured to make a determination whether a frequency of the clock signal is within a predefined margin of a frequency of the ring oscillator and to adjust the core voltage of the integrated circuit based on the determination. Through such adjustments, the core voltage is lowered while ensuring that the core voltage does not reach a point that causes timing errors.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: May 31, 2016
    Assignee: ADTRAN, Inc.
    Inventors: Daniel M. Joffe, Brian Smith
  • Patent number: 9229433
    Abstract: Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: January 5, 2016
    Assignee: PMC-SIERRA US, INC.
    Inventors: Mark Hiebert, Derek J. W. Ho
  • Patent number: 9209822
    Abstract: According to one embodiment, an A/D converter includes a first delay cell column in which a plurality of delay cells, to which a first bias current corresponding to a difference voltage between an input voltage and a reference voltage is supplied, is connected in series. The converter includes a second delay cell column in which a plurality of delay cells, to which a second bias current corresponding to a negative-phase difference voltage of the difference voltage is supplied, is connected in series. The converter includes an encoder unit configured to encode a difference value, in delay time of signal propagation, between the first delay cell column and the second delay cell column.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: December 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chen Kong Teh, Atsushi Suzuki
  • Patent number: 9092013
    Abstract: Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: July 28, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Hui William Song, Mohamed Hassan Abu-Rahma
  • Patent number: 8976051
    Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ljudmil Anastasov, Jens Barrenscheen
  • Patent number: 8970420
    Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Intel Mobile Communications GmbH
    Inventors: Stephan Henzler, Markus Schimper, Stefan Tertinek
  • Patent number: 8786474
    Abstract: An apparatus and method for inserting delay into a start signal of a metastable ring oscillator chain-based time-to-digital circuit (TDC). Included therein is a signal generating circuit that generates the start signal, a plurality of carry elements connected as a chain, each of the carry elements having an input to receive a stop signal, a delay chain circuit including one or more delay modules selected from the plurality of carry elements, at least one feedback line connected between at least one of the delay modules and the signal generating circuit, and a plurality of enable inputs each provided in a respective one of the delay modules. The delay chain circuit generates an amount of delay based on a delay selection signal that is received at the enable inputs and that selects the amount of delay. The delay chain circuit additionally provides the selected amount of delay to the signal generating circuit, which incorporates the delay into the start signal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 22, 2014
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Medical Systems Corporation
    Inventor: Gregory J. Mann
  • Patent number: 8553503
    Abstract: In one embodiment, a timing relationship between two signals on an integrated circuit is measured using a ring oscillator on the die of the integrated circuit. The measured time difference is outputted in a digital form. A delay line coupled to the ring oscillator may be used to reduce uncertainty in measurement which may result from the effects of latch circuit metastability. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: October 8, 2013
    Assignee: Intel Corporation
    Inventors: Igor V. Molchanov, Matthew W. Heath
  • Patent number: 8422340
    Abstract: Methods for determining timestamps for signal timing edges for use in, e.g., a reciprocal counter for determining the frequency of a signal is disclosed, comprising the steps of inputting the signal into a tapped delay line, producing a plurality of delay line tap signals at the output of each of the delay line taps. In one embodiment, after detecting the signal timing edge and determining an initial time value corresponding to the timer clock cycle count at the signal timing edge or the next clock timing edge, the delay line tap signals are monitored to determine a fractional correction time value adjustment to be made to the initial value to account for the delay between the signal timing edge and the next clock timing edge to determine the timestamp. In another embodiment, after detecting the signal timing edge, the average of a plurality of delay line timer clock cycle counts corresponding to the timer clock cycle counts at the delay line tap signal timing edges is used to determine the timestamp.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: April 16, 2013
    Assignee: General Electric Company
    Inventor: Andrew Hutchinson
  • Patent number: 8305847
    Abstract: A method for high-resolution timing measurement includes a first oscillator generating a first clock with a first frequency. A second oscillator generates a second clock with a second frequency. A delay pulse generator generates a delayed pulse from the second clock. An oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the first frequency. A sampling module samples the delayed pulse at the first frequency. A counter generates a digital counter value by counting a number of samples made by the sampling module.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: November 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Saurabh Gupta
  • Patent number: 8243555
    Abstract: Implementations are presented herein that include a time delay path.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: August 14, 2012
    Assignee: Infineon Technologies AG
    Inventors: Stephan Henzler, Siegmar Koeppe
  • Patent number: 8228763
    Abstract: A device is disclosed for measuring a plurality of time intervals.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: July 24, 2012
    Assignee: Infineon Technologies AG
    Inventor: Stephan Henzler
  • Patent number: 8222607
    Abstract: A time-to-digital converter device includes a first delay chain circuit that generates a first value corresponding to a time delay between a start signal and a stop signal. The time-to-digital converter device also includes at least one second delay chain circuits that generates a second value corresponding to a time delay between a delayed start signal and the stop signal. At least one delay element generates the delayed start signal by applying a predetermined delay to the start signal, and a combining circuit generates an output value based on the first and second values. In the time-to-digital converter according to the exemplary embodiments of the present advancements, the output value corresponds to the time delay between the start signal and the stop signal.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: July 17, 2012
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Medical Systems Corporation
    Inventor: Gregory J. Mann
  • Patent number: 8138843
    Abstract: Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter includes a plurality of delay stages configured to enable propagation of a transitioning signal through the delay stages during an enabled state and configured to inhibit propagation of the transitioning signal through the delay stages during a disabled state. Delay stages are interconnected to allow sustained transitions to propagate through the delay stages during the enabled state and to preserve a state of the gated ring oscillator time-to-digital converter during the disabled state. The state represents a time resolution that is finer than the delay of at least one of the delay stages. A measurement module determines the number of transitions of the delay stages.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: March 20, 2012
    Assignee: Massachusetts Institute of Technology
    Inventors: Matthew Straayer, Michael Perrott
  • Patent number: 8065102
    Abstract: A pulse width measurement circuit generates a time difference signal that corresponds to the pulse width of the input pulse signal PULSE. A delay circuit delays the input pulse signal PULSE by a predetermined amount, and outputs a start signal. An inverter inverts the input pulse signal PULSE, and outputs a stop signal. A time measurement circuit measures the time difference between a positive edge in the start signal and a positive edge in the stop signal, and outputs a time difference signal that corresponds to the time difference.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: November 22, 2011
    Assignee: Advantest Corporation
    Inventor: Shoji Kojima
  • Patent number: 8050148
    Abstract: One embodiment of an apparatus for generating a time stamp includes a clock input, an event signal input and a time stamp output. A DLL is connected to the clock input, with a plurality of delay elements inside the DLL. An output of each of the delay elements is connected to a data input on a latch. An event signal input is connected to an enable input on each of the latches. An output of each of the latches is connected to the time stamp output. The apparatus is adapted to produce a value on the time stamp output indicating a point at which the event signal input transitions between transitions on the clock input.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: November 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Graham Brantley, James Richard MacLean, Francesco Cavaliere
  • Patent number: 8023363
    Abstract: A time-to-digital converter apparatus including a delay phase-locked loop, a subtracter, a multi-phase detector and a Vernier detector is disclosed. The delay phase-locked loop herein includes digital delay components for producing counting signals. The multi-phase detector includes digital delay components for producing delay outputs according to the counting signals and thereby detecting a pulse input signal. The Vernier detector includes digital delay components for detecting the remainder of the pulse input signal according to the difference between the delay outputs produced by the subtracter.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: September 20, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Hong-Yi Huang, Yi-Jui Tsai, Yuan-Hua Chu
  • Patent number: 7961559
    Abstract: A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert C. Dixon, Robert L. Franch, Phillip J. Restle
  • Publication number: 20100141240
    Abstract: Methods for determining timestamps for signal timing edges for use in, e.g., a reciprocal counter for determining the frequency of a signal is disclosed, comprising the steps of inputting the signal into a tapped delay line, producing a plurality of delay line tap signals at the output of each of the delay line taps. In one embodiment, after detecting the signal timing edge and determining an initial time value corresponding to the timer clock cycle count at the signal timing edge or the next clock timing edge, the delay line tap signals are monitored to determine a fractional correction time value adjustment to be made to the initial value to account for the delay between the signal timing edge and the next clock timing edge to determine the timestamp. In another embodiment, after detecting the signal timing edge, the average of a plurality of delay line timer clock cycle counts corresponding to the timer clock cycle counts at the delay line tap signal timing edges is used to determine the timestamp.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 10, 2010
    Inventor: Andrew Hutchinson
  • Patent number: 7710835
    Abstract: A high resolution time detecting apparatus using interpolation and a time detecting method using the same are provided. The time detecting apparatus includes a delayer which generates delayed signals by sequentially delaying a reference signal using a plurality of delay elements, a latch unit which outputs latch signals using the delayed signals, and an interpolation unit which outputs interpolated signals using input and output signals of the delay elements. As a result, a high resolution TDC using an interpolation and a time detecting method using the same provide improved performance of digital PLL, high resolution digital signal output at a low power consumption, and controlled circuit size.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-wook Kim, Choong-yul Cha, Jae-sup Lee, Kang-yoon Lee
  • Publication number: 20090296532
    Abstract: A time-to-digital converter includes a circular delay chain, a phase interpolator, and a time-to-digital (TDC) core. The circular delay chain receives a first input clock and generates a first set of multi-phase clocks by propagating the first input clock through delay cells in the delay chain. The phase interpolator performs phase interpolation with a second input clock and another clock to generate a second set of multi-phase clocks. The other clock may be a delayed version of the second input clock. The TDC core uses the first and second set of multi-phase clocks to determine the time difference between the first and second input clocks.
    Type: Application
    Filed: April 3, 2009
    Publication date: December 3, 2009
    Inventor: Hong-Yean HSIEH
  • Publication number: 20090154300
    Abstract: The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.
    Type: Application
    Filed: December 14, 2007
    Publication date: June 18, 2009
    Applicant: Guide Technology, Inc.
    Inventor: Sassan Tabatabaei
  • Publication number: 20090141595
    Abstract: A time-to-digital converter apparatus including a delay phase-locked loop, a subtracter, a multi-phase detector and a Vernier detector is disclosed. The delay phase-locked loop herein includes digital delay components for producing counting signals. The multi-phase detector includes digital delay components for producing delay outputs according to the counting signals and thereby detecting a pulse input signal. The Vernier detector includes digital delay components for detecting the remainder of the pulse input signal according to the difference between the delay outputs produced by the subtracter.
    Type: Application
    Filed: May 2, 2008
    Publication date: June 4, 2009
    Applicant: Industrial Technology Research Institute
    Inventors: Hong-Yi Huang, Yi-Jui Tsai, Yuan-Hua Chu
  • Patent number: 7525878
    Abstract: In a time measuring circuit, a pulse delay circuit is provided with a plurality of delay units. The pulse delay circuit is configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units. A delay time of each of the plurality of delay units depends on a level of a first drive voltage being input to each of the plurality of delay units. A generating circuit is configured to obtain a number of the delay units through which the pulse signal has passed within a predetermined period to generate, as time measurement data, digital data based on the obtained number. A first setting unit is configured to variably set the level of the first drive voltage being input to each of the plurality of delay units.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: April 28, 2009
    Assignee: DENSO CORPORATION
    Inventor: Takamoto Watanabe
  • Patent number: 7516032
    Abstract: A system and method for providing improved resolution in the measuring the pulse width of digital signals comprising counting the integral number of measuring clock pulses covered by said digital pulse and triggering a chain of cascaded high resolution delay elements from the trailing edge of said measuring clock pulses. Further, the invention measures the delay count obtained from said chain of cascaded delay elements from the trailing edge of the last measuring clock pulse up to the end of said digital pulse, and adds said measured delay count to said integral measuring clock pulse count to obtain the total width of said digital pulse.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: April 7, 2009
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventor: Balwant Singh
  • Publication number: 20080198700
    Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
    Type: Application
    Filed: March 10, 2008
    Publication date: August 21, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle, Timothy M. Skergan
  • Publication number: 20080198699
    Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
    Type: Application
    Filed: March 10, 2008
    Publication date: August 21, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle, Timothy M. Skergan
  • Patent number: 7400555
    Abstract: A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: July 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Franch, William V. Huott, Norman K. James, Phillip J. Restle, Timothy M. Skergan
  • Patent number: 7339853
    Abstract: Generally, the embodiments are directed to circuits and methods for time stamping an event at a fraction of a clock cycle. A time stamping circuit comprises two or more detection circuits. The detection circuits receive an event-in signal and generate event signals based on a clock phase at which the event-in signal was received. A decoder receives the event signals and outputs an event-out signal and a time stamp that represents the phase at which the event-in signal was detected. By time stamping the event-in signal to a phase division, the time stamping circuit detects event signals that occur at a rate faster than the clock cycle.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: March 4, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: Vamsi Krishna Srikantam, Andew David Fernandez, Dietrich Werner Vook
  • Patent number: 7315489
    Abstract: A method is provided for accurate time measurement. Time is first measured with a first oscillator. At designated intervals, a second oscillator is activated for a period of time based on the first oscillator. The second oscillator is more accurate than the first oscillator. Pulses are then counted from the second oscillator during the period of time. The second oscillator is then turned off after the period of time. The count from the second oscillator is used as a new measurement of the period of time of the first oscillator.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: January 1, 2008
    Assignee: Powerprecise Solutions, Inc.
    Inventor: John Houldsworth
  • Patent number: 7315270
    Abstract: Differential delay-line analog-to-digital (A/D) converters for use in current and power sensing applications are provided. These A/D converters are well suited for a wide range of electronic applications, including over-load protection, current mode control, current sharing in digitally controlled switched-mode power supplies, power sensing, and implementation of power optimization methods in power management applications.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: January 1, 2008
    Assignee: The Regents of the University of Colorado
    Inventors: Dragan Maksimovic, Hao Peng
  • Publication number: 20070280054
    Abstract: In a time measuring circuit, a pulse delay circuit is provided with a plurality of delay units. The pulse delay circuit is configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units. A delay time of each of the plurality of delay units depends on a level of a first drive voltage being input to each of the plurality of delay units. A generating circuit is configured to obtain a number of the delay units through which the pulse signal has passed within a predetermined period to generate, as time measurement data, digital data based on the obtained number. A first setting unit is configured to variably set the level of the first drive voltage being input to each of the plurality of delay units.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 6, 2007
    Applicant: DENSO Corporation
    Inventor: Takamoto Watanabe
  • Patent number: 7228464
    Abstract: PICA probe system apparatus is described, including apparatus for calibrating an event timer having a coarse measurement capability in which time intervals defined by clock boundaries are counted and a fine measurement capability in which time between boundaries is interpolated using a voltage ramp.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: June 5, 2007
    Assignee: Credence Systems Corporation
    Inventor: Kenneth R. Wilsher
  • Patent number: 7219269
    Abstract: A self-calibrating strobe signal generator for a BIST circuit responds to an edge of an input strobe signal by generating corresponding edges of first and second strobe signals separated in time by a target delay specified by input data. The strobe signal generator includes a multiplexer, a delay circuit and a controller. The multiplexer normally provides the input strobe signal as a multiplexer output signal to the delay circuit which generates edges in each of the first and second strobe signals in response to each edge in the multiplexer output signal with a programmable delay between corresponding first and second strobe signal edges.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: May 15, 2007
    Assignee: Credence Systems Corporation
    Inventor: Arnold M. Frisch
  • Patent number: 7216047
    Abstract: A method of determining the delay between two corresponding noise-like signals comprises determining events at which the level of a first of the signal crosses a predetermined threshold, using each event to sample a second signal, combining the samples to produce an output value and determining the delay from the output value. Preferably, each sample is weighted according to one or more characteristics of the event used to define the sample. The magnitude of the output value could be an indication of the delay, or there could be several output values each for a respective differently-delayed version of the second signal, in which case these could be evaluated to select which corresponds to the actual delay.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: May 8, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Wieslaw Jerzy Szajnowski
  • Patent number: 6944099
    Abstract: Measurement of the period of a relatively slow but precise reference clock in terms of a high speed oscillating clock, such as from a voltage controlled oscillator (VCO). The reference clock is known to be accurate and stable and values of the time measurement unit are output that determine the integer and fractional number of the high speed oscillating clock periods which occurred during one reference clock cycle. The measurements are very accurate and all cycles of the reference clock are measured. Such measurements enable various frequency control schemes over the high speed oscillating clock source.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: September 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Curtis Walter Preuss, Michael Launsbach
  • Patent number: 6868047
    Abstract: A accurate time measurement circuit. The design is amenable to implementation as a CMOS integrated circuits, making the circuit suitable for a highly integrated system, such as automatic test equipment where multiple time measurement circuits are required. The circuit uses a delay locked loop to generate a plurality of signals that are delayed in time by an interval D. The signal to be measured is fed to a bank of delay elements, each with a slightly different delay with the difference in delay between the first and the last being more than D. An accurate time measurement is achieved by finding coincidence between one of the TAP signals and one of the delay signals. The circuit has much greater accuracy than a traditional delay line based time measurement circuit with the same number of taps. It therefore provides both accuracy and fast re-fire time and is less susceptible to noise.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: March 15, 2005
    Assignee: Teradyne, Inc.
    Inventors: Ronald A. Sartschev, Jun Xu
  • Patent number: 6819117
    Abstract: PICA probe system methods and apparatus are described, including methods and apparatus for calibrating an event timer having a coarse measurement capability in which time intervals defined by clock boundaries are counted and a fine measurement capability in which time between boundaries is interpolated using a voltage ramp.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: November 16, 2004
    Assignee: Credence Systems Corporation
    Inventor: Kenneth R. Wilsher
  • Patent number: 6785194
    Abstract: A method and apparatus for precision time interval measurement in a time-of-flight mass spectrometer (TOF-MS). The method and apparatus produces an instrument capable of measuring bursts of data occurring at rates much higher than the average data rate. An asynchronous serial stream of data, consisting of a start pulse followed by an arbitrary number of stop pulses, repeated an arbitrary number of times, is converted into a digital stream of data synchronized to a precision master clock. Conversion of the asynchronous, analog data to synchronous digital data simplifies the measurement task by allowing the use of powerful, low-cost digital logic in the measurement.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: August 31, 2004
    Assignee: Advanced Measurement Technology, Inc.
    Inventors: Jeffrey V. Peck, Dale A. Gedcke, Russell D. Bingham
  • Patent number: 6760551
    Abstract: The present invention is a decoder for decoding a signal. The decoder includes a discriminator and a threshold generator. The discriminator receives the signal and generates an output voltage equal to a first voltage if the signal is less than a threshold level that is input to the discriminator and equal to a second voltage if the signal is greater than the threshold level. The threshold level depends on the output from the discriminator in a preceding time interval that depends on the impulse response of a transmission link through which the input signal has passed. The threshold generator implements a low-pass analog filter that receives the output voltage during each of the clock periods and generates therefrom a filtered output signal.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: July 6, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Adrian Wan-Chew Seet, Ken Nishimura, Richard C. Walker
  • Patent number: 6747468
    Abstract: To accomplish circuit trimming of a packaged IC chip by applying a magnetic field thereon, a magnetically configurable adjuster device is coupled with the packaged IC chip. The magnetically configurable adjuster device includes a Hall element, a signal processor and amplifier device, a decoder, and a configurable adjuster that receives a signal outputted by the packaged IC chip. The configurable adjuster includes a plurality of electrically configurable elements and circuit-trimming members. The Hall element senses and converts the magnetic field into a voltage signal by Hall effect. After amplification, the voltage signal is inputted to the decoder. The decoder decodes the voltage signal into decoded signals that configure the configurable adjuster by means of the configurable elements. With the configurable adjuster hence configured, circuit trimming of the packaged IC chip is achieved via the circuit-trimming members.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: June 8, 2004
    Assignee: Anachip Corp.
    Inventor: James Seng-Ju Ni
  • Patent number: 6741522
    Abstract: Methods and structure for improving accuracy of a master delay line associated with slave delay lines wherein the master delay line is design utilizing a higher clock frequency then the clock frequency applied to associated slave delay lines. The higher clock frequency applied to the master delay line in accordance with the present invention permits the master delay line to be comprised of fewer delay elements than would be the case for a master delay line using the same basic clock frequency as associated slave delay lines. The lower number of delay elements comprising the master delay line (i.e., the shorter length of the master delay line) helps reduce static phase errors associated with the master delay line inherent in the design, layout and fabrication of a longer delay line.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: May 25, 2004
    Assignee: LSI Logic Corporation
    Inventor: Shuaibin Lin
  • Patent number: 6611477
    Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC A designers to minimize the guard band and consequently guarantee higher speed performance.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: August 26, 2003
    Assignee: Xilinx, Inc.
    Inventors: Gil A. Speyer, David L. Ferguson, Daniel Y. Chung, Robert D. Patrie, Robert W. Wells, Robert O. Conn
  • Patent number: 6574169
    Abstract: A delay test system includes an electronic circuit, such as a normal circuit which has a portion to be tested and a plurality of flip-flop circuits. In this event, each of flip-flop circuits is serially connected to each other to perform a delay test for said normal circuit. Further, a first clock input terminal is connected to the flip-flips and a normal circuit to input a normal mode clock signal. Moreover, a second clock input terminal is connected to the flip-flop circuits and the normal circuit to input a test clock signal. With such a structure, an input and output operation of data signals is carried out in synchronism with edge timings determined by both the normal mode clock signal in the normal mode on the condition that the test clock signal is not supplied to the second clock input terminal. On the other hand, the first and second clock input terminals are separately driven by the normal mode clock signal and the test clock signal in the test mode.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: June 3, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Hisashi Yamauchi
  • Patent number: 6529842
    Abstract: Highly accurate time interval measurement is achieved for an electrical waveform. The electrical waveform is sampled and converted to a series of voltages, and the series of voltages is interpolated in order to form a time tag list, using interpolations that are optimized for time interval measurement and analysis. The time tag list accurately represents the times at which particular events of interest occur, and is used to generate displays and results analysis such as adjacent cycle jitter and accurate differential triggering and analysis.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: March 4, 2003
    Inventors: Michael K. Williams, Daniel J. Coffey
  • Patent number: 6501706
    Abstract: A time-to-digital converter records the arrival times of successive signals—which are separated from one another by more than one period of a reference clock signal—by recording the number of nodes disposed within a plurality of fine delay paths—each coupled to a different one of a plurality of coarse delay stages in a first coarse delay path—through which the signals propagate. The delay across each fine delay path is substantially the same as the delay across a coarse delay stage in the coarse delay path. A phase detector maintains the clock signal and its delayed replica in phase by adjusting the delay through each of the coarse delay stages in a second coarse delay path. The time delay between the clock signal and its delayed replica is equal to one period of the clock signal.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: December 31, 2002
    Inventor: Burnell G. West
  • Patent number: 6477115
    Abstract: In a semiconductor integrated circuit, a monitor circuit for evaluation is provided on a semiconductor substrate in an input/output buffer circuit region. This monitor circuit includes a delay circuit, a first flip-flop circuit on the input side of the delay circuit, and a second flip-flop circuit on the output side of the delay circuit.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: November 5, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Chizuru Inoshita, Kazuo Aoki
  • Patent number: 6466520
    Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: October 15, 2002
    Assignee: Xilinx, Inc.
    Inventors: Gil A. Speyer, David L. Ferguson, Daniel Y. Chung, Robert D. Patrie, Robert W. Wells, Robert O. Conn
  • Patent number: 6452459
    Abstract: A circuit measures a signal propagation delay through a series of memory cells on a programmable logic device. In one embodiment, a number of RAM cells are configured in series. Each RAM cell is initialized to store a logic zero. The first RAM cell is then clocked so that the output of the RAM cell rises to a logic one. The resulting rising edge from the output of the RAM cell then clocks the second RAM cell, which in turn clocks the next RAM cell in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each RAM cell to change in response to a clock edge. Consequently, the delay through the series of RAM cells provides a measure of the time required for one of the RAM cells to store data in response to a clock edge.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: September 17, 2002
    Assignee: Xilinx, Inc.
    Inventors: Siuki Chan, Christopher H. Kingsley