Abstract: A circuit measures a signal propagation delay through a series of memory cells on a programmable logic device. In one embodiment, a number of RAM cells are configured in series. Each RAM cell is initialized to store a logic zero. The first RAM cell is then clocked so that the output of the RAM cell rises to a logic one. The resulting rising edge from the output of the RAM cell then clocks the second RAM cell, which in turn clocks the next RAM cell in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each RAM cell to change in response to a clock edge. Consequently, the delay through the series of RAM cells provides a measure of the time required for one of the RAM cells to store data in response to a clock edge.

Abstract: A semiconductor circuit is provided including circuitry for producing a pulse. A plurality, n, of delay elements are provided each enabled and disabled in parallel by the pulse. Each delay element is adapted to transmit the pulse from an input to an output, with the pulse reaching the respective outputs at different times. A plurality, n−1, of detectors is provided each having an input coupled to an input of a corresponding delay element. Each detector is adapted to set a state of its output to a predetermined state, from a plurality of states, in response to receiving a portion of the pulse. The outputs of the detectors are coupled to output pins of the semiconductor circuit. A tester is provided that is adapted to couple to the semiconductor output pins and detect the state of the detector outputs.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components.

Abstract: An apparatus for measuring valve dispensing time. In the apparatus, an optical fiber sensor is located arranged in the vicinity of an outlet of a nozzle. A magnetic field is generated in coils of a first relay by an ON signal from an electromagnetic valve, such that contacts thereof are connected to each other. A magnetic field is generated in coils of a second relay by an OFF signal from the electromagnetic valve, such that contacts thereof are connected to each other. A stopwatch has a start terminal connected to the first relay and a stop terminal connected to the second relay. When the electromagnetic valve transmits a signal to the suckback valve to dispense the photoresist from the nozzle, a ON signal is transmitted to generate a magnetic field in coils of the first relay, while contacts of the first relay are connected to start the stop watch.

Abstract: A semiconductor circuit is provided including circuitry for producing a pulse. A plurality, n, of delay elements are provided each enabled and disabled in parallel by the pulse. Each delay element is adapted to transmit the pulse from an input to an output, with the pulse reaching the respective outputs at different times. A plurality, n−1, of detectors is provided each having an input coupled to an input of a corresponding delay element. Each detector is adapted to set a state of its output to a predetermined state, from a plurality of states, in response to receiving a portion of the pulse. The outputs of the detectors are coupled to output pins of the semiconductor circuit. A tester is provided that is adapted to couple to the semiconductor output pins and detect the state of the detector outputs.

Abstract: Oscillating precision of the first and the second oscillating sections each having the same oscillation frequency is determined in the oscillating precision determining section according to the timing of a signal supplied from the external time source, and in the internal time stepping control section, stepping control is provided over the internal time using a reference clock oscillated by any of the first and the second oscillating sections according to a result of determination of the oscillation precision.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components.

Abstract: A circuit measures a signal propagation delay through a series of memory elements. In one embodiment the memory elements are configured in series so that together they form a delay circuit. In another embodiment the memory elements are configured in a loop to form a ring oscillator. Each memory element propagates a signal to a subsequent memory element so that the time the signal takes to traverse all of the memory elements is proportional to the average delay induced by the individual elements. This proportionality provides an effective means for measuring the delays of those components. Various embodiments of the invention measure the speeds at which memory elements can be preset, cleared, written to, read from, or clock enabled.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. One embodiment of the invention includes a phase discriminator that samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

Abstract: A test signal retiming circuit that captures an input signal to produce a first output signal and generates a second output signal in response to the first output signal and a predetermined reference signal. The second output signal is resistant to an input signal timing variation. A verification is performed to insure the second output signal conforms to timing of a predetermined output signal. The input signal produces the first output signal by acquiring the input signal in a first buffer in response to a first signal and transferring the acquired input signal from the first buffer to a second buffer in response to the first signal. The first output signal is transferred from the second buffer to a third buffer in response to a second signal to produce a second output signal. The second output signal is resistant to a plurality of clock and data skews.

Abstract: A circuit measures a signal propagation delay through a series of memory elements on a programmable logic device. In one embodiment, a number of latches are configured in series. Each latch is initialized to store a logic zero. The first latch is then clock-enabled so that the output of the latch rises to a logic one. The logic one from the first latch clock-enables the second latch in the series so that the output of the second latch rises to a logic one, which in turn enables the next latch in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each latch to change in response to a clock-enable signal. Consequently, the delay through the series of latches provides a measure of the time required for one of the latches to respond to a clock-enable signal.

Abstract: A distance measurement apparatus for measuring distance to the target by measuring a time elapsed from the emission of pulsed light to the target until the receiving thereof. This apparatus comprising a light-emitting section, a light-receiving section, a delay circuit for delaying at least one of generation of the trigger signal with respect to a measurement start signal and the outputting of the measurement stop signal with respect to the reflected pulsed light and outputting thus delayed signal, a reference clock section, time measuring sections consisting of a start-side and stop-side fractional time signal measurement sections and a counter section, and a distance measurement section for determining, based thus measured items, the distance to the target according to the time from the emission of the pulsed light to the receiving thereof.

Abstract: A delay test system includes an electronic circuit, such as a normal circuit which has a portion to be tested and a plurality of flip-flop circuits. In this event, each of flip-flop circuits is serially connected to each other to perform a delay test for said normal circuit. Further, a first clock input terminal is connected to the flip-flips and a normal circuit to input a normal mode clock signal. Moreover, a second clock input terminal is connected to the flip-flop circuits and the normal circuit to input a test clock signal. With such a structure, an input and output operation of data signals is carried out in synchronism with edge timings determined by both the normal mode clock signal in the normal mode on the condition that the test clock signal is not supplied to the second clock input terminal. On the other hand, the first and second clock input terminals are separately driven by the normal mode clock signal and the teat clock signal in the test mode.

Abstract: A time measurement circuit (100) measures a time interval between two events. The time measurement circuit (100) includes two digital phase counters (10' and 10"), a period counter (210), and a digital calculator (310). The first digital phase counter (10') converts a time interval from a leading edge of a start signal to a leading edge of clock signal following the start signal into a first binary number. The second digital phase counter (10") converts a time interval from a leading edge of a stop signal to a leading edge of clock signal following the stop signal into a second binary number. The period counter (210) converts a time interval between the two leading edges of the clock signal into a third binary number. The digital calculator (310) combines the three binary numbers to generate a number representing the time interval between the start signal and the stop signal.

Abstract: Apparatus and method for measuring the time interval between a first event and a second event in a tester system. First and second time measurement circuits independently receive respective first and second events. The time measurement circuits each includes a coarse counter clocked by the master clock. The first coarse counter is activated by an initial event, and the first coarse counter stops counting upon activation of the first event. The second coarse counter is also activated by the initial event, and the second coarse counter stops counting upon activation of the second event. A first fine counter clocked by the master clock produces a count value representing the time interval between the first event and a first leading edge of the master clock. A second fine counter clocked by the master clock produces a count value representing the time interval between the second event and a second leading edge of the master clock.

Abstract: A circuit separately measures a selected one of the rising-edge and falling-edge signal propagation delays through one or more circuits of interest. A number of synchronous components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component clocks a subsequent synchronous component in the ring; the subsequent synchronous component responds by clocking a later component in the ring and by clearing a previous component to prepare it for a subsequent clock. The oscillator thus produces an oscillating test signal in which the period is proportional to the clock-to-out delays of synchronous components. This proportionality provides an effective means for measuring the clock-to-out delays of those components. Other embodiments include additional asynchronous test circuit paths for which the associated signal propagation delays are of interest.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. A phase discriminator samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

Abstract: A method and apparatus for measuring time intervals between electrical signals. A coincidence detection circuit is adapted to detect coincidence or near coincidence of two signals and to provide for selection from a plurality of predetermined delays to remove the coincidence. If the two input signals are periodic and have the same frequency, the apparatus also provides a signal from which both the time delay between the signals and the period of the signals may be determined at substantially the same point in time.

Abstract: A time measurement device for measuring a duration of an input signal based on a clock signal comprises a first gate for outputting a gate signal based on an input signal; a first holding circuit for holding the gate signal at the time of falling of the clock signal; a second holding circuit for holding the gate signal at the time of rising of the clock signal; a second gate for passing the clock signal according to either of the widths of output signals of the first and second holding circuits; a third holding circuit for holding an output state of the second holding circuit at the timing of a leading edge of an output of the first holding circuit; a fourth holding circuit for holding an output state of the second holding circuit at the timing of a trailing edge of an output of the first holding circuit; and a counter for counting the clock signal output from the second gate. The count value is corrected based on the outputs of the third and fourth holding circuits.

Abstract: A clock doubler circuit with duty cycle control includes an exclusive-OR, a toggle flip-flop, a plurality of control bit flip-flops, a primary delay element, a plurality of secondary delay elements, and a multiplexer. The toggle flip-flop has a clock input connected to an output of the exclusive-OR, and an inverted data output connected back to a data input of the toggle flip-flop and connected forward to an input of the primary delay element. An output of the primary delay element is connected to an input of the multiplexer and to individual inputs of the plurality of secondary delay elements which in turn, have outputs connected to other inputs of the multiplexer. A plurality of control bits generated, for example, by a computer program running on a host processor, are respectively provided to data inputs of the plurality of control bit flip-flops which in turn, have data outputs connected to select inputs of the multiplexer.

Abstract: A floating point timer comprises a floating point counter using a reference clock signal generated by a digital ring oscillator having an oscillation period that matches the delay of the worst case path through the floating point counter. The digital ring oscillator utilizes a digital delay line which repeatedly delays a bit for the oscillation period and feedback logic to reapply the delayed bit for another oscillation. The digital delay line includes enough high-precision digital delay elements whereby the oscillation period is at least as great as that of the delay of the worst case path through the floating point counter.

Abstract: A free loop oscillator system including a set of successive delay elements connected in series forming a free running loop oscillator, a set of taps disposed between the delay elements, a circuit for determining the speed of the free-running loop oscillator, and circuit for choosing a given tap in response to the speed of the free-running loop oscillator. Such a system may be implemented as a part of interval timer, a printer controller, a frequency synthesizer, an FM modulator, a digital-to-analog converter, or any other device which requires the availability of finely addressable signals since the taps disposed between the delay elements present signals much finer than any presently available clock.

Abstract: A programmable timing unit having a number of event markers circuits that receive a master clock signal and generate an output when a predetermined time occurs. Optionally, the event marker circuit can add an interpolated delay time to provide greater resolution than the master clock circuit. The output is programmably coupled to any of a number of function circuits. Each function circuit has a trigger input for receiving the event signal and output for providing the delayed output function.

Abstract: A self-setup non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate having a first input terminal coupled to receive an inverted signal of the primary clock signal. Further, a second logic gate is provided, having a first input terminal coupled to receive the primary clock signal. A first programmable delay portion is used to delay an output signal from the first logic gate an amount of time according to the selection signal, and a second programmable delay portion is used to delay an output signal from the second logic gate a predetermined amount of time according to the selection signal. Therefore, a first clock signal is generated from the output of the first logic gate, and a second clock signal is generated from the output of the second logic gate.

Abstract: A video camera, capable of being connected with a computer, for photographing animated images. The video camera includes: a camera main body for outputting image signals corresponding to the animated images; and a memory adapter, detachable from the video camera, for recording one of the animated images as a still picture. The memory adapter also sends back the image signals, corresponding to the still picture, to the video camera so that the video camera outputs the image signals corresponding to the still picture.

Abstract: To provide a time measuring apparatus which is compact and capable of highly accurate measurements, on a semiconductor chip, flip-flops constituting a delayed-signal holding circuit of a first channel and flip-flops constituting a delayed-signal holding circuit of a second channel are disposed alternatingly and in a single row in a circuit region of the delayed-signal holding circuits to latch delayed signals from a pulse-circulating circuit, and flip-flops for latching the same delay signals are mutually adjacent. Due to this, distances between the pulse-circulating circuit and the respective delayed-signal holding circuits become equal, and delay signals having no deviation in delay due to difference in wiring length are supplied to the respective channels, and so uniform measurement can be performed between the respective channels.

Abstract: A temperature-compensated high-speed timing circuit, which is particularly advantageous in read-interface circuits for disk-drive interface. The voltage on the integrating capacitor is compared against a voltage defined by the drop, on a resistor, induced by a current which is the combination of a reference current from a reference current generator with a temperature-dependent current from another current generator.

Abstract: A time measurement circuit (100) measures a time interval between two events. The time measurement circuit (100) includes two digital phase counters (10' and 10"), a period counter (210), and a digital calculator (310). The first digital phase counter (10') converts a time interval from a leading edge of a start signal to a leading edge of clock signal following the start signal into a first binary number. The second digital phase counter (10") converts a time interval from a leading edge of a stop signal to a leading edge of clock signal following the stop signal into a second binary number. The period counter (210) converts a time interval between the two leading edges of the clock signal into a third binary number. The digital calculator (310) combines the three binary numbers to generate a number representing the time interval between the start signal and the stop signal.

Abstract: A free loop oscillator system including a set of successive delay elements connected in series forming a free-running loop oscillator, a set of taps disposed between the delay elements, a circuit for determining the speed of the free-running loop oscillator, and circuit for choosing a given tap in response to the speed of the free-running loop oscillator. Such a system may be implemented as a part of interval timer, a printer controller, a frequency synthesizer, an FM modulator, a digital-to-analog converter, or any other device which requires the availability of finely addressable signals since the taps disposed between the delay elements present signals much finer than any presently available clock.

Abstract: A delay time measurement apparatus of delay circuit is configured to minimize the influence of periodic noises for accurately measuring the delay time.

Abstract: The present invention makes possible to generate pulses having set period in high speed. An address series from a pattern generator 11 is converted into two address series, each having two time enabling periods by conversion means 40. A period value memory is read out by these two series of address series. A first and a second fractions read out are stored in flip-flops (FF hereinafter) 41.sub.1 and 41.sub.2 respectively, and integers are stored in FF 43.sub.1 and 43.sub.2 respectively. The output of the FF 41.sub.2 is stored in a FF 46.sub.2. The outputs of the FFs 41.sub.1 and 41.sub.2 are summed and accumulated in an adder 45.sub.1 and the outputs of the FFs 41.sub.1 and 46.sub.2 are summed and accumulated in an adder 45.sub.2. The outputs of the FFs 43.sub.1 and 43.sub.2 are set in coincidence detection counters 62.sub.1 and 62.sub.2 via FFs 58.sub.1 and 58.sub.2 respectively. Each of the counters 62.sub.1 and 62.sub.

Abstract: A clock distributing circuit, that comprises a clock distribution output circuit for inputting an external clock, outputting a first clock that synchronizes with the external clock, and distributing the first clock to each of load circuits, and a distributed clock input circuit disposed on input stages of all or part of the load circuits and adapted for inputting the first clock and outputting a second clock that synchronizes with the input clock, wherein one of the clock distribution output circuit and the distributed clock input circuit includes a phase difference-voltage converting circuit for converting the phase difference between the input clock and the output clock into a voltage, and a voltage control type delay circuit for delaying the input clock corresponding to an output voltage of the phase difference-voltage converting circuit and for outputting the delayed input clock.

Abstract: Output pulses of a period which is an integral multiple of the fundamental period T are generated by coarse timing generating means 13 in correspondence with an integral part Di of timing set data read out of a memory 11, and the output pulses are distributed by distributing means 17 to set- and reset-side delay means 26s and 26r under the control of a waveform generation control circuit 18. Pieces of data Dr and Ds, which are obtained by adding a fractional part of the timing set data read out of the memory and set-side skew absorbing data and reset-side skew absorbing data, respectively, are provided as delay control signals to the set- and reset-side delay means 26s and 26r. The pulse distributed to the set-side delay means 26s is delayed by logical delay means 27s for any one of delay times 0, 1T and 2T in accordance with the integral value of the data Ds, and the thus delayed pulse is further delayed by fine delay means 28s in accordance with the fractional value of the data Ds.

Abstract: A Vernier delay line interpolator provides a precision level smaller than a clock period by delaying a periodic pulse signal in a delay line which has equally time-spaced taps and a total delay that is a harmonic H greater than 1 of the pulse period. The taps of the delay line are latched and decoded to derive the fraction of the pulse period that has passed. When the interpolator is combined with a coarse counter, misalignment between their outputs is prevented by having the coarse counter count both edges of the periodic pulse signal so as to provide redundant bits between the counter and the interpolator. If the redundant bits are not equal, the counter output is corrected before it is combined with the output of the interpolator.

Abstract: The disclosed apparatus includes first and second delay lines, the first delay line having an input tap and a set of n output taps F.sub.1, F.sub.2, . . . F.sub.n, and the second delay line having an input tap and a set of n output taps S.sub.1, S.sub.2, . . . S.sub.n, and each of the output taps has an associated delay interval. A first signal representative of a first event is applied to the input tap of the first delay line, and a second signal representative of a second event is applied to the input tap of the second delay line. The disclosed apparatus further includes a set of n latches L.sub.1, L.sub.2, . . . L.sub.n, and a set of n delay units D.sub.1, D.sub.2, . . . D.sub.n. The output signals generated by taps F.sub.i and S.sub.i are applied to a first input terminal and a second input terminal, respectively, of latch L.sub.i.

Abstract: A circuit arrangement for measuring a time interval by evaluating the number of complete cycles, and/or the fraction of a cycle, of a ring oscillator that occur(s) during the time interval to be measured, in which there are provided means to avoid a count ambiguity if the time interval ends at or about the completion of a cycle of the ring oscillator.

Abstract: According to the present invention, a process for use with automatic test equipment ("ATE") for determining a propagation delay in a semiconductor circuit is provided. In one embodiment of the invention, the process comprises the steps of determining an expected delay time by interpolating a first simulation capacitance, a second simulation capacitance, and an ATE capacitance, with a first simulated delay time and a second simulated delay time, the simulated delay times corresponding to the first and second simulated capacitances respectively, testing the semiconductor circuit with the ATE to determine an ATE delay time, and comparing the ATE delay time with the expected delay time to determine whether the propagation delay is acceptable.

Abstract: A programmable timing unit having a number of event markers circuits that receive a master clock signal and generate an output when a predetermined time occurs. Optionally, the event marker circuit can add an interpolated delay time to provide greater resolution than the master clock circuit. The output is programmably coupled to any of a number of function circuits. Each function circuit has a trigger input for receiving the event signal and output for providing the delayed output function.

Abstract: A control signal generator for generating a plurality of control and timing ignals which are supplied to a scan converter. The control and timing signals are utilized by the logic elements of the scan converter to process the incoming pixel data from a missile's seeker allowing the data to be supplied to a video monitor for viewing. The control signal generator includes a state machine which generates four state variable signals and a cycle counter which generates a binary count thirty one signal which allows the state machine to cycle through six predetermined states until the scan converter completes processing of incoming pixel data from each detector of the missile's seeker. The count thirty one signal and the four state variable signals are decoded by five decoders which generate the timing and control signals for the logic elements of the scan converter.

Abstract: A time interval unit which operates in accordance with electronic sampling techniques and employing a pair of identical sampling interpolators which are respectively triggered at the start and stop of the time interval to be measured. Each time interval unit includes a GHz frequency sinusoidal clock signal generator and a time counter in the form of a pulse counter and a pair of sampling type interpolators which are respectively triggered on in response to a start and a stop signal. When triggered, each interpolator samples the instantaneous amplitude of the in-phase(x) and quadrature(y) components of the sinusoidal clock signal. From the samples of the x and y components and the pulse counter's result, the elapsed time between two events is computed to a psec accuracy.

Abstract: An electronic vernier for a laser range finder enhances the resolution of the range finder to that of the vernier without increasing the frequency of the range clock. The range finder includes a range counter circuit for storing the total integer number of clock pulses produced by a range clock and counted by a range counter. The vernier includes a tapped delay line which subdivides the clock pulses into a predetermined plurality of equal increments. The contents of the tapped delay line at the time of transmission of the ranging pulse, and reception of the reflected ranging pulse identify the phase of the clock pulse. An electronic storage register of the vernier captures and stores the contents of the tapped delay line, and then transfers vernier transmission and reception fractions to a system controller for computing a corrected range measurement from the total integer number of clock pulses produced by the range clock and counted by the range counter.

Abstract: A laser speed detector is described which includes a laser rangefinder which determines the time-of-flight of an infrared laser pulse to a target and a microprocessor-based microcontroller. The device is small enough to be easily hand-held, and includes a trigger and a sighting scope for a user to visually select a target and to trigger operation of the device upon the selected target. The laser rangefinder includes self-calibrating interpolation circuitry, a digital logic-operated gate for reflected laser pulses in which both the "opening" and the "closing" of the gate can be selectably set by the microcontroller, and dual collimation of the outgoing laser pulse such that a minor portion of the outgoing laser pulse is sent to means for producing a timing reference signal.

Abstract: A timing generator which is capable of generating a timing signal with high resolution and accuracy which is not affected by the changes in temperature and power supply voltage or the self-generated heat of the circuit component. The timing signal generator can generate a timing signal which has a delay time combined with a large delay time which is greater than the clock signal period and a small delay time which is smaller than the clock signal period.

Abstract: A delay time measuring circuit includes a delay circuit for changing the delay times of first and second clock signals output to measure the delay time of an evaluated circuit according to an externally supplied control voltage, and a voltage controlled oscillator whose oscillation frequency is controlled by the same control voltage as that used for the delay circuit, and is constructed to measure the delay time of the evaluated circuit based on an output of the voltage controlled oscillator. Therefore, it is possible to precisely evaluate the operation speed of a circuit operating at high speed.

Abstract: A time code receiver 18 is used to provide a rough estimate of an elapsed time, which is then enhanced by additional circuitry 53. The time code receiver 18 uses a square wave reference oscillator to produce a digital time value 56. This reference oscillator is also fed into a phase detection circuit 34 along with an output 30 from a second oscillator circuit which is triggered upon detection of the occurrence of the event 24. The measured phase difference of the time code receiver reference oscillator 20 and the second oscillator signal 30 is used to produce digital values 38 and 40 that represent a fraction of the clock cycle. This fractional clock cycle or "fine time" value is added to digital time value 56 from the time code receiver 18 to increase the resolution of time measurement. This method of measuring times of events can be used to measure events such as the arrival of radio frequency signals at remotely based receivers in order to determine the distance of the transmitter from the receivers.

Abstract: Round trip absolute delays through a transmission system are measured. A modulation signal S1 of radian frequency .omega. is modulated onto a carrier. The modulation frequency is changed. While the change propagates through the system, the returned demodulated S2 signal remains at the old radian frequency .omega.. During that time, signal S1 advances in phase relative to signal S2. After the propagation time d which is equal to the network delay, the two signals stabilize at a fixed phase offset. The increase .theta..sub.o in the phase offset during the propagation time is determined. The delay d is then determined by dividing the phase offset increase .theta..sub.o by the difference between the two modulation frequencies.

Abstract: A digital data propagation delay margin monitoring circuit that includes (a) a digital data propagation unit having a send flip-flop, a combinatorial delay, and a receive flip-flop; and (b) a margin detection circuit having a test flip-flop that receives the same input as the receive flip-flop and is configured to have a set up time margin or a hold time margin that is less than the set up margin or hold time margin of the receive flip-flop by a predetermined amount, depending upon which margin is being monitored. The outputs of the receive flip-flop and the test flip-flop are compared by a comparison circuit which provides an indication of when the outputs of the receive flip-flop and the test flip-flop are different, which indicates that the monitored margin of the receive flip-flop has been reduced to a predetermined margin or less.

Abstract: A method and apparatus for the measuring of a delay in a delay circuit by making a continuous frequency measurement is proposed. The phase-locking of a variable frequency signal applied to the delay circuit allows the user to significantly improve the precision and accuracy of the time delay measurement. A scheme to extract the number of cycles stored in the delay circuit is also disclosed.

Abstract: A laser speed detector is described which includes a laser rangefinder which determines the time-of-flight of an infrared laser pulse to a target and a microprocessor-based microcontroller. The device is small enough to be easily hand-held, and includes a trigger and a sighting scope for a user to visually select a target and to trigger operation of the device upon the selected target. The laser rangefinder includes self-calibrating interpolation circuitry, a digital logic-operated gate for reflected laser pulses in which both the "opening" and the "closing" of the gate can be selectably set by the microcontroller, and dual collimation of the outgoing laser pulse such that a minor portion of the outgoing laser pulse is sent to means for producing a timing reference signal.

Abstract: A laser survey instrument is described which includes a laser rangefinder which determines the time-of-flight of an infrared laser pulse to a target, a magnetic compass module which produces an electronically readable compass signal, a vertical angle sensor module which produces an electronically readable inclination signal, and a microprocessor-based microcontroller. The device is small enough to be easily hand-held, and includes a trigger and a sighting scope for a user to visually select a target and to trigger operation of the device upon the selected target. The sighting scope preferably has means for measuring the apparent width of the target.