Abstract: A method for cancelling, from servo signals read in a read channel while a write channel is active, interference caused by write signals in the write channel, includes generating a predicted channel response signal from the write signals in a data clock domain, resampling the generated predicted channel response signal using a clock in the data clock domain having a rate corresponding to a servo clock from a servo clock domain, transferring the resampled predicted channel response signal from the data clock domain to the servo clock domain and aligning phase of the transferred resampled predicted channel response signal with phase of the servo clock, determining a domain-boundary-crossing delay incurred in the transferring, based on the domain-boundary-crossing delay, synchronizing the phase-aligned transferred resampled predicted channel response signal with the servo signals, and subtracting the synchronized phase-aligned transferred resampled predicted channel response signal from the servo signals.

Abstract: A semiconductor integrated circuit includes an equalizer circuit configured to amplify a signal component in a particular frequency band of an input signal on a signal path after a coupling capacitor, a sampler circuit configured to convert a first signal outputted from the equalizer circuit to a digital signal, a detector circuit configured to output a second signal based on a frequency of appearance of two values included in the digital signal, and a compensator circuit configured to compensate for a shift of a DC voltage level on the signal path after the coupling capacitor based on the second signal outputted from the detector circuit.

Abstract: In an embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect according to a bus clock signal; a first receiver to receive second information from at least one of the plurality of devices via the interconnect according to the bus clock signal; and a clock generation circuit to generate the bus clock signal having an asymmetric duty cycle. Other embodiments are described and claimed.

Abstract: Disclosed is a communication method of a satellite and a ground station and apparatuses performing the same. The communication method includes transmitting a plurality of frames to a satellite based on a beam hopping time plan (BHTP) of the satellite and a ground station and synchronizing the BHTP based on an index of a frame received through a beam switching window (BSW) allocated to the ground station among the plurality of frames, and an identification value indicating at least one sub-frame included in the frame.

Abstract: There is disclosed in one example a digital phase-locked loop (DPLL) circuit adapted to avoid loop-bandwidth tradeoff, the circuit including: a frequency dimension frequency detector having an external frequency input and a feedback frequency input, the frequency dimension frequency detector including circuitry to measure a frequency difference between the external frequency input and the feedback frequency input and to drive an impulse signal, wherein the impulse signal is of a first species if the difference is positive and of a second species if the difference is negative; and a number-controlled oscillator (NCO) including circuitry to drive an output clock and to adjust the frequency of the output clock responsive to the impulse signal, wherein an output of the NCO provides the feedback frequency input of the frequency dimension frequency detector.

Abstract: There is disclosed in one example a digital phase-locked loop (DPLL) circuit adapted to avoid loop-bandwidth tradeoff, the circuit including: a frequency dimension frequency detector having an external frequency input and a feedback frequency input, the frequency dimension frequency detector including circuitry to measure a frequency difference between the external frequency input and the feedback frequency input and to drive an impulse signal, wherein the impulse signal is of a first species if the difference is positive and of a second species if the difference is negative; and a number-controlled oscillator (NCO) including circuitry to drive an output clock and to adjust the frequency of the output clock responsive to the impulse signal, wherein an output of the NCO provides the feedback frequency input of the frequency dimension frequency detector.

Abstract: The present invention provides a signal sending apparatus, a signal detection apparatus, a signal sending and detection system, a signal sending method, and a signal detection method. The apparatus determines a time unit that is in each time window and that is used to transmit a synchronization signal, and transmits the synchronization signal in the determined time unit in each time window. Therefore, a synchronization signal is always located in a time unit that has a fixed location in each time window, so that a device at a receive end needs to perform detection only in a fixed time unit in each time window, thereby reducing complexity of designing and detecting the synchronization signal.

Abstract: According to one embodiment, a memory controller includes a first volatile memory, a second volatile memory, and a controller. The first volatile memory temporarily stores therein data acquired from outside. The controller controls the temporarily stored data to be transferred from the first volatile memory to a non-volatile memory, stores correspondence information of the transferred data to the non-volatile memory in the second volatile memory, and updates correspondence information stored in the non-volatile memory based on the correspondence information stored in the second volatile memory by using the first volatile memory after the data transfer as a work area. The correspondence information represents association between a logical address and a physical address of the data.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: Described embodiments provide a magnetic mass storage device with a system clock phase-locked to servo address marks on the magnetic disk. A head sequentially reads multiple adjacent servo address marks in a spiral track of servo address marks. When a servo address mark detector detects a mark, the count value of a counter driven by the system clock is sampled and held by a latch. A system clock synthesizer calculates differences in value between successively sampled count values from the latch, averages the differences in value to create an average difference value, and normalizes a difference between the average difference value and a target value to create a phase error value. The phase of the system clock is updated using the phase error value.

Abstract: The present disclosure describes techniques for DVD-RAM header or land/groove detection. In some aspects, a wobble signal is integrated, an offset is removed from the integrated wobble signal, and a header is detected in the non-offset integrated wobble signal. In some aspects, a threshold value is adjusted based on a comparison of the received wobble signal and the threshold value, and a header is detected based on the adjusted threshold value.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.

Abstract: A system for providing an accumulated phase to an interpolator of a read channel, the interpolator configured to provide a digital clock signal. A frequency accumulator is configured to generate a frequency offset based on a difference between the digital clock signal and a desired clock signal. A zero phase start module is configured to, during a zero phase start, output an incremental phase jump. A phase accumulator is configured to generate the accumulated phase based on the difference between the digital clock signal and the desired clock signal, and, during the zero phase start, the incremental phase jump output by the zero phase start module, or the frequency offset generated by the frequency accumulator or a predetermined frequency offset.

Abstract: A method and device for determining frequency error to extend the pull-in range of a timing recovery circuit for a storage device such as an optical disc drive. A code associated with a storage format of the storage device is detected, and the distance between occurrences of the code is determined. The calculated distance is compared with the expected distance to determine the difference. Based on the difference, the frequency error is determined.

Abstract: New and useful methods and systems for detecting sync signals/patterns in streams of data are disclosed. For example, in an embodiment system for processing data includes a first module having dedicated processing circuitry configured to detect a sync signal embedded in a received stream of data and to produce an output stream of data, and second module that includes a firmware-controlled processor configured to correct sufficient errors within the received stream of data so as to allow the first module to detect the sync signal on a condition when the first module by itself is incapable of resolving the sync signal caused by the errors in the received stream of data.

Abstract: A control device includes: a delay unit configured to delay a signal for use in exposure of a master disc; and a control unit configured to adjust an amount of delay of the signal so that an exposure pattern that satisfies an information recording medium format is formed on a master disc rotated by a constant linear velocity (CLV) system.

Abstract: A hard disk drive includes a processor to automatically adjust a threshold level for finding sync-marks. The processor determines all possible sync-mark patterns for a particular pattern length and analyzes each pattern with reference to real world data. The pattern with the largest distance gap is used. The threshold level is then adjusted dynamically to produce the lowest possible failure rate for the given pattern.

Abstract: A hard disk drive includes a processor to automatically adjust a threshold level for finding sync-marks. The processor determines all possible sync-mark patterns for a particular pattern length and analyzes each pattern with reference to real world data. The pattern with the largest distance gap is used. The threshold level is then adjusted dynamically to produce the lowest possible failure rate for the given pattern.

Abstract: New and useful methods and systems for detecting sync signals/patterns in streams of data are disclosed. For example, in an embodiment system for processing data includes a first module having dedicated processing circuitry configured to detect a sync signal embedded in a received stream of data and to produce an output stream of data, and second module that includes a firmware-controlled processor configured to correct sufficient errors within the received stream of data so as to allow the first module to detect the sync signal on a condition when the first module by itself is incapable of resolving the sync signal caused by the errors in the received stream of data.

Abstract: A disk drive is disclosed comprising a head and a disk comprising a plurality of servo tracks, wherein each servo track comprises a plurality of servo sectors. The disk drive further comprises control circuitry comprising a servo control system operable to actuate the head over the disk in response to the servo sectors. The disk is rotated at a first speed and the servo sectors are read at a first servo sample frequency to generate first servo samples. The disk is rotated at a second speed different from the first speed and the servo sectors are read at a second servo sample frequency to generate second servo samples. The second servo samples are processed to measure a frequency response of the servo control system proximate the first servo sample frequency.

Abstract: A control device includes: a delay unit configured to delay a signal for use in exposure of a master disc; and a control unit configured to adjust an amount of delay of the signal so that an exposure pattern that satisfies an information recording medium format is formed on a master disc rotated by a constant linear velocity (CLV) system.

Abstract: A recording adjustment method capable of controlling an edge position of a mark with high accuracy. Based on an acquired read-out signal waveform, a starting position of a last pulse is adjusted such that a so-called L-SEAT shift value for an end edge of the mark becomes minimum.

Abstract: Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation.

Abstract: A read signal evaluating means for ensuring compatibility in an optical phase multilevel recording and reading system is provided. In addition, a decoding means not large in circuit scale is provided. An optical phase is modulated based on user data, and phase information thus obtained is recorded in a recording medium. Then, the phase information recorded in the recording medium is optically read, and is converted into an electric signal. The signal is subjected to adaptive equalization and to partial response most-likely decoding. A shift in a time axis direction from a target wave of a predetermined pattern is detected from the read phase information and a statistical average is calculated. Meanwhile, a value of the phase read from the predetermined pattern is extracted from the read phase information and a statistical average is calculated.

Abstract: Noise generation in transferring data is suppressed or prevented by transferring data at a data transfer rate according to the amount of data to be transferred to a memory. In a reproducing apparatus, when a read unit or both reads data from a storage medium or both, a determination unit determines the type of the storage medium from which the data is read, then, according to the determined type of the storage medium, a transfer rate change unit orders a data transfer unit to use a preset transfer rate corresponding to the type of the storage medium. The data transfer unit transfers the read data to the temporary storage unit at the ordered transfer rate. This allows data to be transferred without a significant change in the amount of data transfer, which suppresses or prevents noise.

Abstract: A digital loop filter receives a phase error output from a phase comparator to generate a digital frequency value. This digital frequency value is converted into an analog voltage by a D/A converter, and VCO outputs a synchronizing dock of frequency corresponding to the voltage output from the D/A converter. The phase error output from a phase comparator is gain-corrected by a product of an output from the digital loop filter and a specific coefficient “A”, and delivered to digital loop filter. The phase error input to the digital loop filter is changed in proportion to the output clock frequency, whereby the PLL loop as whole linearly controls the loop characteristic depending on the output clock frequency.

Abstract: Aspects of the disclosure provide a signal processing circuit that includes a signal processing circuit includes a processing path configured to process an electrical signal to produce input data samples, and a feed-forward correction module configured to delay the input data samples to produce delayed data samples, to apply the delayed data samples to a timing loop during periods when a profile variation of the data samples is not detected, and to apply the input data sample to the timing loop during periods when a profile variation of the data samples is detected.

Abstract: Method for reading data from an optical disc comprising a substrate layer, a read-only data layer, and a nonlinear layer with a super-resolution structure disposed on the data layer, the read-only data layer including diffractive pits and lands having a length larger than the diffraction limit of the pickup and super-resolution pits and lands having a length smaller than the diffraction limit of the pickup, the method comprising the steps of using a pickup including a laser for providing a HF signal for retrieving of the data of the data layer, providing a constant laser power for retrieving of the data, and pulsing the laser at the end of a diffractive pit or land. The Apparatus comprises a pickup with a laser and a comparator responsive to a threshold level and to the HF signal, for providing a trigger signal for pulsing of the laser.

Abstract: Circuitry for controlling mode selection of a CD/DVD reader is described. In one embodiment, the CD/DVD reader has a first device having at least one analog output, a second device having at least one digital input and at least one analog input, and an interface circuit coupling the analog output of the first device to the digital input and the analog input in the second device. The interface circuit includes a circuitry to use a single control signal from the analog output of the first device to control the digital input and the analog input in the second device. Other embodiments are also described.

Abstract: A method and device for determining frequency error to extend the pull-in range of a timing recovery circuit for a storage device such as an optical disc drive. A code associated with a storage format of the storage device is detected, and the distance between occurrences of the code is determined. The calculated distance is compared with the expected distance to determine the difference. Based on the difference, the frequency error is determined.

Abstract: In step S1, the address generator generates address information composed of a sync signal which is recorded on an optical disc, address data and an error correction code for the address data, pre-encodes and supplies it to a modulator. At the same time, a carrier signal generator generates a carrier signal which is to carry the address information, and supplies it to the modulator. In step S2, the modulator makes MSK modulation of the carrier signal supplied from the carrier signal generator on the basis of the pre-encoded address information supplied from the address generator, and supplies a resultant MSK modulation signal to a wobbling unit. In step S3, the wobbling unit forms, on the optical disc, a spiral groove wobbled adaptively to the MSK modulation signal supplied from the modulator. In this optical disc, a given address can be accessed quickly and accurately.

Abstract: A reading unit reads sound signals recorded in a recording medium. A buffer unit temporarily stores the sound signals which is read by the reading unit. A recording unit records the sound signal which is temporarily stored in the buffer unit. A reproducing unit reproduces the sound signals which is recorded in the recording unit. A controller controls reading speed of the reading unit. The sound signals include a first set of signals and a second set of signals. The reading unit reads the first set of signals at a first reading speed and reads the second set of signals at a second reading speed which is faster than the first reading speed after reading the first set of signals.

Abstract: A recording apparatus, which records information in an optical recording medium, includes: a mode-lock laser unit including a saturable absorber section that applies a bias voltage, a gain section that feeds a gain current, a semiconductor laser that emits laser light used to record the information on the optical recording medium, and an external resonator; an optical modulation unit performing amplification modulation on the laser light emitted from the mode-lock laser unit; a reference signal generation unit generating a master clock signal and supplying a signal synchronized with the master clock signal to the gain section of the semiconductor laser; a recording signal generation unit generating a recoding signal based on the master clock signal; and a driving circuit generating a driving pulse used to drive the optical modulation unit based on the recording signal.

Abstract: There is provided a light source including a mode-lock laser unit that includes a semiconductor laser and an external resonator unit and emits a laser beam having a predetermined frequency, the semiconductor laser including a saturable absorber unit that applies a reverse bias voltage and a gain unit that applies a gain current, a semiconductor optical amplifier that performs amplification modulation on the laser beam emitted from the mode-lock laser unit, a laser clock generating unit that generates a laser clock synchronized with the laser beam based on a signal detected from the saturable absorber unit when the laser beam oscillates in the mode-lock laser unit, and a modulating unit that generates a driving current synchronized with the laser clock and applies the driving current to the semiconductor optical amplifier.

Abstract: Aspects of the disclosure provide an apparatus. The apparatus includes a pick-up unit, such as an optical pick-up unit, a wobble channel and a defect detector. The pick-up unit generates a push-pull signal corresponding to a wobbled track of a storage medium. The wobble channel includes circuits to receive the push-pull signal, obtain a wobble signal from the push-pull signal, and calculate a wobble amplitude metric based on the wobble signal. The defect detector compares the wobble amplitude metric to a threshold to detect wobble defects.

Abstract: Aspects of the disclosure provide a method for signal processing. The method includes receiving a tracking signal corresponding to a recording track on a storage medium. The tracking signal is frequency modulated with encoded symbols. Further, the method includes phase-locking an internal signal to the tracking signal to cause a frequency of the internal signal to be locked at a center frequency of the tracking signal, detecting a drift between the internal signal and the encoded symbols, and phase-shifting the internal signal to compensate for the drift.

Abstract: A servo control device includes: a phase compensator configured to generate a plurality of types of control values for controlling a driver based on a signal output from an optical pickup, and output the control values; and a transfer data generator configured to serially transfer the control values to the driver. The phase compensator sends, to the transfer data generator, a notification that the phase compensator has output a control value which needs to be sent with a reduced delay among the control values. In response to the notification, the transfer data generator determines whether or not the transfer data generator is transferring one of the control values, and if the transfer data generator is not transferring one of the control values, the transfer data generator starts transferring a control value associated with the notification among the control values.

Abstract: A phase error detection apparatus includes: a sampling block; a first phase error calculation block; a second phase error calculation block; and a selective output block.

Abstract: A signal processing device with dynamic phase detector switching includes a first phase detector of a first type, a second phase detector of a second type, and a mixing device to switch between using output from the first phase detector and output from the second phase detector in real time based on specified changes in an input signal being fed to the signal processing device.

Abstract: A method for determining a phase difference of a tracking error signal is provided. The method includes: predetermining a plurality of phase differences, measuring MPP and SPP signals, establishing a phase difference curve by use of an amplitude ratio between (MPP+SPP) and (MPP?SPP), measuring MPP and SPP signals for a tracking error signal under test, calculating the amplitude ratio (MPP+SPP)/(MPP?SPP), and comparing with the phase difference curve to promptly determine the phase difference.

Abstract: An apparatus includes a read/write head disposed on a slider, a control circuit disposed on the slider, and an adjustable delay line disposed on the slider. The adjustable delay line delays transmission of aligned write data to the read/write head by an adjustable delay. The adjustable delay is controlled by the control circuit a function of read synchronization data provided by the read/write head.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, an inter-track interference signal estimator circuit, and a sync mark detector circuit. The data buffer is operable to store a previous track data set that includes a first sync pattern. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set based at least in part on the previous track data set and a current track data set. The current track data set includes a second sync pattern. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set based at least in part on the previous track data set and the inter-track interference response from the previous track data set.

Abstract: Analog components whose characteristics greatly differ from one another are removed as much as possible from an optical disc drive. Provided are means 38, 39 for changing the sampling frequency of a pulsed read signal to a different frequency, means 40, 41 for changing the modulation clock frequency by the same ratio as the sampling frequency, and means for automatically setting the sampling frequency changing means and the modulation clock changing means based on the channel clock.

Abstract: A servo control device includes a plurality of reproduction channels, a plurality of analog/digital (A/D) converters, a servo error detecting circuit that generates a servo error signal, a servo signal processing device that executes predetermined processing for the servo error signal to generate a control signal, and a sampling frequency converter that converts the sampling frequency between the servo error detecting circuit and the servo signal processing device. A first clock is included as a sampling clock of the A/D converters and a processing clock of the servo error detecting circuit. A second clock is included as a processing clock of the servo signal processing device. The sampling frequency converter converts the sampling frequency by processing the servo error signal by the servo error detecting circuit in synchronization with the first clock and processing the signal processed in synchronization with the first clock in synchronization with the second clock.

Abstract: An asynchronous interface circuit for transferring a data stream between different clock domains, the asynchronous interface circuits includes a data holding circuit for sequentially receiving and transferring data of the data stream in synchronism with a first clock signal, and holding the received data until an input of a next data, an asynchronous memory for sequentially receiving the data held in the data holding circuit in synchronism with the first clock signal and for outputting the data in the order of inputting in synchronism with a second clock signal. The asynchronous interface circuit further includes a monitor for detecting an operating state of the asynchronous memory, and a selector for selecting one of the data output from the asynchronous memory and the data output from the data holding circuit on the basis of a detecting result of the monitor.

Abstract: Aspects of the disclosure provide a signal processing circuit that includes a signal processing circuit includes a processing path configured to process an electrical signal to produce input data samples, and a feed-forward correction module configured to delay the input data samples to produce delayed data samples, to apply the delayed data samples to a timing loop during periods when a profile variation of the data samples is not detected, and to apply the input data sample to the timing loop during periods when a profile variation of the data samples is detected.

Abstract: A recording device includes a plurality of channels configured to record data to an optical recording medium, a reception unit configured to receive data transmitted from an external device, a storage unit configured to temporarily store the data that is received by the reception unit, and a distribution control unit configured to read the data that is stored in the storage unit and distribute the data by a block unit to the plurality of channels based on transfer time of the data and recording time to the optical recording medium so that record processing of the plurality of channels are simultaneously ended.

Abstract: Aspects of the disclosure provide an apparatus. The apparatus includes a pick-up unit, such as an optical pick-up unit, a wobble channel and a defect detector. The pick-up unit generates a push-pull signal corresponding to a wobbled track of a storage medium. The wobble channel includes circuits to receive the push-pull signal, obtain a wobble signal from the push-pull signal, and calculate a wobble amplitude metric based on the wobble signal. The defect detector compares the wobble amplitude metric to a threshold to detect wobble defects.

Abstract: Various embodiments of the present invention provide apparatuses, systems and methods for heat assisted magnetic recording. For example, an apparatus is disclosed that includes a signal generator operable to generate laser trigger pulses at the transition rate of the magnetic write data signal, a variable delay element operable to control an alignment between the laser pulse control signal and the magnetic write data signal, a phase difference detector operable to control the variable delay element, a triggerable pulse generator circuit operable to generate a laser pulse control signal based on the laser trigger pulses, a magnetic write head operable to record data to a magnetic storage medium under control of the magnetic write data signal, and a laser diode operable to heat the magnetic storage medium under control of the laser pulse control signal.

Abstract: An optical disk structure and optical disk recorder which enables data to be rewritten onto the recording layer of the optical disk. A clock reference structure is permanently formed along servo tracks of the optical disk. An optical transducer is coupled to the clock reference structure and generates a clock reference signal simultaneously with writing new data onto the recording layer of the optical disk. The data is written as data marks along the servo tracks. Each of the data marks includes edges. The edges of the data marks are recorded in synchronization with a write clock. The write clock is phase-locked with the clock reference signal. Therefore, the edges of the data marks are aligned with the clock reference structure with sub-bit accuracy. Standard DVD-ROM disk readers are not able to detect the high spatial frequency of the clock reference structure.