Abstract: Example systems, apparatus, and methods receive audio information including a plurality of frames from a source device, wherein each frame of the plurality of frames includes one or more audio samples and a time stamp indicating when to play the one or more audio samples of the respective frame. In an example, the time stamp is updated for each of the plurality of frames using a time differential value determined between clock information received from the source device and clock information associated with the device. The updated time stamp is stored for each of the plurality of frames, and the audio information is output based on the plurality of frames and associated updated time stamps. A number of samples per frame to be output is adjusted based on a comparison between the updated time stamp for the frame and a predicted time value for play back of the frame.
Type:
Grant
Filed:
July 1, 2019
Date of Patent:
August 31, 2021
Assignee:
Sonos, Inc.
Inventors:
Nicholas A. J. Millington, Michael Darrell Andrew Ericson
Abstract: Embodiments of a method and a device are disclosed. In an embodiment, an electronic device includes a plurality of input ports configured to receive at least two serial communication signals, an encoder circuit configured to encode the at least two serial communication signals based on signal edges of the at least two serial communication signals to generate an encoded serial communication signal, the encoded serial communication signal enabling reconstruction of the at least two serial communication signals independent of a clock signal, and a transmitter configured to transmit the encoded serial communication signal.
Type:
Grant
Filed:
June 18, 2019
Date of Patent:
April 21, 2020
Assignee:
NXP B.V.
Inventors:
Abhijeet Chandrakant Kulkarni, Siamak Delshadpour, Krishnan Tiruchi Natarajan, Steven Daniel
Abstract: A universal asynchronous receiver/transmitter (UART) module is disclosed. The UART module may include an edge detector coupled with a data line of the UART module, wherein the edge detector resets a counter on a rising and a falling edge.
Abstract: Embodiments of various methods, devices and systems are described herein that use a unified bus communication protocol. One such device comprises an interface for sending and receiving signals, and a mux and sync engine coupled to the interface and configured to determine time slots for sent and received signals according to a unified bitstream frame format. The unified bitstream frame format comprises a plurality of frame channels for transmitting data in a bitstream mode of communication such that data from the frame channels are time-multiplexed across the frame channels one bit at a time, wherein one of the frame channels is allocated as a control channel comprising individual control bits from control data, and at least one of the frame channels is allocated as a virtual frame channel comprising individual data bits taken from digital word data.
Abstract: A system comprises a first host bus adapter (HBA) that uses a first context to facilitate the transmission of packets through a logical connection through the first HBA. The system also comprises a second HBA and memory in which the first context is stored. The memory is accessible by both of the first and second HBAs. Upon receiving a packet associated with the logical connection, the second HBA accesses the memory to use the first context to process the packet in accordance with the first context.
Type:
Grant
Filed:
October 24, 2006
Date of Patent:
October 26, 2010
Assignee:
Hewlett-Packard Development Company, L.P.
Inventors:
Michael Sean McGee, Darda M. Chang, Daniel N. Cripe