Abstract: Embodiments of the present disclosure relate to a system and a method for operating the system. The operating mode of a data processing circuit is changed according to a request indicating whether or not a first clock or a second clock is to be changed. Data transmitted from a first module to a second module inside the system is processed according to the operating mode of the data processing system. Accordingly, when the clock of one of modules included in the system changes, the module can quickly switch to a state in which the same can transmit/receive data to/from another module included in the system, and the performance of data transmission/reception between the modules included in the system can be optimized.

Abstract: A wireless communication device transmits a device beacon in accordance with a system timing of a wireless wide area network (WWAN). For one example, the beacon is transmitted relative to WWAN uplink channels of the time-frequency space of the uplink WWAN channel assignment. In response to the reception of the device beacon by another wireless communication device, a peer to peer communication session is established.

Abstract: Authenticator plugin interface for an enterprise virtualization portal is provided. An example method for evaluating a portal access request may comprise: receiving, by a virtualization management platform, a request initiated by a requestor for access to an enterprise virtualization portal associated with the virtualization management platform, the request comprising a login credential; transmitting, to a first authentication system, a first authentication query comprising an identifier of a first data type, and a first value of the first data type, wherein the first value is derived from the login credential; receiving a first response message comprising an identifier of a second data type, and an authentication response of the second data type; and responsive to evaluating the authentication response, granting the requestor access to the enterprise virtualization portal.

Abstract: A device of the present invention, connected to a Communication Module (CM) via two signal lines, constructs a frame, formatted according to a second Communication Protocol (CP), from bit signals, which are being received from the CM via one signal line, corresponding to data of a frame of a particular format defined by a first CP, to transmit the constructed frame to a bus while transmitting data detected from the bus to the CM via the other signal line in the form of a frame of the particular format. The device measures a width of a pulse signal inserted at a predetermined position in a frame of the particular format being received from the CM first after power on, identifies a bit rate, based on the measured width, at which the CM transceiver data, and applies the identified bit rate to data communication with the CM.

Abstract: A correct commutation is realized even if a communication error occurs due to a change in an actuator drive current. An electronic control unit that includes a communication section outputting a control signal and that can transmit the control signal to an actuator connected to the electronic control unit via a power line, includes an actuator operation detection section. When the actuator operation detection section detects an actuator operation, the communication section retransmits the control signal at timing of detecting the actuator operation.

Abstract: A mobile device includes a slave device that receives first data provided to a serial data line in synchronization with a clock signal provided through a serial clock line, and outputs second data to the serial data line in synchronization with the clock signal; and a master device that generates the clock signal and provides the first data to the serial data line in synchronization with the generated clock signal, or receives the second data output to the serial data line in synchronization with the clock signal. The master device generates the clock signal of a first frequency upon transmitting the first data, and generates the clock signal of a second frequency, which is lower than the first frequency, upon receiving the second data.

Abstract: A method of operating a mobile communication network including plural radio transceiver stations serving and managing communications between mobile communication devices.

Abstract: Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.

Abstract: Embodiments of this disclosure provide an apparatus and method for generating a transmitting sequence, a training sequence synchronization apparatus and method, an apparatus and method for estimating channel spacing and a system. The training sequence synchronization apparatus includes: a delay correlation processing unit configured to parallelly perform autocorrelation operations of different delay amounts on a receiving sequence containing a periodic training sequence to obtain multiple parallel correlation sequences; a superimposition processing unit configured to perform a superimposition operation on the multiple parallel correlation sequences to obtain a synchronization correlation sequence; and a synchronization extracting unit configured to perform a synchronization position extraction on the synchronization correlation sequence to obtain a synchronization position of the training sequence. With the embodiments of this disclosure, anti-noise performance of the training sequence may be enhanced.

Abstract: Embodiments of bus interface systems and methods of operating the same are disclosed. In one embodiment, a bus interface system includes a master bus controller and multiple slave bus controllers that are each coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. Each of the slave bus controllers decodes the first set of data pulses along the bus line representing the payload segment and performs an error check. Each slave bus controller is then configured to generate an acknowledgement pulse along the bus line to indicate that the slave bus controller's particular error check was passed. In this manner, the bus interface system can perform a group write bus function and the master bus controller can determine that the multiple slave bus controllers each received an accurate copy of the payload segment.

Abstract: Methods, systems and devices related to bidirectional edge-based pulse width modulation communication systems are disclosed. In some implementations, upon receipt of a predetermined trigger pulse at least two slave devices perform an action.

Abstract: A motion analysis system includes first to N-th (N is an integer of 2 or more) sensor units which is attached to an object, an analysis unit which obtains a plurality of items of sampling data output from the sensor units, to analyze a motion of the object, a synchronization signal sending unit which transmits a first synchronization signal group including N first synchronization signals in order from the first to the N-th sensor unit, and transmits a second synchronization signal group including N second synchronization signals in order from the N-th to the first sensor unit, with respect to sensor unit, and a reference synchronization signal generation unit which generates a reference synchronization signal which is to be a reference with respect to the first to N-th sensor units, based on the first and second synchronization signal groups received by sensor unit.

Abstract: A wireless communication device transmits a device beacon in accordance with a system timing of a wireless wide area network (WWAN). For one example, the beacon is transmitted relative to WWAN uplink channels of the time-frequency space of the uplink WWAN channel assignment. In response to the reception of the device beacon by another wireless communication device, a peer to peer communication session is established.

Abstract: An elastic gear First-In-First-Out (FIFO) buffer architecture is disclosed. The proposed elastic gear FIFO buffer uses a frequency monitor unit to control clock frequency compensation. By using an independent frequency monitor unit, the data latency and FIFO buffer size are best optimized. An elastic gear FIFO could be utilized in applications where clock compensation and asynchronous data width conversion are desired or required.

Abstract: A system including a first receiver that generates a first set of decoded codewords; and a first canceller that cancels, in response to any decoded codeword of the first set of decoded codewords failing CRC and a first decoded codeword from the first set of decoded codewords passing CRC, interference of a first codeword on a second set of codewords which includes the plurality of codewords and excludes the first codeword. The system further includes a second receiver that generates a third set of decoded codewords by decoding the second set of codewords; and a second canceller that cancels, in response to any decoded codeword of the third set of decoded codewords failing CRC and a second decoded codeword from the third set of decoded codewords passing CRC, interference of a second codeword on a fourth set of codewords.

Abstract: A time synchronization method in a wireless sensor network, a low power routing method using a reservation scheme, and an apparatus for performing the method are provided. The time synchronization method in the wireless sensor network may include: receiving a first synchronization request command packet from a parent node that manages time synchronization for a predetermined synchronization region; receiving, from the parent node, a second synchronization request command packet that has a transmission timestamp value of the first synchronization request command packet; and performing time synchronization for a child node based on a reception time of the first synchronization request command packet, a reception time of the second synchronization request command packet, and the transmission timestamp value of the first synchronization request command packet.

Abstract: In a communication system wherein a plurality of electronic devices connect and disconnect from communication over a medium and wherein the communication system has a protocol such that it is followed by the plurality of electronic devices when using the communication system, a probing device attempts to detect presence of a listening device and parameters associated with a connection to be set up between the probing device and the listening device by sending a probe request packet directed to the listening device and sending, from the listening device, a probe response packet in response to the probe request packet, wherein the listening device bypasses at least one step of the protocol when sending the probe response packet.

Abstract: The present invention discloses a digital self-timed timer for measuring the passage of time; a digital self-timed pulse generator for generating both continuous and finite pulse sequences; and a digital self-timed data receiver for recovering data from an asynchronous, two-wire bit-channel. Being self-timed, a disclosed self-timed timer measures time as a function of logic delays incurred while executing a sequence of internal state transitions. A pulse generator supports both a triggered pulse mode and continuous clock generation; pulse widths and pulse intervals are programmable. A data receiver may recover a data bit from each received two-bit code word and outputs recovered data and an associated write strobe for each recovered datum.

Abstract: A system including a first receiver module and a first interference canceller module. The first receiver module generates a first set of decoded codewords by decoding codewords in a received signal and determines if any of the first set of decoded codewords fails cyclic redundancy check (CRC). The first interference canceller module generates a second signal based on a first decoded codeword from the first set of decoded codewords when (i) any of the first set of decoded codewords fails CRC and (ii) the first decoded codeword passes CRC. By subtracting the second signal from the first signal, the first interference canceller module (i) cancels interference of a first codeword, which corresponds to the first decoded codeword, on a second set of codewords, which includes the plurality of codewords and excludes the first codeword and (ii) generates a third signal, which includes the second set of codewords.

Abstract: In one embodiment, a system is configured to generate a time reference where the system includes a bi-directional loop configured to have a first propagation speed in a first direction and a second propagation speed in a second direction, wherein the first propagation speed is substantially equal to the second propagation speed. In one embodiment, the system further includes a plurality of system elements coupled to the bi-directional loop, wherein each respective system element of the plurality of system elements is configured to determine a time reference common to each as an average arrival time at the respective system element of a first signal transmitted in the first direction over the bi-directional loop and a second signal transmitted in the second direction over the bi-directional loop.

Abstract: A multi-mode wireless communication device and multi-mode communication method are disclosed. The multi-mode device includes a first baseband co-processor configured to execute low-level stack operations of a first wireless communications protocol employed within a first wireless communications network. The device also includes a host baseband processor configured to execute a set of protocol stack operations of a second wireless communications protocol employed within a first wireless communications network and higher-level stack operations of the first wireless communications protocol. A data communication channel capable of carrying data received by the multi-mode wireless communication device from the first wireless communications network or sent by the multi-mode wireless communication device through the first wireless communications network is provided between at least the host baseband processor and the first baseband co-processor.

Abstract: Disclosed are a wireless communication system, method, and site controller for mitigating at least one of a transmission timing synchronization loss and a receiving timing synchronization loss at a base station. The method includes determining, at a first base station, a loss of a timing reference the timing reference is used by the first base station for timing synchronization of at least one of a transmission and reception of wireless data. The timing synchronization is predefined and common between at least the first base station and a second base station. The method further includes adjusting, in response to the determining, at least one of a transmit guard time and a receive guard time by at least one symbol time.

Abstract: A system for managing the simultaneous operation of a plurality of radio modems in a single wireless communication device (WCD). The multiradio control may be integrated into the WCD as a subsystem responsible for scheduling wireless communications by temporarily enabling or disabling the plurality of radio modems within the device. The multiradio control system may comprise a multiradio controller (MRC) and a plurality dedicated radio interfaces. Further, clock synchronization protection between the multiradio system controller, other modems and wireless communication devices with whom the wireless device is communicating may further be implemented as a protective measure to ensure a valid clock synchronization between all devices internal and external to the primary wireless device.

Abstract: With a method for synchronization in a communication system that includes a central participant and at least one further participant, at least one of the further participants being synchronized with the central participant, and, to this end, a telegram with synchronization information being transmitted by the central participant to the at least one further participant, particularly efficient synchronization of the at least one participant with the central participant results due to the fact that the telegram is a data telegram.

Abstract: A method is provided for maximizing utility of a media delivery network having a media source, a first media adaptor, a second media adaptor and a media renderer. The media source can provide data in a first format and a second format. The first media adaptor can receive the data in the first format from the media source. The second media adaptor can receive the data in the second format from the media source. The first media adaptor can further provide data in a third format based on the received data in the first format. The second media adaptor can further provide data in a fourth format based on the received data in the second format. The media renderer can render the data in the third format and can render the data in the fourth format.

Abstract: System and method for a four-slot asynchronous communication mechanism with increased throughput. The system may include a host system and a client device. The host may comprise a data structure with four (two pairs of) slots and first information indicating a status of read operations from the data structure by the host. The client may read the first information from the host. The client may read second information from a local memory. The second information may indicate a status of write operations to the data structure by the client. The client may determine a slot of the data structure to be written. The slot may be determined based on the first information and the second information and may be the slot which has not been written to more recently of the pair of slots which has not been read from most recently. The client may increment a value of a counter. The value of the counter may be useable to indicate which slot has been written to most recently.

Abstract: A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce the signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. Preferably, the destination port is in a first cross link multiplexer, the origin port is in a second cross link multiplexer, and the first cross link multiplexer is configured to convey the signal toward the second cross link multiplexer in more than one direction. In an embodiment, the signal is capable of being represented as a series of characters, and a character is capable of being represented as a number of bits. Preferably, the plurality of cross link multiplexers includes a delay buffer to delay conveyance of a first bit so that it remains substantially synchronized with a second bit.

Abstract: Methods and systems are provided for implementing an alternative timing source for low-cost-Internet-base-station-(LCIB) systems. In accordance with an embodiment, an LCIB has an internal clock. The LCIB is arranged to receive a GPS signal, and to treat timing information embedded in the GPS signal as the LCIB's primary source of timing information for calibrating the internal clock. The LCIB detects a loss of the GPS signal, and responsively uses a macro-network receiver to receive macro-network timing information from a macro network, which is a terrestrial wireless network. The LCIB uses the macro-network timing information to calibrate the internal clock.

Abstract: A time stamp adding device includes: PCR_PID detecting means for detecting a PCR_PID included in a PMT by searching TS packets included in a TS from the head of the TS including TS packets having no time stamp, input from the outside and transmitted in a MPEG2-TS format and analyzing the resulting PMT; PCR detecting means for detecting values of PCRs included between the head of the TS and the PMT and position information of the PCRs and detecting values of all PCRs in the TS packets between the PMT and the tail of the TS and position information of the PCRs in the TS; time interval calculating means for calculating a time interval for adding a time stamp and a value of the time stamp based on the PCR values; and time stamp adding means for adding the time stamps to the TS packets having no time stamp based on the time interval.

Abstract: Systems and methodologies are described that facilitate identifying peers based upon encoded signals during peer discovery in a peer to peer network. For example, direct signaling that partitions a time-frequency resource into a number of segments can be utilized to communicate an identifier within a peer discovery interval; thus, a particular segment selected for transmission can signal a portion of the identifier, while a remainder can be signaled based upon tones communicated within the selected segment. Moreover, a subset of symbols within the resource can be reserved (e.g., unused) to enable identifying and/or correcting timing offset. Further, signaling can be effectuated over a plurality of peer discovery intervals such that partial identifiers communicated during each of the peer discovery intervals can be linked (e.g., based upon overlapping bits and/or bloom filter information).

Abstract: A packet preamble search method is disclosed for locating a packet preamble with multiple predetermined patterns of a regular form within a received transmission signal with sequential multiple patterns. The pattern of the received transmission signal and the predetermined pattern of the packet preamble have the same length with even bits. The pattern of the transmission signal is sequentially compared with the predetermined pattern. A hit count is increased and a miss count is reset when the pattern of the transmission signal matches the predetermined pattern. The miss count is increased and the hit count is decreased when the pattern of the transmission signal does not match the predetermined pattern. The hit count and the miss count are reset when the hit count is less than or equal to the miss count. An address matching procedure is activated when the hit count exceeds or is equal to a threshold value.

Abstract: Disclosed herein is a time synchronizing apparatus for a mobile WiMAX analyzer. The time synchronizing apparatus includes a Global Positioning System (GPS) receiver and a synchronization control unit. The GPS receiver outputs a GPS signal that is synchronized with the GPS time using information received from a GPS satellite. The synchronization control unit compares the GPS signal and a reference signal, which is generated using an internal clock, and controls synchronization according to the result of the comparison. The synchronization control unit includes an oscillator, a divider, an offset comparison unit and a processor. The oscillator outputs an oscillation signal having a predetermined frequency. The divider divides the oscillation signal into the reference signal. The offset comparison unit compares the differences between the GPS signal and the reference signal, and outputs the result value of the comparison.

Abstract: A method is disclosed for recovering timing information between master and slave nodes interconnected over a packet network having an underlying time grid with a distinct granularity. A series timing packets are exchanged between said master and slave nodes to measure the time offset of the time grid relative to clocks at the master and slave clocks. This offset is then used to either adjust the local clock at the slave node, or generate the clock using a digital controlled oscillator.

Abstract: Systems, methods, and other embodiments associated with synchronizing link delay is provided. In one example system, a system for synchronizing signal communication between a first electronic component and a second electronic component connected by one or more serial communication links comprises an offset logic configured to apply a selected offset to signal transmissions to cause a unidirectional delay between the first and the second electronic components to be synchronized for both directions of signal transmissions. A synchronization logic is configured to determine the uni-directional delay for signal transmissions between the first and second electronic components and configured to control the offset logic to apply the selected offset.

Abstract: The invention relates to a method of synchronizing a mobile station with a base station in a wireless communications system, to a mobile station for a wireless communications system, as well as to a wireless communications system of this kind. In order to enable faster ultimate synchronization, it is proposed to compare components of the received data not only with a stored synchronization pattern, but also with a stored identification pattern prior to the adaptation of the timing of the mobile station to received data. Already before the synchronization it can thus be determined with a high degree of probability whether received data originates from a desired base station or not. The necessity of checking the contents of packets which are not associated with a desired base station can thus be avoided.

Abstract: A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce said signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. The signal is capable of being represented as a series of characters. A character is capable of being represented as a first data bit, a second data bit, and a control bit. A first interconnect is configured to convey the first data bit. A second interconnect is configured to convey the second data bit. A third interconnect is configured to convey the control bit. The third interconnect is positioned substantially between the first interconnect and the second interconnect.

Abstract: A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce the signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. Preferably, the destination port is in a first cross link multiplexer, the origin port is in a second cross link multiplexer, and the first cross link multiplexer is configured to convey the signal toward the second cross link multiplexer in more than one direction. In an embodiment, the signal is capable of being represented as a series of characters, and a character is capable of being represented as a number of bits. Preferably, the plurality of cross link multiplexers includes a delay buffer to delay conveyance of a first bit so that it remains substantially synchronized with a second bit.

Abstract: The invention provides a media synchronizing system capable of achieving various kinds of services synchronized with delivery of media to users. A synchronization data decoding unit 114 makes a reference to an internal clock 112, determines a command execution time from a synchronization data starting time recorded in synchronization data, and a command execution time period, decodes command types recorded in synchronization data 22, and sends command information to media synchronization command executing units 12-1 to 12-n. A command recognizing means 122 of the media synchronization command executing units 21-1 to 12-n recognizes a command from the received information, and sends execution instructions to a command executing unit 123. The command executing unit 123 operates based on the received execution instructions. A media receiving unit 13 restores and regenerates delivery data delivered from a media delivery service proprietor system 4.

Abstract: Mediation devices in an asynchronous network of low power consumption communication devices are leveraged through the use of new protocols (2500) that analyze relevant QoS parameters (2520) in order to provide a better than best effort service in the network. These protocols invoke adaptive quality of service (QoS) mechanisms to capitalize on the strength and flexibility provided to the network by the presence of one or more MDs, as described above. Expanded functionality of the MD includes control information messaging and service differentiation for the purpose of improving QoS of the network.

Abstract: In a signal generator, a peak value/peak position detection section detects value and position of an amplitude peak observed in modulation data coming from an orthogonal modulation section, and a peak carrier extraction section extracts L subcarriers capable of minimizing such an amplitude peak. A peak carrier generation section generates peak suppression data corresponding to thus extracted subcarriers, and a subtraction section subtracts the peak suppression data from the modulation data. A transmission signal generation section generates an analog transmission signal from the modulation data, and a peak suppression section generates an analog peak suppression signal from the peak suppression data. A signal synthesis section synthesizes the transmission signal and the peak suppression signal, and sends out the synthesis result to a wireless communications line via a transmission antenna. With such a structure, any amplitude peak found in a multicarrier transmission signal can be successfully suppressed.

Abstract: Described are a system and method for providing an interface to synchronize data transfers across clock domains. A first pulse converter receives a request signal in a first clock domain and converts the request signal into a synchronization signal in a second clock domain. A second pulse converter receives the synchronization signal in the second clock domain from the first pulse converter and converts the synchronization signal into an acknowledgment signal in the first clock domain. The pulse converters cooperate thus to perform a self-acknowledging handshake that synchronizes writes and reads to and from a FIFO memory, thereby effectuating the transfer of data across two clock domains.

Abstract: A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26) The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data.

Abstract: In a transmitting apparatus 101, there are provided PLL circuit 601 for generating high-speed clock signals up to 2m times (m being a positive integer) from a basic clock signal, and a clock generating circuit 600 for generating a communication clock signal (S-CLOCK) and a reception timing signal (S-LATCH*) as independent clocks of any time length with using the generated high-speed clock signal as the smallest unit.

Abstract: A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26). The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data.

Abstract: An output circuit of the present invention includes a data output circuit and a clock output circuit. The output circuit includes a first D-type flip-flop and a selector for selectively outputting an output from the first D-type flip-flop or second data according to a selection signal. The clock output circuit includes a second D-type flip-flop, a third D-type flip-flop, and a dummy selector circuit. The dummy selector circuit is connected to the second and third D-type flip-flops and outputs a clock signal by using the same elements as those of the selector in order to realize the same delay time as that of the selector.

Abstract: The invention concerns a method of checking the synchronization between at least two nodes Ni?1, Ni, with i=1, . . . , n in a network, each of said nodes having respectively an internal clock having a respective clock frequency Fi?1, Fi, wherein said method includes the following steps: a) transmitting the frequency Fi?1 of the internal clock from the node Ni?1 to the node Ni, b) comparing the frequency Fi?1 of the internal clock of the node Ni?1 transmitted to the node Ni with the frequency Fi of the internal clock of said node Ni, c) checking the synchronization between the nodes Ni?1 and Ni using the result of the comparison between the frequencies Fi?1 and Fi.

Abstract: A cellular communications system includes a base station and at least one mobile station communicating therewith. The base station may include a plurality of antennas and a modulator for providing a transmit signal for each antenna. The modulator may estimate a weighting factor for each transmit signal based upon considering each transmit signal as having an unknown and arbitrary fading factor associated therewith and based upon considering the unknown and arbitrary fading factors to have a predetermined cross-correlation function.

Abstract: A method of synchronizing wireless communication between computer (16) having a transmitter (24) and a peripheral device (50) having an amplitude modulated (AM) receiver (54) and at least one frequency modulated (FM) receiver (56) which communicates via radio frequency signals. The computer (16) partitions the data (28) into a plurality of data blocks (30), spreads the data blocks (30) over a plurality of frequency channels (38) within a predetermined range (70), and selects one of the channels (32) for transmitting the signal (40). The resulting signal (40) has increased and decreased frequency corresponding to the data block (30). The peripheral device (50) detects the signal (40) as being present and begins measuring a time period (64) with the AM receiver (54). The method is characterized by scanning the plurality of frequency channels (38) with the FM receiver (56) during the measured time period (64).

Abstract: A synchronous network traffic processor that synchronously processes, analyzes and generates data for high-speed network protocols, on a wire-speed, word-by-word basis. The synchronous network processor is protocol independent and may be programmed to convert protocols on the fly. An embodiment of the synchronous network processor described has a low gate count and can be easily implemented using programmable logic. An appropriately programmed synchronous network traffic processor may replace modules traditionally implemented with hard-wired logic or ASIC.

Abstract: System and method for synchronizing transaction data in real-time within a network environment. The system and method include and involve a plurality of authentication subsystems. Each authentication subsystem has a data storage subsystem and a processor. The processor is operative to receive a service request from a network user, and to authenticate the network user within the network environment in accordance with the service request. The service request causes a state stored within the data storage subsystem and related to the network user to change. The processor is further operative to transmit a synchronization request in real-time within the network environment, to receive another synchronization request from another authentication subsystem of the plurality of authentication subsystems, and to allow the processor to subsequently authenticate the network user within the network environment in accordance with the other synchronization request.